JPS6126164A - Controlling method of data transfer - Google Patents

Abstract

PURPOSE:To transfer directly data from a buffer in one controller to a buffer in the other controller through a system bus and to reduce the load of a CPU or the like by forming a buffer request line. CONSTITUTION:At the transfer of data from an apparatus A3 to an apparatus B5, the CPU1 issues a command to a controller A4 and data of one block in the apparatus A3 are transferred to the apparatus 5. At that time, the CPU1 sends the address specifying the controller 4 and a signal indicating the transferred apparatus 5 or the like to an address line, a data line and a command line. Consequently, the controller 4 outputs the address of a buffer memory 9, one-word data read out from a buffer memory 8 and a wirte command to the address, data and command lines respectively, and then writes the data on the data line in the specified memory 9. Namely, data can be directly transferred and the load of the CPU or the like can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a control method when data is transferred between a plurality of devices connected to a system bus.

[Prior art]

Figure 1 is a block diagram showing the conventional method, and in the figure (
1) is a central processing unit (hereinafter abbreviated as CPU), (2)
is the main storage device (hereinafter abbreviated as side), (3) is device A,
(4) is controller A that controls device A (3), (5
) is device B, (6) is controller B that controls device B (5), f7) is the system bus, (8) and (9) are the internal buffer registers of controller A (41, B (61), respectively. .Also shown by the dotted line in Figure 1, (a)
, C mouth), (c).

Those marked with (d), (e), and (f) represent control procedures.

Figure 2 shows the internal configuration of the system bus (7). In addition to the address line, data line, and command line, in which multiple bits are transmitted in parallel, there are 1-bit memory request signals, input/output request signals, and access signals. Includes memory request lines, input/output request lines, and access lines for transmission.

The procedures in FIGS. 1(a) to 1(f) will be explained using the case of transferring data from device A (3) to device B (5) as an example.

(b) The CPU (1) gives a command to the controller A (4) to transfer one block of data in the device A (3) to the IvIM
'[Transfer to J(2). At this time, the CPU (11) inputs an address specifying controller A (4) to the address line, inputs data to the data line indicating which address of MMUf21 should be the first address and how many words should be transferred, and inputs the data to the command line. The signal logic on the input/output request line is set to rlJ.

(b) Controller A (4) learns that the controller A (4) is designated by the signal on the address line, inputs the signals on the data line and command line, and indicates that this signal has been input by the signal on the aclude line. Logic “1”
and reports it to CPU (1), and then sends it to device A (3).
) is stored in the buffer memory (8), and the data stored in this buffer memory (January 8) is transferred and stored to the specified address location in the MMU (2) according to the instructions received in (a). do. During this transfer, controller A (4+ outputs a memory address to the address line of the system bus (7), takes out one word of data from the buffer memory (8) and outputs it to the data line, and commands ffM-
After outputting a memory write instruction to , the signal logic on the memo IJ IJ quest line is set to "1". On the other hand, MM
U(2) responds by setting the signal logic on the accrue line to "1" and writes the data on the data line to the location specified by the address on the address line in MIvIU(2).

(-・) Controller A (4) repeats the operation (b) and transfers all the contents of buffer memory (8) to MMU (2).
After the data transfer is completed, an input/output interrupt is generated to the CPU (11) to report that the data transfer has been completed.

(d) When the CPU (11) receives the transfer completion report from controller A (4), it sends MM to controller B (6).
A command is given to transfer data from device U (2) to device B (5). The method of this directive is the same as described in (a).

(e) Controller B (6) transfers data from MU (2+) to device B (5) via buffer memory (9).

The transfer method at this time is the same as described in (b).

(v) The controller B (6) generates an input/output interrupt to the CPU (11) when the transfer for the number of transfer words specified in (d) is completed.

As described above, data transfer between devices can be performed using conventional control methods.
Since this is done via the MU (2), it is necessary to secure an area on the MMU (2) to temporarily store the data, and a large amount of software processing is required to secure and release this area. In addition, in order to transfer one block of data between devices, the CPU (1> requires two input/output instruction commands and two input/output interrupt processing, which causes an increase in software processing time. There was a drawback.

[Summary of the invention]

This invention was made to eliminate the drawbacks of the conventional system as described above.
By providing a buffer request line for sending a signal from one controller to another controller to request data transfer, data can be transferred directly from one controller's buffer to the other controller's buffer via the system bus. It made it possible to do so.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or corresponding parts, and (71) is the system bus of the present invention. Also()).

Those marked with (ch), (υ), (nu), and (ru) represent control procedures.

FIG. 4 shows the internal configuration of the system bus (71), which differs from the system bus in that a buffer request line for transmitting a 1-bit signal is added.

The procedures in FIGS. 3 (g) to (l) will be explained using an example of transferring data from device A (3) to device B (5).

()) CPU (1) gives a command to controller A (4) to transfer one block of data in device A (3) to device B (
5). At this time, the CPU (11) sends an address specifying controller A (4) to the address line, and a signal indicating that the transfer destination is device B (5), the name of the block to be transferred, and the number of words to be transferred to the data line. , a signal indicating the transfer direction is sent to the command line, and the signal logic on the input/output request line is set to "1".

(H) Controller A (4) learns that the controller A (4) is designated by the signal on the address line, inputs the signals on the data line and command line, and indicates that this signal has been input by the signal on the aclude line. rIJ logic
Then, one block of data from device A (3) is stored in the buffer memory (8).

(S) Next, controller A (4) outputs the address of the buffer memory (9) to the address line, one word of data read from the buffer memory (8) to the data line, and a write instruction to the command line, and then The signal logic on the buffer request line is set to rlJ. At this time, the system bus (71)
Each of the above signals also reaches MMU (2), but since the signal logic on the memory request line is "0", MMU (2+) does not perform any operation. Controller B (6) The signal logic on the request line is rl
J and learns that the buffer memory (9) is specified by the address signal on the address line, and writes the data on the data line into the buffer memory (9) at the address position specified by the address signal on the address line. .

Figure 5 shows an example of the structure of the address signal on the address line in this case, assuming that 16 bits with bit numbers 15 to 0 are used, and the upper 4 bits specify the address of the transfer destination controller, and a maximum of 16 controllers are used. The lower 12 bits (which can be specified) indicate the address of the buffer memory within the controller. Therefore, in the example shown in FIG. 5, the buffer memo IJ (8), (9) has a maximum of 4.
It can have a capacity of 096 words. Furthermore, by changing the number of bits of the address signal, the maximum number of controllers and the maximum number of buffer memory words can be freely changed.

(NU) Controller B [6] is the buffer memory (9)
The contents of are transferred to device B (5).

When the transfer commanded from (l) CPUfl) to (g) [2 is completed, the controller (A) generates an input/output interrupt to the CPU (1) and reports the completion.

As described above, according to the method of the present invention, regarding data transfer between devices in the system, the CPU (II is the MMU (
2) Processing to secure/release a working area for data transfer is no longer required, the number of I/O command issues and input/output interrupt processing is reduced to the conventional number, and the number of times on the system bus (71) is reduced. The number of data transfers will be the same as before, and the CP
The load on U(1) can be reduced, and the load on the system bus (71) can also be reduced.

Further, when a data register is provided in the controller and one word of data is transferred between controllers using this data register, the present invention is applied considering that this data register is a buffer memory composed of one word. be able to.

Incidentally, in this specification, the description that the signal logic is set to "1" means that the signal logic is made significant.

〔Effect of the invention〕

As described above, according to the present invention, by adding a buffer request line, data is transferred directly between devices without going through the MMU, so the software in the CPU can be easily Therefore, the load on the CPU and the system bus can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the conventional method, FIG. 2 is a diagram showing the internal configuration of the system bus in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing the internal structure of the system bus, and FIG. 5 is a water-contact diagram showing an example of the structure of the address signal when the signal logic on the buffer request line is set to "1". (1)...CPU, (21...MMU, (3)...
...Device A (first device), (4)...Controller A ($1 controller), (51...Device B (second device), (6)...Controller B (second device) 2 controller), (71)...System bus, (8). (9)...Buffer memory respectively.

Claims (1)

[Claims] A system bus in which a plurality of devices are connected to a system bus to which a central processing unit and a main storage device are connected via respective controllers corresponding to each device, and data is transferred between the plurality of devices. In the data transfer control method, the step of providing a buffer request line in the system bus for sending a signal requesting data transfer from each of the controllers to any other controller; (this specified controller is the first controller), and the device controlled by the controller (this device is the first controller).
equipment designated by the above central processing unit (
a step of transmitting a signal instructing the device to transfer designated data to a second device) via the system bus; reading data specified by the first device from the first device and storing it in a buffer memory within the controller;
specifying a controller that controls the second device (this controller is referred to as the second controller) and sending a data transfer request via the buffer request line; A data transfer control method comprising the step of storing data in a buffer register in the second controller via the system bus.