JPS6143321A - Output device of pulse signal - Google Patents

Abstract

PURPOSE:To facilitate the easy change of an address outputting a pulse signal by making a constant part in an instruction sentence instructing the output of pulse signals offset for the address used for output of pulse signals. CONSTITUTION:A pulse signal output device is provided with an instruction recorder 1, instruction registers 2 and 3, pulse signal producing part 7, etc. The output timing of pulse signals is decided by the numerica value of a constat part in an instruction sentence 50 and outputted. In such a case, the numerical value obtained by adding the constant data 53 of a constant register 3 and the address data 54 is set to an address store part 8 for pulse signal address at a time point when a pulse generation control signal 9 is outputted. An address 61 of the contents of said numerical value is compared with the data 54 through an address comparison part 59. Then the data 54 changes gradually and an address coincidence signal 62 is outputted when the coincidence is obtained from said comparison. The part 7 outputs a pulse signal 60 by the signal 62.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pulse signal output device that outputs pulse signals under program control.

[Conventional magic]

Conventionally, a device of this type is shown in FIG. In the figure, (II is an instruction decoder that decodes instructions read from the program memory, (21 is an instruction register that stores the decoded instruction code, and (3) is a constant register that stores constants associated with the instruction. , (41 is a program counter that accesses the program memory and creates a memory address for reading the program memory t-, (51 is an arithmetic unit that performs each operation'X, (61 is an arithmetic register that stores the operation results, (7) is an i<t response creation unit for creating a pulse signal.

Also, among the signals sent and received between each part, (50) is a command statement that can be output from the program memory, (51) is a memory address for accessing the program memory, (
52) is the instruction code decoded from the instruction sentence (50), (
53) is constant data included in the instruction statement (50) and set in constant register (3), (54) is address data, (55) is operation data, (56) is processing data, (57) are data (53), (54), (5
5).

(56) is a data bus for transmission, (58) is various control signals, (59) is a pulse generation control signal in signal (58), and (60) is a pulse signal.

When a pulse signal is to be output at a desired timing, a pulse signal output command is placed in the address position corresponding to the desired timing in the program memory.

The program counter i41 is a memory address (s) that specifies the address of the instruction statement to be read from the program memory.
x) to access program memory. The memory address (51) is the address of the currently read data (instruction statement in the case of program memory) plus the number 1; it is output, but if it is specifically specified by the instruction being executed. is a constant register (
The contents of 31 are processed by the arithmetic unit (51) and the data is sent to the program counter (54) as address data (54).
The data specified by memory address (51), which is output as memory address (51) after 41 sessions, is read out as an instruction statement (5o), and the instruction part in that instruction statement (50) is an instruction. The decoder fil decodes the decoded instruction code (b't), and the decoded instruction code (b't) is stored in the instruction register (2).
is set to Further, the constant part in the instruction statement (50) is set in the constant register (31).

The instruction code (5) set in the instruction register (2)
Various control signals (58) are created depending on the contents of 2), but when the instruction code (5z) is a /( pulse signal output command, the pulse generation control signal (59) Ii ratio output,
In response to this, the pulse signal generator (7) sends 7. A pulse signal (6 (J)) is output.

This pulse signal (60) is used for checking the operation of the program, controlling other devices, etc.

Since the conventional device is configured as described above, it has the disadvantage that it is difficult to change the timing of pulse signal output. In other words, in order to change the timing of pulse signal output, it is necessary to change the address in the program memory of the command statement that commands pulse signal output, and this address change inevitably causes address changes of other command statements. Address changes are time-consuming, and measures must be taken to ensure that such changes do not cause errors in the operation of programs stored in program memory. There were drawbacks.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. In this invention, the timing of pulse signal output is determined by the value of the constant part in the instruction statement that commands pulse signal output. It is easy to rewrite the numerical value of the constant part, and therefore it is also easy to change the timing of pulse signal output.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, (8)
(9) is an address comparator, (61) is a pulse signal output address, and (62) is an address match signal.

The operation up to the output of the pulse generation control signal (59) from the instruction register (2) is the same as that described with reference to FIG. When the signal (59) is output, the constant register (3
1 (i.e., constant data (53)) and the contents of program counter (4) (i.e., address data (54)).
)) and the total added value are set in the pulse signal output address storage section (8). The comparator (9) compares the pulse signal output address (
61) and address data (54), and when the address data (54) changes sequentially and matches the pulse signal output address (6e), an address match signal (62) is generated.
outputs. In response to the address match signal (62), the pulse signal generator (7) outputs a pulse signal (60) t-.

Note that in the above embodiment, the pulse signal output address storage section (
8) contains address data (54) and constant data (53)
The constant data set in the constant register (3) is Adnos Offset) (addr
ess off-set ) value, but the imperative statement (50
) may contain the address itself for outputting the pulse signal and set it in the constant register. In this case, the constant data (53) of the constant register (3) is stored in the pulse signal output address storage section (8) by the pulse generation control signal (59).

Further, in the above embodiment, the pulse signal generator (71) is driven only by the address match signal (62), but it is driven by the logical sum of the address match signal (62) and the pulse generation control signal (59). You can also do this.

Furthermore, a pulse signal generator driven by the pulse generation control signal (b9) may be provided separately. In this case, the pulse signal output output from the separately provided pulse signal generation section and the pulse signal output output from the pulse signal generation section (7) shown in Fig. 2 may be used appropriately, or they may have different pulse widths. It can be a pulse.

〔Effect of the invention〕

As described above, according to this invention, the constant part in the command statement for commanding pulse signal output is used as an address offset for pulse signal output, making it easy to change the address at which the pulse signal is output. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention.・(2)・・
・Instruction register, (31...Constant register, (41・
...Program counter, (7)...Pulse signal creation section, (81...Pulse signal output address storage section, (9
)...Address comparison unit, (50)...Instruction statement, (5
1)...Memory address, (52)...Instruction code, (53)...Constant data, (54)...Address data, (59)...Pulse generation control signal, (bO)
...Pulse signal, (61)...Pulse signal output address, (62)...Address match signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a pulse signal output device that outputs a pulse signal under program control, an instruction statement including an instruction code for commanding the output of the pulse signal and a constant for determining the timing for outputting the pulse signal is stored in a predetermined location in the program memory. a program counter that sequentially generates memory addresses for accessing the program memory; and when the instruction statement is read, the instruction code is set in the instruction register and the constant is set in the constant register. means for setting a numerical value determined by the contents of the constant register into a pulse signal output address storage section by executing an instruction determined by an instruction code set in the instruction register; a memory address of the output of the program counter and the pulse signal; A pulse signal output device comprising: an address comparison section that compares the contents of an output address storage section; and a pulse signal generation section that outputs a pulse signal in response to a comparison match signal from the address comparison section. .