JPH0323938B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a branch address generation method that dynamically generates a branch address for an added option program without requiring a processing program. Programs related to I/O control, language, etc. are often options, and in order to combine such an option program with a basic program, the next instruction of the branch part of the option program in the basic program must be set as a program exception. If an option program has been added when the instruction in the branch part is read out, then the address is changed to point to the starting area of the option program. Conventionally, this changing process has been carried out by preparing a processing program called linkage or the like, which has had the disadvantage of making the operation of adding an optional program complicated. The present invention aims to easily generate a branch address for an option program without requiring a processing program. The present invention has a main memory block storing a basic program, and a sub memory block storing an optional program is added as necessary. The branch destination address of the branch instruction from the basic program to the option program is set to a predetermined location in the main memory block, and a predetermined instruction is stored in the predetermined location. checks the AND condition between the decoding result of the branch instruction and the signal indicating the implementation state of each of the sub-memory blocks, and if the AND condition is not satisfied, executes the predetermined instruction, and checks whether the AND condition is satisfied. In some cases, implementation information is incorporated to modify the branch destination address section of the branch instruction so as to access the sub-memory block indicated by the branch instruction. This will be explained in detail with reference to examples. FIG. 1 is an explanatory diagram showing one embodiment of the present invention. MEM is a memory that stores various programs and consists of multiple blocks BL ₀ , BL ₁ . . . These multiple memory blocks BL ₀ , BL ₁ . . . are each formed on a different printed circuit board, and each is a main memory block that stores at least a basic program.
If BL ₀ is implemented, the general function as an information processing device will be fulfilled. On the other hand, BL ₁ ,
BL ₂ , ... is a secondary memory block that stores optional programs used in combination with the basic program, such as a fortrun compiler.
Implemented as needed. Main memory block BL ₀
In the basic program, if sub memory block BL ₁ is not implemented, the next address part of the instruction read from area AR ₁ (next to this instruction moves to the program in BL ₁ ) is in the same main memory block BL ₀ . Indicate other areas AR ₂ . This area AR ₂ stores "program exceptions," where execution of the basic program is interrupted and waits for appropriate processing by an operator or the like. On the other hand, when the secondary memory block BL ₁ is implemented, the next address part of the instruction read from the area AR ₁ of the main memory block BL ₀ is the start area of the option program in the secondary memory block BL ₁ .
If you can modify it to point to AR ₃ ,
This option program is AR ₁ of the basic program without requiring any processing programs such as linkage.
It will be automatically executed following the area instruction. In this example, this branch address generation (modification) is attempted to be easily performed by the address generation circuit CONV. In Figure 1, the instruction read from any block of memory MEM is stored in the instruction register.
The address is taken out to REG ₁ , and the address is sent to the address generation circuit CONV and the generation address register.
REG ₂ and instruction address register REG ₃ are used again to access the memory MEM. If the address is not a branch address to the option program, it passes through the address generation circuit CONV. On the other hand, when _the branch address is the branch address, _{the implementation information C 1 ,}
C ₂ , modified according to... Decode the operation code OP in the instruction register REG ₁ using the instruction decoding circuit DEC to determine whether the address retrieved from the memory MEM is a branch address to an option program and which option program it is a branch address to. I understand.
When it is determined that the address is the branch address, the address is modified for jumping to the sub-memory block. For this purpose, the address part of the instruction contains an address part for the optional program.
Set up opt. The opt part of the instruction taken out from area _AR1 is set to 0, for example, and this address opt=0 is changed depending on whether the option program is implemented. FIG. 2 shows a specific example of the address generation circuit CONV. The instruction register REG ₁ has one to several extra bits between the part where the operation code OP is written and the part where the next address is written, and the instruction register REG 1 has one to several extra bits between the part where the operation code OP is written and the part where the next address is written. Store. In this example, the next address is 4 bits _b0 to _b3 , the number of sub memory blocks to be added is 3, and 3 bits of address bits (opt) _b4 to _b6 are prepared. This additional bit
b ₄ to b ₆ are input to the generated address register REG ₂ through OR gates OR ₁ to OR ₃ . On the other hand, the original next addresses b ₀ to b ₃ are passed through and input to the register REG ₂ . or gate
The other input of OR ₁ ~ OR ₃ is an AND gate AND ₁ ~
This is the output of AND ₃ . This and gate AND ₁ ~
AND ₃ is input to register REG 2 b 4 when the operation code OP is not an optional program branch instruction (i.e., a general instruction or a branch instruction into the basic program) because it is all closed by the decode circuit _{DEC .} ~b ₆ are all 0''.
In other words, when the address in register REG ₁ is not a branch address, the address is not modified in any way by this address generation circuit CONV. On the other hand, if the operation code OP is a branch instruction of an option program, the decode circuit DEC decodes which option program it pertains to and outputs the AND gate AND ₁ ~
Only one of AND ₃ is open. The other input of AND gates AND ₁ to AND ₃ is a sub memory block that stores different option programs.
Implementation information C ₁ to C ₃ of BL ₁ to _{BL 3} is derived. This mounting information C ₁ to _{C 3} is a signal generated when the printed circuit board and the connector are connected when the sub memory blocks BL ₁ to BL ₃ are mounted, or a signal from an identification signal generator provided in advance on the printed circuit board. (This signal is sent by inserting a printed board). For example, when it is not mounted, it is 0", and when it is mounted, it is 1".
Let's set it so that In this way, when the secondary memory block BL ₁ is installed, C ₁ = 1, so
When a branch instruction for option program 1 is loaded into register REG, an AND gate is executed.
AND ₁ becomes open and b ₄ of the additional bits b ₄ to b ₆ becomes 〓1''. In the same way, the sub memory block BL ₂
is implemented, C ₂ = 1, so
When a branch instruction for option program 2 is loaded into register REG ₁ , an AND gate is executed.
AND ₂ becomes open and b ₅ =1. The table below shows the modification state of branch addresses by this address generation circuit CONV.

【table】

Claims (1)

[Scope of Claims] 1. In a branch address generation method for a basic program in a computer system that is equipped with a main memory block storing a basic program and a sub-memory block storing an optional program is added as necessary, The branch destination address of a branch instruction from the basic program stored in the memory block to the optional program is a predetermined location within the main memory block,
In addition, a predetermined instruction is stored in the predetermined location, and when executing the branch instruction, an AND condition is performed between the decoding result of the branch instruction and the signal indicating the mounting state of each of the sub-memory blocks. If the AND condition is not satisfied, the predetermined instruction is executed, and if the AND condition is satisfied, the implementation information is taken in and the branch destination address part of the branch instruction is changed to the branch destination address part of the branch instruction. A branch address generation method characterized in that the branch address generation method is modified to access a sub-memory block shown in FIG.