JPS581245A - Branch address producing method - Google Patents

Abstract

PURPOSE:To branch to an optional program easy, by constituting a sub-memory block to a form modified accessibly at an address section of the instruction of a branch section fetching the loading information when the sub-memory block is loaded. CONSTITUTION:A memory MEM stores various programs and consists of blocks BL0, BL1... and each block is formed on a different printed board. An instruction read out from any block of the memory MEM is fetched to an instruction register REG1, and its address is used for the address of the memory MEM again through an address producing circuit CONV, a produced address register REG2, and an instruction address register REG3. When this address is not branched to the optional program, it passes through the circuit CONV. When this address is the branched address, the address is modified with loading information C1, C2... of blocks BL1, BL2....

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a branch address generation method that dynamically generates a branch address for an added option program without requiring a processing program.

I10 Control-related programs, language-related programs, etc. are often made optional, and in order to combine such optional programs with the basic program, it is recommended that the next instruction of the branch part of the optional program in the basic program be As an exception, if the instruction in the branch part is read and an optional program has been added, the address is then changed to point to the top area of the optional program. Conventionally, this changing process has been performed by preparing a processing program called linkage or the like, which has the disadvantage that adding an optional program becomes complicated.

The present invention aims to easily generate a branch address for an option program without requiring a processing program. The present invention provides a branch address generation method for a basic program in a computer system that is equipped with a main memory block storing a basic program, a sub memory block storing an optional program, and additional memory as necessary. The branch destination of a branch instruction from a basic program to an optional program is a specified location in the main memory program if the corresponding sub-memory program is not implemented. In some cases, the implementation information is incorporated to make the address part of the instruction of the branch part modified so that the wrinkled submemory block can be accessed.
This will be explained in detail below with reference to the illustrated embodiments.

FIG. 1 is an explanatory diagram showing one embodiment of the present invention.

MgM is a memory that stores various programs, and consists of a plurality of programs. These multiple memory blocks BL・*B IJI
+ . On the other hand, BLI,
BI, . . . are sub-memory blocks that store optional programs used in combination with the basic program, such as a Fortran compiler, and are implemented as necessary. In the main memory pro-BI4 basic program, if the secondary memory pro-2 BL is not implemented, the instruction read from area AR (the next instruction is BLI).
The next address part of the program (moving to the next program) is another area AR in the same main memory processor or BLe.

instruct. This area AR wing stores a "program exception", at which the execution of the basic program is interrupted and waits for appropriate processing by an operator or the like.

On the other hand, when the secondary memory block BL is implemented, the next address part of the instruction read from the area AR of the main memory block BI4 is the sub memory block BL.
If it is possible to modify the start area ARst of the option program of , without the need for a processing program such as linkage, the option program can be modified to indicate the AR of the basic program.

It will be automatically executed following the area instruction. In this example, this branch address generation (modification) is attempted to be easily performed using the 'fI near address generation circuit C0NV.

In Fig. 1, an instruction read from any of the memory IJ MgM processors is taken out to the instruction register REGI, and the addresses of these are address generation circuit C0NV, generation address register RIG, instruction address register REG.
, is used again to access the memory MEM.

If the address is not a branch address to the option program, address generation circuit C0NVi is passed through. On the other hand, when it is a scissors branch address, it is a secondary memory processor.

Implementation information for B Ll e B Lm e-1 C1e
Modified according to C1e...-. Whether the address taken out from memory MKM is a branch address to an option program and which option program it is is determined by the operation code in the instruction register REG.'OPt instruction decode circuit DEC.
You can see it by decoding it. When it is determined that the branch address is the branch address, the ninth address modification for jumping to the memory block on the corresponding side is performed. For this purpose, an address section optf for an option program is provided in the address section of the instruction. For example, set the aptlllltf of the friend command to be fetched from the domain R1 to 0, and use this address *
pt=O is optional.

Changes may be made depending on the implementation of the program.

FIG. 2 shows a specific example of the address generation circuit C0NV. The instruction register REGI has one to several extra bits between the part where the operation/encode OP is written and the part where the netast address is written, and the memory Mi
l: Stores the address part t of the read friend instruction from M. In this example, the netast address is 4bit y) b・~b3,
Assuming that the number of memory processors to be added is 5, 5 address bits (pt) ba to b@t' are prepared. These additional bits b4 to b- are OR gates OR, ~OR,'
The generated address register REGmK is input through i. On the other hand, the original next address b.about.bs is input through the V register RKGmeC. The other input of the OR gate ORI~OR is the antgame N
This is the output of D, ~ ND. This and gate AND
1 to AND3 are all closed by the decode circuit DECK when the operation code OP is not a branch instruction, so the inputs b4 to b- to the register RBG are all @
0". In other words, when the address in register RIG is not a branch address, the address is not modified in any way by this address generation circuit C0NV.

On the other hand, if the operation, code OP is a branch instruction, the decoding circuit DEC decodes which option program it relates to, and
Only one of ANDI is left open. The other input of Antogame NDI to ANDI has different options, l
/Nine secondary memory blocks RLI to BL for storing programs
Implementation information C1 to CI of I is derived. This implementation information C
1 to Cs are sub-memory processors, and signals generated when the printed circuit board and connector are connected when BLI to BLst are mounted, or signals from the identification signal generator provided in advance on the printed circuit board (when the printed circuit board is inserted). (This signal is sent by inserting the
Set it to be @1' during implementation. In this way, when the sub-memory program, BL, is implemented, CI=1, so when the branch instruction for option program 1 is taken into the register REG, the AND gate AN
DI is open and b4 of additional bits b4 to b6 becomes “
Similarly, if the secondary memory block BL is installed, it becomes 0s-1, so the register RI
When the branch instruction for option program 2 is taken into G, the Android ()AND is open.=
It becomes 1. The table below shows the modification state of branch addresses by this address generation circuit C0NV.

As shown in the table above, the basic program sets the upper 3 bits of the address to 000, and the lower 4 bits to 0000.
to 1111 and access the main memory program, BLII. On the other hand, option program 1 fixes the upper 3 bits of the address to 001 and the lower 4 bits.
It is obtained by accessing the sub memory block BL1f by changing the bits and bits within 0000 to 1111, and the multi-sign program 2 sets the upper 5 bits of the address to t-010, and the lower 4 bits) to t-0000 to 1111. Change it with Vice Memory Pro,
This is obtained by fully accessing the BL, and although not shown in the table above, option program 3 and the like also apply.

If such an address generation circuit C0NVi is used, the branch address to be accessed, for example, the area Act of the main memory block BL in FIG. *It is possible to modify the program so that it is accessed (the same applies to other optional programs), and a separate processing program is required when connecting the optional program to the basic program.1. do not have.

As described above, according to the present invention, the option, /prog2
This has the advantage that a branch address to a system can be easily generated without requiring a processing program.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention, and FIG.
The figure is a configuration diagram showing a specific example of an address generation circuit. In the figure, BLo is the main memory pro, BL Otori IBL! is the sub memory block, C0Nv is the address generation circuit, CI
+ CB is implementation information. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1￥EM Figure 2

Claims (1)

[Claims] In the branch address generation method in the basic program of a computer system, the main memory block that stores the basic program, the main memory block that stores the program, and the sub-memory block that stores the optional program can be added as needed. The branch destination of a branch instruction to a program is a specified location in the main memory block if the corresponding sub-memory program is not implemented, and if the sub-memory program is installed, its implementation information Insert the address part of the branch instruction,
A branch address generation method characterized in that a core sub-memory processor is made accessible and in a friend form.