JPS6215643A - Memory control circuit - Google Patents

Abstract

PURPOSE:To always keep the writing cycle of an arithmetic processor MPU minimum by providing a control signal producing circuit for data bus period of the MPU which masks the MPU for a certain period when the MPU executes a TAS instruction. CONSTITUTION:A control signal generating circuit 21 contains a NAND circuit 10 and an FF circuit 11 and produces the inverse of DTACK signal through an inverter 5. The input signal RASC of the circuit 11 is set an active H at a time point t2. While the output signal, the inverse of CLK, is kept inactive H at and after the point t2. Therefore the output of the circuit 11 changes between time points t2 and t3, i.e., at the rise of S4 of the CLK signal. Then the inverse of DTACK signal is set at an active L. When an MPU2 detects the inverse of DTACK signal, no WAIT period SW is inserted at a time point t4 with the state of S6 kept since the inverse of DTACK is active. The writing cycle is through at the next time point t5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory control circuit for a burner computer, a work stage, etc., and particularly to control of the bus cycle of an MPU.

[Background of the invention]

In a computer system consisting of a processing unit (MPU), memory, memory control circuit, etc., when the MPU exchanges data with the memory, the following methods have been conventionally considered as circuits to control the MPU bus cycle. Ta.

FIG. 2 shows an example of this. In the figure, the memory timing generation circuit 1 includes an arithmetic processing unit (MP06).
8000 (hereinafter abbreviated as MPU) 2 generates signals necessary for exchanging data with memory 3. Signal D
TACK is a signal that controls the bus cycle period of the MPU 2 when the MPU 2 writes (writes) data to the memory 3, reads data, etc. The RA8C signal becomes active when the MPU 2 accesses the memory 3 by passing the A8 signal output from the MPU 2 (a signal indicating that the address signal on the address bus 51 has been finalized) and the signal on the address bus 53 through the decoder 4. .

The inverter 5 is of an open collector type, receives the RASC signal output from the memory timing generation circuit 1, and outputs a DTACK signal. Sled, -C1D'1ACK
The signal passes through the MPU bus and control bus to MPU2.
connected to.

In addition to write cycles and read cycles, the MPU68000 series has a read-modify-write cycle when exchanging data with memory. A read-modify-write cycle is performed when the MPU 2 executes a TAS instruction.

This TAS instruction is an effective instruction when referring to common memory in a multiprocessor system.

FIG. 5 shows a timing chart when the TAS instruction is executed by the circuit shown in FIG. WI2. In order to indicate the passage of time, the time number tI + "@..." is written.

Below, using the timing chart in Figure 5,
The method of controlling the bus cycle period of TA and the circuit shown in Figure 2.
We will discuss some inconveniences that occur when executing the S command.

The CLK signal in FIG. 3 is a signal that drives the MPU 2, the DS signal is an output signal of the MPU 2, and is a signal that becomes active when valid data is determined on the data bus 52 (data confirmation signal). Equal to the signal in the figure. C.L.
1 above the K signal to make it easier to explain the status of MPU2.
(Similarly, in the timing charts from Figure 3 onwards, So, S, etc. are written above the time number and CLK signal. ...
). The MPU 2 detects the DTACK signal at the falling edge of 84 of the CLK signal.

That is, if the DT input CK signal is inactive ('H') at the falling edge of S4, then the MPU2 is in the 86 state at t4 following time number [3], the state S3w is inserted; As shown in FIG. 6, if the DT ACK signal is in the active ('L') state, the MPU 2 enters the S state at time number t4.

The above-mentioned 8w state is the WAIT state of MPU 2, and is used during the MPU bus cycle period when the target that exchanges data with the MPU, such as memory or I10 device, cannot correctly exchange data during the MPU's basic bus cycle period. inserted to extend the

In the circuit shown in FIG. 2, the following problem occurs when the TASi instruction is executed. DrACK signal active ('L')
According to the MPIJ2 standard, the timing at which the signal changes from ) to inactive ('H') is determined to be within several hundred ns after the signal changes to inactive ('H'). However, in the circuit shown in Figure 2, the DTACK signal is RA8C
The RASC signal is determined by the /'y8 signal, that is, when the As signal changes to active (inactive), the RASC signal also changes to active (inactive). Therefore, the DTACK signal is also determined by the As signal. Therefore, the above-mentioned standards of MPU2 cannot be satisfied. In the read-modify-write cycle of the MPU2 during the 'I' A 8 instruction, the Ds signal becomes active twice while the As signal is active ('L'). 6 (In Figure 3, only the first active timing of the D8 signal is shown.) Next, Figure 4 shows an example of a circuit that does not have the defects caused by the circuit in Figure 2. show.

In the circuit of FIG. 4, the RASC signal is functionally the same as the RASC signal of FIG. 2, except for the polarity.

The circuits in FIG. 4 and FIG. 2 are the same except for the DTACK signal generation circuit. In this circuit, even if the delay circuit 7 is removed, the WAIT state Sw may be forced into the write cycle and read-modify-write cycle of the MPU 2, and there is a problem that it is unsuitable when high-speed processing is desired at all times. The explanation is given below.

In the case of this circuit, when the MPU 2 writes data to the memory 3, the DTACK signal is activated ('L') when the DS signal is
After changing to , it passes through the delay circuit 7 and becomes active (,'L
). A timing chart of this write cycle is shown in FIG. In FIG. 5, CLK (
Since the DTACK signal is inactive ('H') at the falling edge of fi number s4, the WA
IT 3w is inserted.

DTACK signal is active (・L・
) Therefore, at time number t, the LCK signal becomes a turtle, which is the last state of the write cycle. In order to make MPU2 perform high-speed processing, select high-speed MPU2 and drive C
When the LK signal is set to the highest frequency of MPU2, according to the MPU2 standard, the DS signal changes to active (j) when MPU2 writes at the MAX value, which is 8 at time number t3.
4, the WAIT period Sw is inserted when the DTACK signal is activated from the active timing of the DS signal. In order not to insert the WAIT period 8w, it is necessary to activate the DTACK signal before the number of falling edges of S4 + ns (this value is determined by the D of MPU2).
(Defined by TACK signal detection and door knock time)
.

Insertion of the WAIT period 8w lengthens the write cycle period of the MPU 2 and takes processing time accordingly. In addition, when a high-speed access time becomes available as Meshiri 3, the MPU2 bus cycle (light cycle/I/
, read cycle, read-modify-write cycle).

FIG. WI6 shows a timing chart of the read cycle of the circuit of FIG. 4. Unlike the write cycle in FIG. 5, the timing at which the D8 signal changes to active ('L') is similar to that of the As signal and is earlier than the write cycle. The timing at which the DTACK signal changes to active ('L') is after the RA8C signal becomes active (both L') from the input S signal and passes through the delay circuit 6.In this circuit, one WAIT period Sw is inserted. However, depending on the internal configuration of the delay circuit 6, it is also possible not to insert the WAIT period.

Next, we will describe how the TAS instruction is executed in the circuit of FIG. FIG. 7 shows a timing chart of the read-modify-write cycle of the circuit shown in FIG. 4.

In Figure 7, the DS signal is active ('L) at time number 'v6'.
') to inactive ('H''), DTA
The CK signal also changes to inactive ('H'). This is the circuit shown in Figure 4, where the DS signal is inactive ('H).
This is because the NOR circuit 8 changes to 'L' when it changes to 'L', and the output of NAND 9 changes to 'H' through the delay circuit 7. On the downlink, detect the D'['ACK signal of the write operation during the read modify cycle period.
In the figure, when the CLK signal signal S at time number ttt falls, D
Since the active state ('L') of the TACK signal is detected, the CLK signal goes low at the next time number t8.

We have now reached the final state of this cycle.

As mentioned above, in the circuit example of FIG. 2, MPU2 is TA
When executing the S instruction, an inconvenient problem occurs, whereas in the circuit example shown in Figure 4, no problem occurs when executing the TAS instruction, but when the MP
This is inappropriate when it is desired to always execute the U2 bus cycle without inserting WAIT' (especially during a write cycle).

[Purpose of the invention]

An object of the present invention is to provide a memory control circuit that satisfies the following two points.

■ MPU bus cycle (read cycle).

write cycle, read defy write cycle)
is always the minimum period.

■ After the data confirmation signal αji) changes to inactive at the time of Ml'U's TAS command, the MPU
The control signal (DTACK signal) during the data bus period is made inactive to ensure reliable operation.

[Summary of the invention]

The present invention generates a control signal for the data bus period of the MPU from a memory access signal, which is one of the output signals of a memory timing generation circuit, and uses the data confirmation signal and read signal of the iPU to cause the MPU to issue a TAS command. This goal was achieved by providing a circuit that masks only a certain period of time during execution.

[Embodiments of the invention]

A first embodiment of the present invention will be described below with reference to FIG.

The MPU 2, memory 3, decoder 4 of the memory control circuit, and memory timing generation circuit 1 are the same as those shown in FIGS. 2 and 4 as conventional examples. The control signal (DTACK signal) generation circuit for the data bus period of the MPU is different. N
An AND circuit 10, a D-type F/F circuit 11, and an inverter 5 generate a DTACK signal. Further, the output of the F, F circuit 11 is input to the memory timing generation circuit 1 for use in generating memory timing.

Next, the operation will be explained with reference to timing charts for the write cycle, read cycle, and read modify write cycle of the MPU 2.

FIG. 8 shows a timing chart of write cycle y of the MPU 2. The 6R and A8C signals are determined by the A8 signal output from the MPU 2 as described in the conventional example, so the timing is as shown in the figure. F- at time number t.
The input signal of the F circuit 11, the RA8C signal, is active ('
In addition, the output signal CI of the NAND circuit 10
, Mr. issue and Hata Tou issue t, hereafter inactive (')i'
) condition continues. Therefore, between time number [, and t,
In other words, at the rising edge of CLK signal 84, FF' circuit 1
1's output changes, and the D'rACK signal becomes active ('
L'). When the MPU 2 detects the DTACK signal (fall of 84 of the CLK signal), the DTACK signal is active, so at time number t4, the WAIT period SW is not inserted and the state is 86, and at the next time number t, the write cycle is started. It's finished. In this case, it is necessary to activate the DTACK signal before the MPU2 detects the DTACK signal (falling edge of S4) (the MPU2 set-up time standard), but this circuit does not meet this standard value. be satisfied. It also satisfies the specified value of the MPU 2 when the DTACK signal changes from active ('L') to negative ('H') (within several hundred ns after the As signal and DS signal change to negative).

Figure WJ9 shows a timing chart of the read cycle of the MPU2. The timing at which the DTACK signal changes to active ('L') is the same as the read cycle in FIG. ' ). In this read cycle, similarly to the write cycle, the WAIT period is not inserted and is executed in the minimum time. Also, there is no timing when the specified value of the MPU 2 is not satisfied.

FIG. 10 shows a timing chart of the read-modify-write cycle of the MPU2. At this time as well, paying attention to the DTACK signal, the time numbers t1 to t change at the same timing as the read cycle in FIG. After that, at time number t, when the R/W signal changes to 'L' (indicating a write cycle), the CLR signal becomes inactive (
'H'), so the DTACK signal changes to the S level of the CLK signal. It changes to active ('L') at the rising edge of . Then, the DT input CK signal is inactive ('H')
The R&8C signal changes to inactive ('H
) immediately after the next CLK signal rises. Therefore, the problem (D
The time from when the 8 signal changes to inactive to when the DTACK signal changes to inactive exceeds the specified value of the MPU2. ), and the read-modify-write cycle is executed in the minimum period without inserting a W input IT period.

As a result of the above, in the circuit shown in Fig. 5, the MPU2 bus cycle/
It is possible to always execute L/ (read cycle, write cycle, read modify write cycle) in the minimum time and to reliably execute the 'rA8 instruction.

Further, the output signal of the FF circuit 11 is very effective when the memory timing generation circuit 1 generates the memory control 57 and memory address 5B signals. For example, the memory 3 is a DRAM (Dynamic Random Access
ss Memory), address switching (
It can be used for the generation signal of R, OW address and COLUMN address) signal, or RAS signal (connected to the RAS terminal of CDRAM).

Other embodiments are shown in FIGS. 11 and 12.

The circuit of the second embodiment shown in FIG. 11 differs only by changing the polarity of the circuit shown in FIG. 1, the CLR terminal, and the PR terminal.

In the circuit of the third embodiment shown in FIG. 12, the DTACK signal is A in the write cycle and read cycle of MPU2.
In the read-modify-write cycle during the nTAS command, which is determined by the s signal and can always be executed in the minimum time, the read period (the first active state period of the DS signal) and the write period (the second active state period of the D8 signal) During the active state period), the output signal of the NAND circuit 10 becomes active (Lj), so the D'rACK signal becomes inactive ('H'). Then, during the write period, the output signal of the NAND circuit 10 becomes inactive (
'H'), so the D'rACK signal becomes active ('L') again. In this way, NAND circuit 1
1 serves to mask the DTACK signal during read-modify-write, similar to the circuit of the above-described embodiment.

Furthermore, the MPU 2 also processes the read-modify-write cycle in the minimum time.

〔Effect of the invention〕

According to the present invention, there are the following two effects.

■ The MPU's bus cycle A/(R, cycle write cycle, read modify write cycle/I/) is always kept at the minimum period, so the MPU processing becomes faster. After changing to active, the MPU's data bus period control signal (DTAeK signal) is made inactive within the specified range of the MPU, resulting in reliable operation and increased reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of a memory control circuit according to the present invention, FIGS. 2 and 4 are block diagrams of a memory control circuit according to the prior art, and FIG. 3 is a timing diagram of the block diagram of FIG. 2. Chart diagrams, Figures 5, 6, and 7 are timing charts of the configuration diagram in Figure 4, Figures 8, 9, and 10 are timing charts of the configuration diagram in Figure 1.
Timing chart diagrams of the configuration diagrams in Figures 11 and 12
The figures are configuration diagrams of second and third embodiments of the memory control circuit according to the present invention, respectively. 1...Memory timing generation circuit, 2...
...Arithmetic processing unit (MPU), 3...Memory, 4...Decoder, 10...NAND circuit, 11...D type Furi, P. Flop circuit, 20・
...Memory control circuit, 21...Control signal generation circuit. Ding

Claims (1)

[Claims] 1. A memory control circuit consisting of at least a decoder that decodes the address of an MPU (arithmetic processing unit), a memory timing generation circuit that supplies a signal to the memory, and a control signal generation circuit for the data bus period of the MPU,
A control signal for the data bus period is generated from a memory access signal that is one of the output signals of the memory timing generation circuit, and when the MPU executes a TAS instruction using a data confirmation signal and a read signal of the MPU. . A memory control circuit comprising: a control signal generation circuit for a data bus period of the MPU configured to mask only a certain period.