JP2000353384A - Dram control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM(dynamic random-access memory) control circuit in which circuit constitution is simplified, operation speed is increased, and circuit scale is small. SOLUTION: A RAS(row address select) generating circuit 104 generates a RAS signal based on a CPU-ASTB (address strobe) signal and a CLKOUT signal outputted by a CPU 101. An address decoding circuit 103 generates a/CS- DRAM signal based on ADD 0-19 signals. A CAS generating circuit 106 generates a/CAS(column address select) signal and an ADD-SEL signal based on a/RAS2 signal, a/CS-DRAM signal, and a CPU-ASTB signal. An address switching circuit 102 outputs ADD 0-9 or ADD 10-19 as RAM-ADD 0-9 signals based on a value of the ADD-SEL signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic random access memory (DRAM).
The present invention relates to a DRAM control circuit that generates an address signal of a random access memory, and more particularly, to a DR that generates an address signal of a DRAM based on a signal output by a CPU.
It relates to an AM control circuit.

[0002]

2. Description of the Related Art A conventional DRAM control circuit is shown in FIG. 11 and its timing chart is shown in FIG.

A conventional DRAM control circuit includes an address switching circuit 902, an address decoder circuit 903, a RAS / C
An AS generation circuit 904 is provided. The address decode circuit 903 determines whether or not the address on the address bus output by the CPU 901 is within the DRAM address area. The result of the determination is / CS-DRAM (the first "/" in the signal name indicates negative logic). The same applies hereinafter.) The RAS / CAS generation circuit 904 outputs / RAS and / CAS with respect to a CPU-ASTB (Address Strobe) output from the CPU 901 as a time reference, and ADD- for switching between a row address and a column address.
Output SEL. Address switching circuit 902
The address ADD0-19 output from the CPU 901 is switched between upper and lower addresses by the SEL signal and RAM-A
Output as DD0-9.

FIG. 12 is a circuit diagram showing an internal configuration of the RAS / CAS generation circuit. The circuit shown in FIG. 12 inputs the address switching signal ADD-SEL to the selector S of the selector circuit (IC8) in FIG.

The operation of the conventional RAS / CAS generation circuit shown in FIG. 12 at the time of writing or reading will be described with reference to FIGS.

At time A0, / MRD (or / MW)
When R) changes from LOW to HIGH, the output Q of the flip-flop FP4 becomes LOW, so that the flip-flops FP5, FP6, and FP7 are preset, and their outputs Q become HIGH. At this time, / REFR
Q is HIGH. Therefore, at this time, / RAS, / C
AS and ADD-SEL become HIGH.

At time A1, CPU-ASTB goes high.
Since it becomes IGH, the output of the flip-flop FP4 is preset. At time A2 to A3, CPU-AS
Since TB becomes LOW, the output of IC 12 at this time is H
IGH, flip-flops FP5, FP6, FP
The preset signal 7 becomes inactive.

At time A2, / CS-DRAM becomes L
When OW, / REFRQ is HIGH and IC1
The output of 3 becomes LOW. Therefore, at time A3,
/ RAS goes low, and at time A4 ADD-S
EL goes low and at time A5 / CAS goes low.
W.

At time B1, / MRD (or / MW)
When R) changes from LOW to HIGH, the output Q of the flip-flop FP4 becomes LOW, so that the flip-flops FP5, FP6, and FP7 are preset, and their outputs Q become HIGH. At this time, / REFR
Q is HIGH. Therefore, at this time, / RAS, / C
AS and ADD-SEL become HIGH.

In a conventional circuit, a CPU 901 is provided with a DRAM.
To make 905 access with zero wait, / R
AS falls to the last CLKOUT of cycle T1.
ADD-SEL is switched at the same time as the falling edge (A3) of CLKOUT during the cycle T2 (A3).
4) and / CAS falls in cycle T2
At the same time as the last falling edge of CLKOUT (A5).

The active conditions of / RAS and / CAS in the conventional circuit will be described. As shown in FIGS. 11 and 12, the condition that / RAS falls is determined by CPU-AST
When B is HIGH, / CS-DRAM changes from HIGH to LOW. / CS-DRAM is CPU
901 is generated by performing address decoding of the address bus signal, and becomes LOW when an address of the DRAM 905 is selected. / RAS is a signal obtained by inverting the CLKOUT output from the CPU 901 by the IC 11 / CLK-
It falls in synchronization with the rise of OUT. The condition for rising / RAS is that / MRD and / MWR become inactive. / CAS falls in synchronism with the rise of / CLK-OUT after / RAS goes low. The condition under which / CAS rises is the same as the condition under which / RAS rises.

The refresh method in the conventional circuit is shown in FIG.
As shown in FIG. 4, the CAS before RAS method is used. / R
The generation of AS and ADD-SEL is similar to that at the time of read / write, and therefore the description is omitted. The lead /
At the time of writing, the / CS-DRAM changes to active at time A2, but at the time of refreshing, / REFRQ changes to active at time A2 instead. Therefore, the D input of the FP5 via the IC 13 is
At the time of refresh, a signal similar to that at the time of read / write is input. Since / REFRQ is inputted to the IC 14, the / CA falls before the / RAS at the IC 14 / CA
S is generated.

[0013]

The conventional DRAM control circuits shown in FIGS. 11 and 12 have the following problems.

The first problem is that the conventional circuit uses a DRAM 90.
In order to cause the fall of / RAS at the time A3 at the time of reading / writing from / to 5, the propagation delay of the IC9, IC12, and FP5 which affects the generation of the / RAS signal must be minimized.

The reason is that in order to cause the fall of / RAS to occur at time A3 in the conventional circuit, CPU-AST
IC1 of the signal obtained by inverting B with IC9 and the output Q of FP4
2 must be high before time A3, for which IC9, I9
Unless the propagation delay of C12 and FP5 is minimized,
This is because the elapsed time from the time A2 at the fall time of the CPU-ASTB must be shorter than the original elapsed time of the CPU.

The second problem is that a plurality of DRAs can be used in a conventional circuit.
Attempting to control M increases the circuit scale, which is an adverse effect on downsizing the circuit.

The reason is that RAS / C in the conventional circuit is used.
IC13, FP5, FP in AS signal generation circuit 904
6, FP7 and IC14 are necessary circuit configurations for controlling one DRAM, and when controlling a plurality of DRAMs, IC13, FP5, FP6, FP7 and IC1 are used.
This is because a plurality of 4 are required.

An object of the present invention is to simplify the circuit configuration,
An object of the present invention is to provide a DRAM control circuit whose operation is accelerated and whose circuit scale is small.

[0019]

SUMMARY OF THE INVENTION A DRAM control circuit according to the present invention comprises a clock output from a CPU (Central Processing Unit) and a clock after a fall of the first clock in a write cycle or a read cycle. Based on an address strobe signal that becomes active and then becomes inactive after the first rising edge of the clock and an address signal that changes when the address strobe signal changes from inactive to active, a DRAM (Dynamic Rando) is used.
m Access Memory (Dynamic Random Access Memory) in a DRAM control circuit, based on the clock and the address strobe signal, the address strobe signal becomes active and becomes inactive at the same time. RAS signal generation means for generating an RAS (Row Address Select) signal that becomes active at the falling edge of the second clock of the write cycle or the read cycle; and a RAS signal based on the clock and the RAS signal. Address selection signal generating means for generating an address selection signal that changes from row address select to column address select at the rising edge of the second clock of the write cycle or read cycle; and the clock;
On the basis of the address strobe signal and the address selection signal, the address strobe signal becomes inactive at the same time as being active, and becomes CAS (Column) which becomes active at the falling edge of the third clock of the write cycle or read cycle. Address Select,
And a CAS signal generating means for generating a row address select signal.

The DRAM control circuit according to the present invention comprises:
In the above DRAM control circuit, the CA is synchronized with a refresh signal which changes from inactive to active at the rise of the first clock of a refresh cycle.
It is characterized by further comprising a CAS signal changing means for activating the S signal.

Further, the DRAM control circuit according to the present invention comprises:
In the above DRAM control circuit, the DRAM to be controlled is
In an unselected write cycle or read cycle, an address selection signal maintaining means for maintaining the address selection signal as low address selection based on the address signal, and a DRAM to be controlled is not selected. In a write cycle or a read cycle, a CAS signal maintaining means for maintaining the CAS signal inactive based on the address signal is further provided.

Further, the DRAM control circuit according to the present invention
In the above-described DRAM control circuit, one RAS signal generation unit is provided, and a plurality of the address selection signal generation units and the CAS signal generation units are provided.

Further, the DRAM control circuit according to the present invention comprises:
In the above DRAM control circuit, one RAS signal generation unit is provided, and a plurality of the address selection signal generation unit, the CAS signal generation unit, and the CAS signal change unit are provided.

Further, the DRAM control circuit according to the present invention
In the above DRAM control circuit, one of the RAS signal generation means is provided, and the address selection signal generation means, the CAS signal generation means, the CAS signal change means,
A plurality of the address selection signal maintaining means and the CAS signal maintaining means are provided.

Further, the DRAM control circuit according to the present invention
A DRAM control circuit for generating a RAS signal, an address selection signal, and a CAS signal based on a clock signal and an address strobe signal output from a CPU, wherein the RAS signal and the CAS signal are generated when the address strobe signal is activated. Inactive and
Means for setting the address select signal to low address select; and sequentially activating the RAS signal in synchronization with a change in the clock signal sequentially generated after the address strobe signal becomes inactive; To column address select to activate the CAS signal.

[0026]

[First Embodiment] Referring to FIG. 1, a DRAM control circuit according to a first embodiment of the present invention
It includes a PU 101, an address switching circuit 102, an address decoding circuit 103, a RAS generation circuit 104, a CAS generation circuit 106, and a DRAM 105.

The CPU 101 controls the data signals DB0 to DB15
Is input to and output from the DRAM. Also, the CPU 101
Are address signals ADD0-19, CPU-ASTB
(CPU-AddressSTroB) signal, CLK-OUT (ClocK OU
T) signal, / REFREQ (REFreshREQuest) signal, / MR
It outputs D (Memory Read) signal and / MWR (Memory WRite) signal. The address switching circuit 102 outputs the address signal A
DD0 to DD19 are input, and the upper or lower part of the address signal ADD0 to ADD19 is set to R according to the value of the ADD-SEL (ADDress SELECT) signal generated by the CAS generation circuit 106.
Output as AM-ADD (RAM ADDress) 0-9. The address decoder 103 includes address signals ADD0 to ADD19.
/ CS-DR which is the result of decoding
An AM (Chip Select DRAM) signal is output. The RAS generation circuit 104 receives a CPU-ASTB signal and a CLKOUT signal and uses them to generate a / RAS (Row Address Selec).
t) Generate and output the / RAS2 signal. The CAS generation circuit 106 outputs the CPU-ASTB signal, CLKOUT
Signal, the / CS-DRAM signal, and the / RAS2 signal, and the ADD-SEL signal and the / CAS (C
olumn Address Select) signal is generated and output.

Referring to FIG. 2, RAS generation circuit 104
Includes inverters IC1, IC2 and D-type flip-flops FP1, FP2.

Referring to FIG. 3, the CAS generation circuit 106
Are inverter IC3, OR logic gate IC4, NAN
D logic gate IC5, D type flip-flop FP
3. An AND gate IC 6 is provided.

FIG. 4 shows the address decoder 103.
And an OR gate IC7.

Referring to FIG. 5, the address switching circuit 10
2 includes a two-to-one selector 108.

FIG. 6 is a timing chart when data is read from the DRAM 105 or when data is written to the DRAM 105.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD (or / MW)
R) changes from LOW to HIGH. On the other hand, / MWR
(Or / RD) remains HIGH.

At time A1, the address signal ADD0
~ 19 changes and CPU-ASTB becomes LOW
To HIGH. At the same time, / CPU-ASTB is H
It goes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB and / R
AS, / RAS2, and / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, since / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, ADD0 to 09 signals (row address signals) are output as RAM-ADD0 to 9 signals.
The / CS-DRAM has a DRAM address (000
00H to 3FFFFH) is selected, so that it becomes LOW.

After the time A2 has elapsed and before the time A3, the CPU-ASTB goes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT goes high.
When the level changes from H to LOW, / RAS is set to HI by FP1.
GH changes to LOW.

At time A4, CLKOUT becomes LOW.
From HIGH to /, RAS2 causes / RAS2 to go high.
It goes from IGH to LOW. Also, / CS-DRAM is L
Since it remains OW, ADD-SEL is output by IC4.
Changes from HIGH to LOW. Further, since ADD-SEL becomes LOW, signals ADD10 to 19 (column address signals) are output as RAM-ADD0 to 9 signals.

At time A5, CLKOUT goes high.
When the signal changes from H to LOW, since / REFRQ remains HIGH, the clock of FP3 is set to LOW by IC5.
To HIGH. Therefore, / CAS0 by FP3
Changes from HIGH to LOW. Also, / REFRQ is H
Since the signal remains at the high level, / CAS is set to HI by IC6.
GH changes to LOW.

At time A8, / MRD (or / MW)
R) changes from LOW to HIGH. This is the same as the operation at time A0, whereby the read or write operation ends.

FIG. 7 shows a case where the DRAM 105 is a CAS before R
FIG. 4 shows a timing chart when refreshing is performed by AS. The CAS before RAS refresh is performed when the CPU issues a refresh signal.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD changes from LOW to HIGH. On the other hand, / MWR remains HIGH.

At time A1, address signal ADD0
~ 19 changes and CPU-ASTB becomes LOW
To HIGH. At the same time, / CPU-ASTB is H
It goes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB and / R
AS, / RAS2, and / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, since / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, ADD0 to 09 signals (row address signals) are output as RAM-ADD0 to 9 signals.
Also, since the address of / CS-DRAM is undefined,
It becomes HIGH or LOW.

At time A2, / REFRQ goes high.
It changes from H to LOW. At this time, since / CAS0 remains HIGH, / CAS is changed from HIGH to LOW by IC6.

After the time A2 has elapsed and before the time A3, the CPU-ASTB goes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT goes high.
When the level changes from H to LOW, / RAS is set to HI by FP1.
GH changes to LOW.

At time A4, CLKOUT becomes LOW.
From HIGH to /, RAS2 causes / RAS2 to go high.
It goes from IGH to LOW. Also, / CS-DRAM is L
Since it remains OW, ADD-SEL is output by IC4.
Changes from HIGH to LOW. Further, since ADD-SEL becomes LOW, signals ADD10 to 19 (column address signals) are output as RAM-ADD0 to 9 signals.

At time A5, CLKOUT becomes HIG.
The signal changes from H to LOW, but since / REFRQ remains LOW, the clock of FP3 output from IC5 becomes HI.
It remains at GH. However, / REFRQ is already LO
Since it is W, it remains at / CASLOW output from IC6.

At time A8, / MRD (or / MW)
R) changes from LOW to HIGH. This is the same as the operation at time A0, and the refresh operation ends with this.

FIG. 8 shows that the DRAM 105 is RAS-only.
FIG. 4 shows a timing chart when refreshing. RAS ・
The only refresh is performed when the CPU accesses a main storage space other than the DRAM without issuing a refresh signal.

At time A0, the previous read (or write) operation (not shown) ends, and / MRD (or / MW)
R) changes from LOW to HIGH. On the other hand, / MWR
(Or / RD) remains HIGH.

At time A1, address signal ADD0
~ 19 changes and CPU-ASTB becomes LOW
To HIGH. At the same time, / CPU-ASTB is H
It goes from IGH to LOW. Therefore, FP1, FP2, F
P3 is preset by / CPU-ASTB and / R
AS, / RAS2, and / CAS0 become HIGH. Therefore, ADD-SEL becomes HIGH by IC4. Also, since / REFRQ remains HIGH, IC6
As a result, / CAS also becomes HIGH. ADD-SEL is H
Since it becomes IGH, ADD0 to 09 signals (row address signals) are output as RAM-ADD0 to 9 signals.
The / CS-DRAM has a DRAM address (000
00H to 3FFFFH) is no longer selected, so HI
GH.

After the time A2 has elapsed and before the time A3, the CPU-ASTB goes from HIGH to LOW. At the same time, / CPU-ASTB becomes HIGH.

At time A3, CLKOUT becomes HIG.
When the level changes from H to LOW, / RAS is set to HI by FP1.
GH changes to LOW.

At time A4, CLKOUT becomes LOW.
From HIGH to /, RAS2 causes / RAS2 to go high.
It goes from IGH to LOW. / CS-DRAM is H
Since the signal remains at IGH, ADD-
SEL remains HIGH.

At time A5, CLKOUT becomes HIG.
When the signal changes from H to LOW, since / REFRQ remains HIGH, the clock of FP3 is set to LOW by IC5.
To HIGH. However, the D input of FP3 (ADD
−SEL signal) remains HIGH, so / CAS
0 remains HIGH. Also, / REFRQ is also HI
Since the signal remains at GH, the output / CAS of the IC 6 remains at HIGH.

At time A8, / MRD (or / MW)
R) changes from LOW to HIGH. This is the same as the operation at time A0, and the refresh operation ends with this.

[Embodiment 2] Next, Embodiment 2 of the present invention.
Will be described in detail with reference to the drawings.

The second embodiment is different from the first embodiment in that the address decoding circuit 103 of the first embodiment has a plurality of address decoding circuits 103-
1 to 103-n, the CAS generation circuit 106 becomes a plurality of CAS generation circuits 106-1 to 106-n, and the DRA
The point that M105 becomes a plurality of DRAMs 105-1 to 105-n and an ADD-SEL addition circuit 107 is added
Different from the first embodiment. The RAS generation circuit 104 is the same as that of the first embodiment, and this embodiment also has only one RAS generation circuit. FIG. 1 shows a configuration example of the ADD-SEL addition circuit 107.
0 is shown. Also, the address decode circuits 103-1 to 103-1
03-n have different address decode values.

Referring to FIG. 9, there is shown a configuration of a DRAM control circuit when a plurality of DRAMs are connected. Multiple DRAs
At the time of M control, the generation of the RAS signal
RAS signal generation is common regardless of the number of RAMs.
PU-ASTB is input to a data input D of a flip-flop (FP1), and a signal obtained by inverting CPU-ASTB by an inverter (IC1) is input to a preset PR of FP1.
The FP1 output is preset to a high level and the RAS signal rises in synchronization with the fall of C1. The falling of the RAS signal is a signal obtained by inverting the CLKOUT output from the CPU by the inverter (IC2), and the CPU-ASTB falls asynchronously with the inversion of the CLKOUT (A3).
The rising edge of the RAS signal corresponds to the CPU-A
When STB rises, FP1 is preset by the output of IC1 and rises.

The generation of the CAS signal is based on CS signals from the address decode circuits for the number of DRAMs connected to the CPU.
-A DRAM signal and CAS signal generation circuits for the number of DRAMs are required, but the CAS signal generation circuits all have the same circuit configuration to operate in the same manner. When the CS-DRAM is at the low level after the CPU-ASTB falls to the low level after the fall of the CAS signal, the FP3 causes the non-R by the NAND (IC5) of CLKOUT and REFRQ.
IC synchronized with inverted signal of CLKOUT at EFRQ
By outputting 5, the falling signal is output from the AND (IC6) output when REFRQ is at the high level, and the CAS signal falls at (A4). Each ADD-
The SEL signal is input to the address addition circuit shown in FIG. 10 and is ANDed (IC15). The address of the address bus signal from the CPU is switched as one ADD-SEL signal. When the IC15 output is at a high level, the DRAM address is output. A row address is output in response to an input, and a column address is output in response to a DRAM address input when the output of the IC 15 is at a low level. The rise of the CAS signal rises when the FP3 is preset in synchronization with the rise of the CPU-ASTB.

The DRAM is refreshed by the RE of the CPU.
The output obtained by ANDing (IC6) the FRQ output and the output of FP3 is used. At the time of the REFRQ request of the CPU, the RAS falls at (A2) before (A3) before the fall of RAS.
An S-before-RAS refresh operation is performed. When there is no REFRQ request from the CPU, the RAS-only refresh operation is performed by the output of FP3 for the DRAM when the DRAM is not selected by the address decoding.

[0062]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that it is not necessary to create strict timing in RAS / CAS timing creation. Therefore, stable operation can be realized in circuit design. The reason is that a signal dependent on the CPU can be created because the signal output from the CPU is used.

The second effect is that the circuit configuration is simplified and a circuit with a small circuit size can be provided. The reason is that since the signals are commonly used in the RAS timing creation, the RAS signal generation circuit that has been separately created becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a RAS generation circuit 104 of FIG. 1;

FIG. 3 is a diagram showing a CAS generation circuit 106 of FIG. 1;

FIG. 4 is a diagram illustrating a configuration example of an address decode circuit 103 in FIG. 1;

FIG. 5 is a diagram illustrating a configuration example of an address switching circuit 102 in FIG. 1;

FIG. 6 is a timing chart at the time of read / write of the DRAM control circuit of FIG. 1;

7 is a CAS before RA of the DRAM control circuit of FIG. 1;
FIG. 9 is a timing chart at the time of refresh by S.

FIG. 8 is a timing chart at the time of RAS only refresh of the DRAM control circuit of FIG. 1;

FIG. 9 is a block diagram showing a configuration of a DRAM control circuit according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating an ADD-SEL addition circuit 107 of FIG. 9;

FIG. 11 is a block diagram showing a configuration of a DRAM control circuit according to the related art.

FIG. 12 is a diagram showing a configuration of a RAS / CAS generation circuit 904 in FIG. 11;

FIG. 13 is a timing chart at the time of read / write of the DRAM control circuit of FIG. 11;

FIG. 14 is a timing chart at the time of refreshing the DRAM control circuit of FIG. 11;

[Explanation of symbols]

 Reference Signs List 101 CPU 102 Address switching circuit 103 Address decode circuit 104 RAS generation circuit 105 DRAM 106 CAS generation circuit

Claims (7)

[Claims] 1. A clock output from a CPU (Central Processing Unit), and becomes active after a falling edge of a first clock of a write cycle or a read cycle, and after a rising edge of the first clock thereafter. Based on an address strobe signal that becomes inactive and an address signal that changes when the address strobe signal changes from inactive to active, a DRAM (Dynamic Ran
In a DRAM control circuit for generating a control signal for a dom access memory (dynamic random access memory), based on the clock and the address strobe signal, the address strobe signal becomes active and becomes inactive at the same time. RAS signal generating means for generating an RAS (Row Address Select) signal that becomes active at the falling edge of the second clock of the write cycle or the read cycle; Address selection signal generation means for generating an address selection signal that changes from row address select to column address select at the rising edge of the second clock of the write cycle or read cycle; Strobe signal , On the basis of the address selection signal, the address strobe signal is at the same time as inactive when it comes to active, the write cycle or becomes active at the falling edge of the third clock of the read cycle CAS (Colum
and a CAS signal generating means for generating a row address select (row address select) signal. 2. The DRAM control circuit according to claim 1, wherein said CAS signal is activated in synchronization with a refresh signal which changes from inactive to active at the rise of a first clock of a refresh cycle.
DRA further comprising an AS signal changing means.
M control circuit. 3. The DRAM control circuit according to claim 1, wherein in a write cycle or a read cycle in which a DRAM to be controlled is not selected, the address selection signal is set to a low address based on the address signal. An address selection signal maintaining means for maintaining a selected state; and a C for maintaining the CAS signal inactive based on the address signal in a write cycle or a read cycle in which a DRAM to be controlled is not selected.
DRA further comprising AS signal maintaining means
M control circuit. 4. The DRAM control circuit according to claim 1, further comprising one RAS signal generation means, and a plurality of said address selection signal generation means and said CAS signal generation means. circuit. 5. The DRAM control circuit according to claim 2, further comprising one RAS signal generation means, and a plurality of said address selection signal generation means, said CAS signal generation means, and said CAS signal change means. A DRAM control circuit, characterized in that: 6. The DRAM control circuit according to claim 1, further comprising one RAS signal generation unit, wherein said address selection signal generation unit includes:
A DRAM control circuit comprising a plurality of S signal generating means, said CAS signal changing means, said address selection signal maintaining means, and said CAS signal maintaining means. 7. A DRAM control circuit for generating a RAS signal, an address selection signal, and a CAS signal based on a clock signal and an address strobe signal output from a CPU, wherein the RAS signal is activated when the address strobe signal becomes active. Means for making the CAS signal inactive and making the address selection signal low address select; and in synchronism with the change of the clock signal sequentially generated after the address strobe signal becomes inactive. Activating the RAS signal sequentially, switching the address selection signal to column address select,
Means for activating the AS signal. A DRAM control circuit, comprising: