JPH08241586A - Dram control device - Google Patents

Abstract

PURPOSE: To make an operation clock high speed by giving column address strobes of access and refresh to an input terminal of a DRAM from directly the same flip-flop operated by a system clock or through a buffer. CONSTITUTION: A timing generation section 10 is made by integrating an access timing generation section 4 and a refresh timing generation section 5, and flip- flop 44, 55 for outputting each signals *ACAS, *RCAS are integrated to a flip-flop 25. Thereby, a switching section 6 is omitted, at the time of accessing a DRAM, after a column address selecting signal *CAS of the flip-flop 25 is outputted by a clock edge, a time required for fetch the DRAM data is made the minimum by the next clock edge.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for controlling a DRAM (dynamic RAM) which requires periodical refreshing for storing information, and particularly to shorten the clock period to speed up the operation. It relates to a DRAM controller. In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art A DRAM needs to perform a refresh operation at a constant cycle. However, the timing of a control signal is different between the read / write access and the refresh operation, and the read / write access is random. Therefore, the refresh operation must be performed independently of the access.

To access the DRAM, a row address strobe signal (hereinafter referred to as a row address selection signal or RAS) is used.
Signal) and a column address strobe signal (hereinafter also referred to as a column address selection signal or a CAS signal), but both of them are flip-flops (abbreviated as FF) that operate at the system clock for speeding up. Is generally used.

On the other hand, there is a method of using only the RAS signal or a method of using both the RAS signal and the CAS signal for the refresh operation. However, when only the RAS signal is used, the entire area of the row address is sequentially accessed separately. Since it is necessary to provide an address generation circuit, a refresh method using a refresh counter built in DRAM is usually used by using a RAS signal and a CAS signal. However, when accessing and refreshing, the RAS signal and C
Since the set / reset conditions of the AS signal are different, conventionally, separate timing generation circuits are provided for access and refresh, and the separate timing generation circuits generate the RAS signal and the CAS signal, respectively. And the OR condition between the two CAS signals is calculated and DR
It generated the final RAS and CAS signals to the AM.

FIG. 6 is a block diagram showing a configuration example of a conventional DRAM control circuit, FIG. 7 is a time chart of signals of respective parts in the circuit of FIG. 6, and FIGS. 8 to 10 are internal circuits of main blocks of FIG. It is a figure. It should be noted that the asterisk * of the sign of the signal in each of these figures and other figures indicates that it is a negative logic. In FIG. 6, 01 is a DRAM control circuit, 02 is a DRAM, and DR
The AM control circuit 01 is roughly divided into an address decoding unit 1, a refresh request generating unit 2, an arbitration unit 3, an access timing generating unit 4, a refresh timing generating unit 5, and a switching unit 6.

When there is an access request from a CPU (not shown) or the like, the access source has an access destination upper address ADu, an address strobe signal * AS (hereinafter abbreviated as * AS signal) and a read / write signal R / * W ( Below R
/ * W signal) is input to the DARM control circuit 01. The access destination upper address ADu is decoded by the address decoding unit 1 together with the address strobe signal * AS, and when the DRAM 02 is selected, the address decoding unit 1 outputs the DRAM access request signal * AR.
Sends EQ (hereinafter abbreviated as * AREQ signal).

Here, the upper address ADu is DRA.
This is an address that is a higher order of the address AD (address bits A _{0 to} A _{19 in} this example) directly input to M02 (that is, specifies address bits of A ₂₀ or more). The refresh request generator 2 periodically transmits a refresh request signal * RREQ (hereinafter also abbreviated as * RREQ signal),
Refresh end confirmation signal * RACK (hereinafter * RACK
Signal), the refresh request signal * R
Negate REQ.

The arbitration unit 3 uses the DRAM access request signal *
Upon receiving the AREQ and the refresh request signal * RREQ, the access request and the refresh request are arbitrated,
Either an access signal * ACC (hereinafter also referred to as * ACC signal) or a refresh signal * REF (hereinafter also referred to as * REF signal) is transmitted. However, at this time, if the access request signal * AREQ and the refresh request signal * RREQ are received at the same time, the refresh signal * REF is output with priority, and the access signal * ACC is output when the refresh request signal * RREQ is received. If it is being accessed, the refresh signal * REF is output after the access is completed (that is, after the access completion confirmation signal * AACK (see FIG. 8) is received) to start the refresh.

The access timing generation unit 4 accesses
Receives signal * ACC and read / write signal R / * W
DRA at the timing required for DRAM access
Access line address selection signal * ARAS which is M control signal
(That is, in this example, the address AD (A
₀~ A₁₉) Out of row address A₀~ A₉(Lower side 1
0 bit) to the DRAM02 to read it),
Access column address selection signal * ACAS (that is, address A
D (A₀~ A₁₉Column address A of_Ten~ A
₁₉Read (upper 10 bits) into DRAM02
Signal), write enable signal * WE (that is,
Signal that specifies read / write) and access source access
Process end confirmation signal * AACK (hereinafter referred to as * AACK signal
Abbreviated) is generated and output.

Upon receiving the refresh signal * REF, the refresh timing generator 5 generates a refresh row address selection signal * RRAS and a refresh column address selection signal * RCAS signal which are DRAM control signals at the timing required for refreshing. Output. At the refresh timing at this time, the so-called "CA" is performed in which the * CAS signal is asserted and then the * RAS signal is asserted.
S before RAS refresh "is used.

The OR gate G1 of the switching unit 6 inputs the access row address selection signal * ARAS and the refresh row address selection signal * RRAS, and after a certain delay time, the row address as a logical sum signal of these two input signals. Selection signal * R
The AS is generated and output to the DRAM 02. Similarly, the OR gate G2 of the switching unit 6 uses the access column address selection signal * AC
The AS and the refresh column address selection signal * RCAS are input, a column address selection signal * CAS is generated as a logical OR signal of these two input signals after a certain delay time, and DR
Output to AM02.

FIG. 7 is a time chart showing the timing of each signal when requests for access (write cycle) → refresh (refresh cycle) → access (read cycle) are successively input.
Reset conditions and generation logic are indicated by arrows. Here, a general DRAM control method is used, and at the time of access, a row address (row address, A _{0 to} A _{9 in} this example) and a row address selection signal * RAS are asserted, and then a column address (column address, in this example, A _{10 to} A ₁₉ ) and the column address selection signal * CAS is asserted. Further, at the time of refreshing, “CAS before RAS refresh” is used in which the column address selection signal * CAS is asserted and then the row address selection signal * RAS is asserted.

In FIG. 7, a clock signal CLK and an address A
Signals other than the D and read / write signals R / * W are represented by solid lines only at the low level. Therefore, if there is a ◯ mark in the part where there is no line, it means that the signal is at a high level (inactive) in the part marked with the ◯ mark. Also, DRA
The address AD input to M02 is a row address (A ₀ -A) immediately before the assertion of the column address selection signal * CAS during a read cycle and a write cycle via a means (not shown).
It changes from A ₉ ) to the column address (A _{10 to} A ₁₉ ).

The Δ marks at both ends of the signal indicated by the solid line (low level) are output by the flip-flop, and change at the Δ mark portion (occur at the front end of the solid line and disappear at the rear end of the solid line). That is, the upward triangle indicates the change in the falling edge of the clock, and the downward triangle indicates the change in the rising edge. Further, the arrow marked with a circle indicates that the signal indicated by the tip of the arrow is generated by the logical product of the generation logics of the output signals indicated with a circle.

Explaining the arrow (a) in FIG. 7, for example, a low-level DRAM access request signal * ARE
Q, a high level refresh request signal * RREQ, and a high level refresh signal * REF are ANDed to generate a low level access signal * ACC indicated by an arrow tip by the flip-flop at the falling edge of the system clock CLK. Indicates.

Similarly, the arrow (b) in FIG. 7 indicates a low level write enable signal * WE indicated by the tip of the arrow by the logical product of the low level read / write signal R / * W and the low level access signal * ACC. Indicates that it will be generated. The logical expression of the signal generated in FIG. 7 is the following expression (1.
1) to (1.11).

[0017]

[Equation 1] (* ACC) = * AREQ * [* RREQ] * [* REF] ... (1.1) (* REF) = * RREQ * [* ACC] * [* RACK] ... ( 1.2) (* ARAS) = * ACC ** [AACK] ... (1.3) (* ACAS) = * ARAS * [* AACK] ... (1.4) (* RRAS) = * RCAS ・ [* RACK] ・ ・ ・ (1.5) (* RCAS) = * REF ・ [* RACK] ・ ・ ・ (1.6) * RAS = * ARAS + * RRAS ・ ・ ・ (1.7) * CAS = * ACAS + * RCAS ... (1.8) * WE = [R / * W] * ACC ... (1.9) (* AACK) = * ACAS ... (1.10) ( * RACK) = * RRAS (1.11) Here, the signal marked with () on the left side of the above equation is flickering. The signal output by the flip-flop is shown, and the right side of the signal on the left side shows the combination condition of the signals input to the flip-flop for generating the signal on the left side. And, on the right side, is the logical product, + is the logical sum, and [] is the inversion of the signal therein. However, [R / * W] indicates a low level.

FIG. 8, FIG. 9, and FIG. 10 show examples of actual circuit configurations of the arbitration unit 3, the access timing generation unit 4, and the refresh timing generation unit 5, respectively, which realize the above logical expressions. Here, the arbitration unit 3 in FIG. 8 uses the AND gate 31 that realizes the right side of the equation (1.1), the JK flip-flop 32 that realizes the left side of the equation (1.1), and the expression (1.2). The AND gate 33 that realizes the right side and the D flip-flop 34 that realizes the left side of the equation (1.2).

Further, the access timing generator 4 of FIG.
Is an AND gate 41 that realizes the right side of Expression (1.3), and a D flip-flop 4 that realizes the left side of Expression (1.3).
2. AND gate 43 that realizes the right side of equation (1.4),
The D flip-flop 44 that realizes the left side of the formula (1.4) and the D flip-flop 4 that realizes the formula (1.10)
5, AND gate 46 for realizing the equation (1.9).

Further, the refresh timing generator 5 of FIG. 10 has an AND gate 5 for realizing the right side of the equation (1.5).
1. D flip-flop 52 that realizes the left side of expression (1.5), D flip-flop 53 that realizes expression (1.11), AND gate 5 that realizes the right side of expression (1.6)
4. A D flip-flop 55 that realizes the left side of the equation (1.6).

[0021]

By the way, in order to perform the memory access at a higher speed, the DR is started from the clock edge.
It is necessary to reduce the delay time until the output of the * RAS signal and the * CAS signal for controlling the AM. FIG. 11 shows a configuration example of the time that restricts the cycle of the clock CLK,
This figure shows the configuration of the time between the data acquisition timing t ₂ (falling edge of the clock CLK) and the timing t _{0 of the} falling edge of the clock CLK one cycle before in the access (read cycle) of the DRAM. Is shown.

That is, the D flip-flop 4 of the access timing generator 4 is generated by the falling of the clock at time t _0.
4 is driven and the access column address selection signal * ACAS is output after a delay time ΔT1. As a result, O of the switching unit 6
The R gate G2 outputs a column address selection signal * CAS to the DRAM 02 after a delay time ΔT2. This makes D
The output data is fixed after the delay time ΔT3 in the RAM 02.

During this time, an access end confirmation signal * AA
CK is output at the clock rising time t ₁ after the signal * ACAS is output. From the delay time ΔT3, C
Set-up time Δ for PU to recognize output data
DRA at the falling edge of the clock at time t ₂ after the delay of T4
The output data of M is taken into the CPU. At this point in time t ₀
The delay time ΔT2 of the switching unit 6 can be reduced by the DRAM control circuit among the configuration times during t ₁ .

Therefore, according to the present invention, the * RAS signal of the access timing generation unit 4 and the refresh timing generation unit 5,
* The flip-flop relating to the output of the CAS signal is shared, the switching unit 6 is omitted, and * R from the clock edge
D that realizes faster memory access by reducing the output delay time of AS signal and * CAS signal
An object is to provide a RAM control circuit.

[0025]

In order to solve the above-mentioned problems, a DRAM control device according to claim 1 is a host device (CP).
A DRAM access request signal * (via the address decoding unit 1) based on an access signal (upper address ADu, address strobe signal * AS, read / write signal R / * W, etc.) of the DRAM (02) from U, etc. AR
After generating the EQ), at least the row address strobe signal (* RAS) and then the column address strobe signal (* CAS) are output to the DRAM, and (via the refresh request generating unit 2) at a constant period (refresh request signal * RREQ). In the DRAM control device (01) which outputs these two signals to the DRAM and refreshes the DRAM, the column address strobe signal for access and refresh (using the timing generation unit 10) is supplied by the system clock (CLK). The same flip-flop (JK flip-flop 25) that operates is directly applied to the input terminal of the DRAM or via a buffer.

According to a second aspect of the present invention, there is provided the DRAM control device according to the first aspect, wherein the same flip-flop which operates the access and refresh low add strobe signals (using the timing generation unit 10) by the system clock is used. (JK flip-flop 22) directly or via a buffer to the input terminal of the DRAM.

[0027]

1 (a) and 1 (b) respectively show the DR according to the present invention.
The main parts of the AM control device and the conventional DRAM control device are shown in comparison. That is, in the present invention, the timing generation unit 10 in which the conventional access timing generation unit 4 and the refresh timing generation unit 5 are integrated is provided, and at least FIG.
A conventional access column address selection signal * ACAS output flip-flop 44 and a refresh column address selection signal * RCAS output flip-flop 55 shown in FIG.
The conventional switching unit 6 shown in FIG.

By thus combining the conventional refresh flip-flops and access flip-flops of the DRAM control device into one, the gates after the flip-flop 25 of the CAS signal output from the DRAM control device are eliminated, The DRAM 02 can be accessed with a minimum delay time.

[0029]

FIG. 2 is a block diagram of a DRAM controller as an embodiment of the present invention. In the figure, the timing generation unit 10 is a block in which the arbitration unit 3, access timing generation unit 4, refresh timing generation unit 5, and switching unit 6 in FIG. 6 are combined.

Here, the operations of the address decoding unit 1 and the refresh request generating unit 2, the timing of each input signal, and the timing of requesting each output signal are the same as those described in the prior art. FIG. 4 shows the timing generator 1.
It is a circuit diagram which shows the structure of 0. The figure shows AND gate 1
1, 14-16, 19-21, OR gates 12, 13,
17, 18 and flip-flops 22 to 27. As shown in this figure, the row address selection signal * RAS and the column address selection signal * CAS are directly output from the flip-flops 22 and 25 to the DRAM 02. However, a buffer circuit may be provided between the flip-flops 22 and 25 and the DRAM 02.

2 and 4 in the case where requests for access (write cycle) → refresh (refresh cycle) → access (read cycle) are continuously input.
The signal timings of the respective parts are shown. The writing method of FIG. 3 is the same as that of FIG. The logical expressions of the signals generated in FIG. 3 are represented by the following expressions (2.1) to (2.7). The method of writing this logical expression is the same as that described in FIG.

[0032]

(2) (* ACC) = * AREQ · [* RREQ] · [* REF] ... (2.1) (* REF) = * RREQ · [* ACC] ・ ・ ・ (2.2) ( * RAS) = (* AREQ / [* RREQ] / [* REF]) + (* REF / * CAS) (2.3) (* CAS) = (* ACC / * RAS) + (* RREQ)・ [* ACC]) ・ ・ ・ (2.4) * WE = R / * W ・ * ACC ・ ・ ・ (2.5) (* AACK) = * ACC ・ * CAS ・ ・ ・ (2.6) (* RACK) = * REF · * RAS · [* RACK] (2.7) As for the relationship between FIG. 4 and the above logical expression, the right side of expression (2.1) is realized by the AND gate 14. The left side of the equation (2.1) is realized by the JK flip-flop 23.

The right side of the equation (2.2) is realized by the AND gate 15, and the left side of the equation (2.2) is realized by the JK flip-flop 24. The first term on the right side of the equation (2.3) is realized by the AND gate 14, the second term on the right side is realized by the AND gate 11, and the first term on the right side is realized.
The logical sum of the term and the second term is realized by the OR gate 12. The left side of the equation (2.3) is realized by the JK flip-flop 22.

The first term on the right side of the equation (2.4) is realized by the AND gate 16, and the second term on the right side is represented by the AND gate 15.
And the logical sum of the first term and the second term on the right side is OR
It is realized by the gate 17. And this equation (2.
The left side of 4) is realized by the JK flip-flop 25. Expression (2.5) is realized by the AND gate 21.

The right side of the equation (2.6) is realized by the AND gate 19, and the left side of the equation (2.6) is realized by the D flip-flop 26. The right side of Expression (2.7) is realized by the AND gate 20, and this Expression (2.
The left side of 7) is realized by the D flip-flop 27. FIG. 5 shows an access (read cycle) in the present invention.
At times, an example of the configuration of time that restricts the cycle of the clock CLK is shown, and this figure corresponds to FIG. 11. As can be seen from FIGS. 2 to 4, the * RSS signal and the * CAS signal, which are independently generated, are directly connected to the input terminals of the DRAMs from the outputs of the flip-flops 22 and 25 during the access and the refresh, respectively. Therefore, the delay time of the OR gate of the conventional switching unit 6 becomes unnecessary, and the time that must be accommodated in the clock cycle from the time point t ₀ is as shown in FIG. 5 of the flip-flop (25 in this example). output delay time Delta] T1, * CAS signal delay time from the assertion to the determination of output data of the DRAM of .DELTA.T3, the clock CLK is only setup time ΔT4 until time t ₂ which falls output data from stable, increasing the clock frequency It becomes possible. In addition, no special parts are required to realize the circuit of FIG.
Not only can it be configured, but also ASIC and PLD can be made extremely easily.

[0036]

According to the present invention, the refresh FF and the access FF are combined into one, and at least the CAS signal (column address strobe signal) which is the DRAM control signal is directly connected from the output of the flip-flop to the input terminal of the DRAM. By doing so, the delay time from the clock edge to the data fetch at the time of accessing the DRAM can be minimized. Therefore, by shortening the clock cycle and increasing the operating frequency of the entire DRAM control circuit, high speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a DRAM control circuit in comparison with the present invention and a conventional one.

FIG. 2 is a block diagram of a DRAM control circuit according to the present invention.

FIG. 3 is a time chart of signals at various parts in the circuit of FIG.

FIG. 4 is an internal circuit diagram as an embodiment of the timing generation unit in FIG.

FIG. 5 is a block diagram of a time for restricting a clock cycle in the present invention.

FIG. 6 is a block diagram of a conventional DRAM control circuit corresponding to FIG.

FIG. 7 is a time chart of signals at various parts in the circuit of FIG.

8 is an internal circuit diagram of the arbitration unit of FIG.

9 is an internal circuit diagram of the access timing generation unit in FIG.

10 is an internal circuit diagram of the refresh timing generator of FIG.

FIG. 11 is a block diagram of a time period in which a conventional clock cycle is restricted.

[Explanation of symbols]

01 DRAM control device 02 Dynamic RAM (DRAM) 1 Address decoding unit 2 Refresh request generation unit 10 Timing generation unit 11 AND gates 12 and 13 OR gates 14 to 16 AND gates 17 and 18 OR gates 19 to 21 AND gates 22 to 27 Flip block R / * W Read / write signal ADu Upper address AD address * AS address strobe signal * AREQ DRAM access request signal * RREQ refresh request signal * ACC access signal * REF refresh signal * RAS Row address select signal (row address strobe signal) * CAS column address selection signal (column address strobe signal) * WE write enable signal * AACK access end confirmation signal * RACK refresh end confirmation signal

Claims (2)

[Claims] 1. A column address strobe signal is output to the DRAM at least following a row address strobe signal based on a DRAM access signal from a host device.
Also, these two signals are output to the DRAM at regular intervals and DR
A DRAM controller for refreshing an AM, wherein a column address strobe signal for access and refresh is applied to an input terminal of the DRAM directly or through a buffer from the same flip-flop operating with a system clock. 2. The DRAM control device according to claim 1, wherein the row address strobe signal for access and refresh is applied to the input terminal of the DRAM directly from the same flip-flop operating with a system clock or via a buffer. Characteristic DRAM control device.