JPH0423146A - Write assurance circuit for risc processor - Google Patents

Abstract

PURPOSE:To secure the proper holding time for the address and the data of a RISC (reduced instruction set computer) processor and to attain a write assurance by delaying a data request signal, securing an AND with the data request signal, and producing a data strobe signal. CONSTITUTION:A flip-flop 40 delays a data request signal, and an AND circuit 41 secures an AND between the output of the flip-flop 40 and the data request signal and produces a data strobe signal. Thus the data strobe signal is produced when an address and the data are well decided even though a RISC processor 1 which produces no data strobe signal gives a write access to an SRAM 2. Then the holding time is assured for the address and the data and a write operation is assured.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 5) Means for solving the problem to be solved by the invention (Figure 1) Working example (a) 1 Description of Examples (Figures 2 to 4) (b)
Description of other embodiments Effects of the invention [Summary] Regarding a write guarantee circuit when a RISC processor that does not generate a data strobe signal writes to a storage unit such as a register or memory, the address and data hold time of the RISC processor is guaranteed. The processor has a RISC processor, a storage section, and an address/data bus connecting the RISC processor and the storage section, and the 1lIsc processor outputs addresses and data to the address/data bus, In a system that generates and writes a data request signal and a write signal in the storage unit, a flip-flop delays the data request signal, ANDs the output of the flip-flop and the data request signal, and generates a data strobe signal. It has an AND gate that generates .

[Industrial application field]

The present invention is a RISC that does not generate a data strobe signal.
The present invention relates to a write guarantee circuit when a processor writes to a storage unit such as a register or memory.

With the recent demand for faster information processing systems, RI
S C (Reduced In5truction S
et Computer) processors are provided.

RISC processors are conventional CISC (Com-
plex In5truction Set Comp
uter) processor, the number of instruction cents is limited,
It executes one instruction in one machine cycle, increasing data processing speed.

In such a RISC processor, priority is given to speeding up, so the number of input/output control signals is limited, and an external circuit is particularly required for write guarantee.

[Conventional technology]

FIG. 5 is an explanatory diagram of the prior art.

When the RISC processor 1 writes to the storage unit 2 such as the L7 register or the memory via the bus 3, it outputs a data request *DREQ and a write signal to put the data on the bus 3.

By the way, in the Cl5C processor, since a data strobe signal is generated, a long data hold time and address hold time are guaranteed.

This RISC processor 1 executes in one machine cycle, so after accessing an external register, it may access another register or memory in the next cycle. Since data requests are continuous, a data strobe signal is generated. There are things I haven't done.

For example, eight advanced Micro Devices
There is no data strobe signal in the 290ORI SCMPU from Company S.

For this reason, in the RISC processor, a data request is used as a data strobe signal.

[Problem to be solved by the invention]

However, if the data request is a data strobe signal, there is a problem that the data strobe signal does not satisfy the address and data hold times.

Therefore, an object of the present invention is to provide a write guarantee method for a RISC processor that can guarantee the address and data halt time of the RISC processor.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

As shown in FIG. 1, the present invention provides a RISC processor 1
, a storage section 2, and an address/data bus 3 connecting the tSC processor 1 and the storage section 2, and the RIS
In a system in which a C processor 1 outputs an address and data to the address/data bus 3 and generates and writes a data request signal and a write signal to the storage section 2, a flip-flop 40 for delaying the data request signal is used. , and an AND gate 41 for ANDing the output of the flip-flop 40 and the data request signal to generate a data strobe signal.

[Effect]

In the present invention, a delayed data request signal,
Since the data strobe signal is generated by ANDing the data request signal, the data strobe signal can be generated at the time when the data is determined.

Therefore, even in the RISC processor, the address and data hold time during writing can be guaranteed, and writing can be guaranteed.

Moreover, it can be realized with a simple configuration.

〔Example〕

(al　Explanation of one embodiment FIG. 2 is a configuration diagram of an embodiment of the present invention.

In the figure, the same components as those shown in FIG. 1 are indicated by the same symbols; 3a is an address bus, and 3b is a data bus.

4 is a memory control circuit, and a data request signal *D
REQG to data strobe signal DSTRB, data ready signal *DRDY, data request cut signal D
A control signal generation circuit 4a that generates REQCUT and RI
Continuous data request signal from SCMPUI *D
A DREQ gate circuit 4b that cuts REQ with a data request cut signal DREQCUT, a data request signal DREQG from the DREQ gate circuit 4b, a data strobe signal DSTB, and a read/write signal RE.
AD/WRITE to static memory (SRAM)
2, a read/write control circuit 4C that generates an out enable signal *OE, a write enable signal *WE, and a chip select signal *C8, and a decoder 4d that decodes the address of the address bus 3a and generates a memory select signal MEMSEL. It has

Figure 3 is a detailed circuit diagram of Figure 2, and the memory of Figure 2.
(SRAM) control circuit is shown.

In the figure, the same parts as those shown in FIG. 2 are indicated by the same symbols.

The DREQ gate circuit 4b includes an AND gate 45 that inverts and ANDs a data request signal *DREQ from the RISC processor 1 and a data request cut signal DREQCUT, which will be described later, and outputs the inverted output DREQG. It has an AND gate 46 that ANDs the data request signal DREQG and the memory select signal MEMSEI.

The control signal generation circuit 4a converts the data request signal DREQG of the AND gate 46 into the system clock 5YSCL.
The flip-flop 40 outputs data ready DRDY1 to DRDY3 delayed by 1 clock, 2 clocks, and 3 clocks, data ready DRDY2, read signal READ, and inverted data request signal *DRE.
The write guarantee circuit includes an AND gate 41 which inverts QG and AND gate 41 to generate a data strobe signal DSTRB.

Furthermore, the control signal generation circuit 4a outputs data ready DRDY.
a data ready generation circuit consisting of an inverter 43 that inverts the output of the inverter 43 and the data ready DRDY2, an AND gate 44 that ANDs the output of the inverter 43 and the data ready signal *DRDY, and outputs the inversion as the data ready signal *DRDY; The cut signal generation circuit includes an AND gate 42 that performs an AND operation on the data request cut signal DREQCUT and generates a data request cut signal DREQCUT.

The read/write control circuit 4c includes an inverter 47 that inverts the data request signal DREQG and generates a chip select signal *C8, and a data request signal DREQ.
G and the read signal READ, and the AND gate 48 generates the inversion as the out enable signal *OE, AND the data request signal DREQG and the data strobe signal DSTRB, and generates the inversion as the write enable signal *WE. It has an AND gate 49 that outputs .

FIG. 4 is a time chart diagram of one embodiment of the present invention.

In the figure, a continuous (burst) access mode of write access and read access will be explained.

RISC processor 1 accesses memory 2 by
The data request signal *DREQ is asserted to a low level, an address is output to the address bus 3a, data is output to the data bus 3b, and the read signal READ is set to a low level (write instruction).

The data request signal *DREQ is an AND gate 45
The signal is ANDed with the memory select signal MENSEL by the AND gate 46, and after passing through the gate, it becomes the data request signal DREQG.

This signal is input to the flip-flop (FF) 40, delayed by 1 clock by the system clock 5YSCLK, and becomes data ready DRD\1.

This data ready DRDYI is re-inputted to the flip-flop 40, and is delayed by ■ clock, and data ready DRDY
It becomes 2.

Furthermore, this data ready DRDY3 is a flip-flop 4.
0 again, delayed by 1 clock, data ready DR
It will be DY3.

That is, the flip-flop 40 generates data ready signals DRDY1 to DRDY3 by delaying the data request signal DREQG by one, two, or three clocks.

Data ready DRDY2 delayed by two clocks is inverted and input to the AND gate 41.

Ant game 1/41 is an inverted data request signal *D
REQG and an inverted read signal READ are input.

Therefore, with a write instruction from the AND gate 41, DREQ
When G is at high level, the inversion of data ready DRDY2 is output as data strobe signal DSTRB.

That is, the data strobe signal DSTRB rises when the data request signal *DREQG is asserted, and falls at the rise of the second clock.

This means that the data strobe signal DSTR at the 1.5 clock in the 2.5 clock write access period shown in the figure
The falling edge of B is the starting point for data acquisition.

At this point, the write data indicated by data DATA in FIG. 4 has been determined on the data bus 3b, and the write data is guaranteed for at least one clock from there.

On the other hand, as in the conventional case, the data strobe signal DS
If TRB is the data request signal DREQG, D
The rising timing of STRB is the 2.5 clock from the assertion of DREQG, which is the point at which the write data begins to disappear, and the data is not guaranteed.

In addition, the inverted data ready DRDY via the inverter 43
3 and data ready DRDY2 are ANDed at an AND gate 44, and data ready *DRDY is returned to the RISC processor 1.

Further, data ready DRDY2 and data DRDY3 are ANDed by an AND gate 42, a data request cunt signal DREQCUT is generated, and an AND gate 45 of the DREQ gate circuit 4b is controlled.

The meaning of this data request cut signal DREQCUT is that in the case of the RISC processor 1, the data request signal *DREQ remains asserted during continuous access, and is not negated for each access as in the Cl5C processor.

Therefore, out enable *OE and write enable *WE cannot be generated for each access, making it impossible to access the memory in a normal memory sequence.

Furthermore, it becomes impossible to perform a check sequence such as a general-purpose ECC or parity check circuit.

Therefore, the alert data request signal *D
REQ is converted by data request cut signal DREQCUT into negative 1-L for each access and data request signal *DREQG for each access.

Finally, in the read/write control circuit 4C, the data request signal DREQG for each access is inverted by the inverter 47 to generate the chip select signal *C3.
When writing, data strobe signal DSTR is generated.
B and data request signal DREQG generate write enable signal *WE from AND gate -49, and S
Access RAM2.

In this way, R
Even when the ISC processor 1 performs write access to the SRAM 2, a data strobe signal can be generated when the address and data are sufficiently determined, and the hold time of the address and data is guaranteed, so that writing can be guaranteed.

(b) Description of other embodiments In addition to the embodiments described above, the present invention can be modified in the following ways.

(2) Although the explanation has been made using SRAM as the storage unit, the present invention may also be applied to registers such as DRAM, flip-flops, and latch circuits.

■ Also, although data ready DRDY2 is used, data ready signal *DRDY and data request signal *DRE created from data ready DRDY2 and DRDY3 are used.
QG may be used to generate the data strobe signal DSTRB.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, the data request signal is delayed by the flip-flop 40, and the data request signal is delayed by the AND gate 40.
1 and the data request signal to generate the data strobe signal, it is possible to take an appropriate hold time for the address and data during writing by an RTSC processor that does not generate a data strobe signal, and to guarantee writing.

Moreover, it can be realized with a simple circuit.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Fig. 3 is a detailed circuit diagram of an embodiment of the invention, and Fig. 4 is a time chart diagram of an embodiment of the invention. FIG. 5 is an explanatory diagram of the prior art. In the figure, 1.1--RISC processor, 2-memory section, address/data bus, flip-flop, and gate.

Claims (1)

[Claims] A RISC processor (1), a storage section (2), and an address/data bus (3) connecting the RISC processor (1) and the storage section (2); In a system in which a RISC processor (1) outputs an address and data to the address/data bus (3) and generates and writes a data request signal and a write signal to the storage unit (2), the data request signal is A RISC processor characterized in that it has a flip-flop (40) that delays, and an AND gate (41) that ANDs the output of the flip-flop (40) and the data request signal to generate a data strobe signal. Write guarantee circuit.