JPH0520164A - Memory access device - Google Patents

Abstract

PURPOSE:To provide the memory access device which is operated by a frequency of two folds of a fundamental bus cycle, and constituted by improving an operation sequence which does not necessitate a high speed memory system. CONSTITUTION:A read timing at the time of read is between a second transition of a level of a fundamental bus cycle in which a read signal becomes an active state after an address signal is transferred, and a first transition of a level of a clock of the next fundamental bus cycle, and a section in which the read signal becomes an active state is about 3/4 of the fundamental bus cycle and much longer than before, therefore, a low speed memory can be used. That is, this memory access device is operated by a frequency of two folds of the fundamental bus cycle, can use a low speed memory without executing an operation of the memory itself at a high speed, thus, has an effect by which a high speed computer system can be realized at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation sequence of a memory access device, and more particularly to a memory access device applicable to various computer system controllers.

[0002]

2. Description of the Related Art Speeding up memory access in a computer system is an essential condition for speeding up the system. The speeding up of the memory access by speeding up the operation speed of the memory itself causes a large cost increase because the memory is used in a large amount in the system. Therefore, there is a demand for a high-speed memory access device in which the conventional memory can be used by improving the operation sequence without increasing the operation speed of the memory itself.

[0003]

Here, at the time of reading the memory in the memory access, the capacitor of each cell forming the memory is amplified by the sensing amplifier and read. Therefore, the active time of the read signal of the memory access device needs to be considerably long. On the other hand, when writing to the memory during memory access,
The capacitor of each cell forming the memory is charged with a current. At this time, since a large current can be used in consideration of the writing time to the memory, the active time of the write signal of the memory access device may be shorter than that of the read signal. That is, in increasing the speed of the basic bus cycle described above, the ratio of the read signal in the active state in the basic bus cycle becomes a problem. According to the memory access circuit of the prior art, a frequency of four times or three times the basic bus cycle, which is a unit of memory read (hereinafter, read) and memory write (hereinafter, write) for memory access, is used. Reference period signal (hereinafter,
There is something that requires a clock signal). recent years,
As shown in an example in FIG. 5, as the basic bus cycle becomes faster, the operation of a circuit for memory access has been realized with a clock signal having a frequency twice that of the basic bus cycle. With this device, the timing of the end of the read signal at the time of reading is as fast as about 1.5 cycles after the end of the basic bus cycle after the output of the address signal. As described above, in the memory access device having the operation sequence in which the ratio of the read signal in the active state in the basic bus cycle is as small as about 1/2, there is a problem that a memory having a high operation speed is eventually required. It was Further, in a memory access device having an operation sequence in which the timing of the end of data writing at the time of writing is later than the end of the basic bus cycle, the memory access device will go into the next basic bus cycle by that amount. For this reason,
It is necessary to delay the start timing of the read signal or the write signal in the next basic bus cycle. However, delaying the above timing is against the speeding up of the basic bus cycle. Therefore, in order to eliminate the bite into the next basic bus cycle in the memory access device having the above-described operation sequence, there is a problem that a memory having a high operation speed is eventually required.

The present invention has been made to solve the above problems, and an object of the present invention is to operate at a frequency twice as high as a basic bus cycle in a memory access of a microprocessor so that the memory itself. The object of the present invention is to provide a memory access device with an improved operation sequence that does not require a high-speed memory system, such as an attempt to increase the operation speed, and to realize a high-speed computer system at low cost.

[0005]

The structure of the invention for solving the above-mentioned problems is a memory which is accessed in a basic bus cycle in which four transitions of the level of a clock signal consisting of two level states are set as one unit. In the access device, address signal output means for starting the transition of the address signal in synchronization with the first transition of the level of the clock signal in each of the basic bus cycles, and at the time of reading,
Start the level transition of the read signal in synchronization with the second transition of the level of the clock signal of the basic bus cycle, and synchronize with the first transition of the level of the clock signal of the next basic bus cycle. Read signal output means for restarting the level transition of the read signal and returning the level of the read signal to the original state, and at the time of writing,
The transition of the level of the write signal is started in synchronization with the second transition of the level of the clock signal in the basic bus cycle, and is synchronized with the fourth transition of the level of the clock signal in the same basic bus cycle. Write signal output means for starting the level transition of the write signal again and returning the level of the write signal to the original state, and the read signal by the read signal output means or the level of the write signal by the write signal output means The transition of the data signal is started at the same time as the transition of the data signal is started or at a timing after that, and the data signal is again synchronized with the first transition of the level of the clock signal of the next basic bus cycle. Data signal input / output means for starting the transition of the data signal and returning the data signal to the original state.

[0006]

In the basic bus cycle, four transitions of the level of the clock signal consisting of two level states are set as one unit, and the address signal output means makes the first transition of the level of the clock signal every basic bus cycle. The transition of the address signal is started in synchronization. At the time of reading, the read signal output means starts the transition of the level of the read signal in synchronization with the second transition of the level of the clock signal of the basic bus cycle. Then, the read signal output means starts the transition of the level of the read signal again in synchronization with the first transition of the level of the clock signal in the next basic bus cycle, and the level of the read signal is in the original state. Returned to. Further, at the time of writing, the write signal output means starts the transition of the level of the write signal in synchronization with the second transition of the level of the clock signal in the basic bus cycle. Thereafter, the write signal output means starts the level transition of the write signal again in synchronization with the fourth transition of the level of the clock signal in the same basic bus cycle, and the level of the write signal returns to the original state. Will be returned. Then, at the same time when the level transition of the read signal by the read signal output means or the write signal by the write signal output means is started by the data signal input / output means, or the transition of the data signal occurs at a timing thereafter. Be started. Thereafter, the data signal input / output means starts the transition of the data signal again in synchronization with the first transition of the level of the clock signal in the next basic bus cycle, and the data signal is returned to the original state. As a result, the read timing is from the second transition of the level of the clock signal of the basic bus cycle in which the read signal is active to the first transition of the level of the clock signal of the next basic bus cycle. The write timing is from the second transition of the level of the clock signal of the basic bus cycle in which the write signal is active to the fourth transition of the level of the clock signal of the same basic bus cycle. Then, the transition of the data signal occurs at the same time when the read signal or the write signal is activated, or
From the subsequent timing to the first transition of the level of the clock signal of the next basic bus cycle.

[0007]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 is a block diagram showing a semiconductor integrated circuit using a memory access device according to the present invention. The microprocessor 5 is mainly composed of a central processing unit (hereinafter referred to as CPU) 1, a memory management unit (hereinafter referred to as MMU) 2, and a memory access device 3. The semiconductor integrated circuit 6 is composed of the memory 4 and the microprocessor 5. The semiconductor integrated circuit 6 may include a part or all of the memory 4 or may not include it at all. CPU1 and MM
The U2, the memory access device 3, and the memory 4 are mainly connected by the following signal lines. CPU1
And MMU2, MMU2 and memory access device 3, memory access device 3 and memory 4, and CPU1 and memory access device 3 are address signal lines 10 and 11, respectively.
12 and 13 are connected to each other. Also, CPU1
The memory access device 3 and the memory access device 3 and the memory 4 are connected by data signal lines 14 and 15, respectively. Further, between the memory access device 3 and the memory 4, a read signal line 16, write signal lines 17 and 18, a read / write selection signal line 19, a byte / word selection signal line 20,
Then, they are connected by a data strobe signal line.
Signals having the same name are transmitted via the above-mentioned signal lines.

FIG. 2 shows an operation timing chart at the time of reading in the basic bus cycle of the memory access device according to the present invention. The basic bus cycle is 4 times the level of the clock signal composed of the first clock T _s and the second clock T _e.
The transition is one unit. That is, the operation sequence of the memory access device operates with a clock signal having a frequency twice that of the basic bus cycle. At the time of reading, the read / write selection signal becomes Hi which permits the read state in synchronization with the rising of the first clock T _s of the basic bus cycle based on the instruction from the CPU 1. At this time, the address signal,
The read signal and the data signal operate at the timing shown in FIG. That is, the address signal transition is started in synchronization with the rise of the first clock T _s of the basic bus cycle. The read signal starts transition in synchronization with the fall of the first clock T _{s in} the basic bus cycle. Then, in synchronization with the rise of the first clock T _s of the next basic bus cycle, the transition of the level is started again and the state is returned to the original state. The transition of the data signal is started at the timing after the transition of the level of the read signal is started.
Then, the transition is started again in synchronization with the rising of the first clock T _s of the next basic bus cycle, and the original state is restored. In the above-mentioned timing operation sequence, the important point in using the low-speed memory during reading is
It is the length of the section in which the read signal is transited to become the active state Lo. That is, the longer the length, the more accessible the low speed memory. In the present invention, from the fall of the first clock T _s of the basic bus cycle to the rise of the first clock T _s of the next basic bus cycle, L
It is about 3/4 of the basic bus cycle, which is much longer than the conventional one.

FIG. 3 shows an operation timing chart at the time of writing in the basic bus cycle of the above memory access device. As in the case of reading in FIG. 2, the basic bus cycle uses four transitions of the level of the clock signal composed of the first clock T _s and the second clock T _e as one unit. That is, the operation sequence of the memory access device is operated with the clock signal having a frequency twice as high as the basic bus cycle. At the time of writing, the read / write selection signal becomes Lo which permits the write state in synchronization with the rising of the first clock T _s of the basic bus cycle based on the command from the CPU 1. At this time, the address signal, the write signal and the data signal are shown in FIG.
It operates at the timing shown in. That is, the address signal starts to transition in synchronization with the rising edge of the first clock T _{s in} the basic bus cycle. Further, the write signal starts transition in synchronization with the falling edge of the first clock T _{s in} the basic bus cycle. Then, in synchronization with the fall of the second clock T _e of the basic bus cycle, the transition of the level is started again and the original state is restored. Further, the transition of the data signal is started at the timing after the transition of the level of the write signal is started. And the first of the next basic bus cycle
The transition is started again in synchronization with the rising of the clock T _s , and the original state is restored. What is important in using the low-speed memory at the time of writing is the length of the section that is Lo of the write signal and the timing of its end. That is, the length of the section of the write signal, which is Lo, is preferably as long as possible, but as described above, the write time is sufficient even when the section of Lo is not long as in the read operation. At the time of writing, the data signal is not returned to the original state by the rise of the first clock T _s of the next basic bus cycle, and in order to prevent erroneous writing of data, the write in the next basic bus cycle is performed. It is necessary to delay the start of the signal level transition. Then, the length of the section that is Lo of the write signal becomes shorter by that amount, and it becomes necessary to use a high-speed memory. Therefore, in order to avoid the above-mentioned state, the end timing of the write signal is ended earlier than other signals, and the writing is ended by the rising edge of the first clock T _s of the next basic bus cycle,
At the same time, the memory access device has an operation sequence of returning the data signal to the original state. In the present invention, the write signal is Lo from the fall of the first clock T _{s to} the fall of the second clock T _e of the basic bus cycle, and the transition of the data signal starts the transition of the level of the write signal. Since the timing is from the timing after that to the rising of the first clock T _s of the next basic bus cycle, the above inconvenience does not occur.

Although the byte / word selection signal and the data strobe signal shown in FIGS. 2 and 3 are not essential in the present invention, they are often necessary in constructing a computer system. is there. Part-Time Job/
The word select signal is the access type of the data, that is,
If the byte / word selection signal is Hi, it is a signal indicating that word-type (2-byte type) data access is performed, and if the byte / word selection signal is Lo, it is a signal indicating that byte-type data access is performed. The data strobe signal is an intermediate signal for producing a read signal or a write signal by combining with the read / write selection signal, and is a necessary signal depending on the type of memory.

FIG. 4 is a table showing numerical examples corresponding to the variables in the operation timing charts of FIGS. 2 and 3 as an example of bus timing by the memory access device of the present invention. Than the value shown in the table, the basic bus cycle is a _{2T C = 2 × 50 = 100} , 2T C - (T H + T R + T RDF) = 100- because it is (22 + 3 + 10) = 65, the basic bus cycles About 6 for 100 ns
A low speed memory of 5 ns access can be used.

[0012]

According to the present invention, the address signal output means starts the transition of the address signal in synchronization with the first transition of the level of the clock signal in each basic bus cycle, and at the time of reading, the read signal output means. By this, the level of the read signal becomes active from the second transition of the level of the clock signal of the basic bus cycle to the first transition of the next basic bus cycle, and at the time of writing, the write signal is output by the write signal output means. The level is in the active state from the second transition to the fourth transition of the level of the clock signal of the basic bus cycle, and the section in which the gate opens with respect to the data signal is a read signal during a read or a write signal during a write. Are activated at the same time, or the next basic bus cycle after that. It is until the first transition of the clock signal level, and the period in which the read signal becomes active is approximately 3/4 of the basic bus cycle, which is very long compared to the conventional one, so low-speed memory can be used. .. Also, since the write signal returns from the active state to the original state earlier than other signals in the basic bus cycle, erroneous writing does not occur. That is, the memory access device of the present invention operates at a frequency twice as high as the basic bus cycle, and a low-speed memory can be used without increasing the operating speed of the memory itself, and as a result, the low-speed memory can be used without impairing reliability. This has the effect of realizing a high-speed computer system at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit using a memory access device according to a specific embodiment of the present invention.

FIG. 2 is an operation timing chart at the time of reading in the basic bus cycle of the memory access device according to the embodiment.

FIG. 3 is an operation timing chart at the time of writing in the basic bus cycle of the memory access device according to the embodiment.

FIG. 4 is a table showing numerical values corresponding to variables in the operation timing diagrams of FIGS. 2 and 3 as an example of bus timing by the memory access device of the present invention.

FIG. 5 is an operation timing diagram at the time of reading and writing in the basic bus cycle of the conventional memory access device.

[Explanation of symbols]

1-CPU 2-MMU 3-Memory access device 4-Memory 5-Microprocessor 6-Semiconductor integrated circuit 10-13-Address signal line 14,15-Data signal line 16-Read signal line 17,18-Write signal line 19 -Read / write selection signal line

Claims (1)

Claim: What is claimed is: 1. A memory access device for accessing a memory in a basic bus cycle in which four transitions of a level of a reference periodic signal composed of two level states are set as one unit. Address signal output means for starting the transition of the address signal in synchronization with the first transition of the level of the reference cycle signal, and the second level of the level of the reference cycle signal of the basic bus cycle during memory read. The level transition of the read signal is started in synchronization with the first transition, and the level transition of the read signal is started again in synchronization with the first transition of the level of the reference period signal of the next basic bus cycle. Read signal output means for returning the level of the read signal to the original state, and the reference cycle of the basic bus cycle at the time of memory writing. Of the write signal is started in synchronization with the second transition of the level of the write signal, and again in synchronization with the fourth transition of the level of the reference period signal of the same basic bus cycle. Write signal output means for starting the level transition and returning the level of the write signal to the original state, and level transition of the read signal by the read signal output means or the write signal by the write signal output means is started. At the same time as or after that, the transition of the data signal is started, and the transition of the data signal is started again in synchronization with the first transition of the level of the reference period signal of the next basic bus cycle. And a data signal input / output unit for returning the data signal to the original state.