JPS61264453A - Storage circuit - Google Patents

Abstract

PURPOSE:To synthesize a multi-value picture data at high speed by providing an arithmetic function to a storage circuit and carrying out the read-out and arithmetic in the storage circuit with a single access. CONSTITUTION:The read data DO and the external data DI undergo the arithmetic through a control circuit 1 with indications of the external control signals CNT and Cr. While the write data Z of the arithmetic result is written to a storage element 2. When both signals CNT and Cr are equal to 0, such a mode is set that the data DI serves as a control signal which decides whether the data DO of the element 2 is transmitted as it is or inverted. While a mode where the data DI is transmitted as it is is secured when the signals CNT and Cr are equal to 0 and 1 respectively. When the signal CNT is equal to 1, the data DO, the data DI and the signal Cr are added together.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage element, and more particularly to a storage circuit suitable for an image memory for processing high-speed multivalued image data.

[Background of the invention]

The prior art will be explained by taking image processing as shown in FIGS. 2 and 3 as an example.

In FIG. 2, Ml is the memory area where the original multi-value image data is stored, M2 is the memory area where the multi-value image data to be synthesized is stored, and M1' is the multi-value image data storage area after calculation. .

Further, in FIG. 3, 81 is a processing step for reading data from memory area M1, 82 is a processing step for reading data from memory area M2, and 85 is a processing step for reading data from memory area M1 and memory area M2. A processing step 84 is a processing step for writing the combined data obtained in S6 to the memory area M1.

Since the multivalued image data processing shown in FIG. 2 is a normal combination, addition is performed as an operation. As a result,
In the overlapping area, the data value increases and becomes darker as shown by the crosshatch. Generally, the amount of data in a memory area is large, ranging from several hundred kilobytes to several tens of megabytes, and most data units handled by an arithmetic processing unit range from 8 bits to 52 bits. As a result, as shown in FIG. 5, the number of repetitions of the data processing steps 81 to 84 is on the order of 10 to 10, assuming 52 bits as 1 arithmetic unit. Since the number of repetitions is large as described above, most of the image data processing time is the processing time in the loop shown in FIG. As a result, image data processing uses more time for memory access than for data calculation processing. (Out of the four steps from Sl to 84, three steps, Sl, Sl, S4, are memory accesses). As described above, in processes that require large-capacity memory access, such as image data processing, even if the processing speed of the processing unit is improved, the processing time is determined by the memory access time, and the processing time of the processing unit is limited. The disadvantage is that the effective calculation speed does not improve.

Note that a memory circuit that performs this type of processing is disclosed in, for example, Japanese Patent Laid-Open No. 129387/1983.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage circuit that can perform image processing of multivalued image data, multi-length arithmetic processing, etc. at high speed in order to overcome the above-mentioned drawbacks.

[Summary of the invention]

The present invention is a storage circuit having the following five functions, for example, in order to speed up the above-mentioned multivalued image data synthesis process (addition process between image data).

(1) A function for writing external data to a storage element.

(2) A function for executing logical operations on data already stored in the storage element and external data and writing the operation results to the storage element.

(3) Processing function of executing arithmetic operations on data already stored in the storage element and external data and writing the operation results to the storage element.

A memory circuit with these three functions was realized by focusing on the following points.

In many arithmetic processes other than the above-mentioned multilevel image data synthesis process, what is required is a binary arithmetic operation and a two-operand arithmetic operation. That is, there are many operations in the form of D-DopS (OP is an operator), D 4-81 op 8. Polynomial operations and multi-operand operations such as op----op3n are rarely used. A processing unit (CPU) performs this two-term and two-operand operation.
When performing the operation between data in a memory element and data in a memory element, if the storage destination of the operation result is a register of the CPU (D is a register and S is a memory element), accessing the memory element is sufficient, but vice versa. In the case of (the above is a memory element and S is a register)
So, it will be accessed twice. In many data processes, including multilevel image data processing, the latter operation using D as a storage element is often used because more data is handled than the number of registers in the CPU, and furthermore, both operands are used as storage elements. This is often the case. Accessing S is essential for reading data, but accessing D twice for reading and writing means accessing the same storage element twice for one operation.

That is, DRAM (Dynamic Random A
Read used in accessMemory)
Using Modify Write, arithmetic functions are added to the memory circuit, and reading and arithmetic are executed within the memory circuit.
To allow one access to the same storage element for one operation.

That is, in a memory element in which data can be read, written, and saved as desired, a normal write mode is used in which first data is stored in the memory element from first data from the outside and second data within the memory element. and a logical operation mode in which data as a result of a logical operation of the first data and second data is stored in a storage element, and an arithmetic operation mode in which data as a result of an arithmetic operation in the first data and second data is stored in a storage element. It is characterized by the provision of a control circuit that can take different modes.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

First, the present invention will be explained in detail. In Figure $4, Read
Modify Write (An example of a memory cycle modification chart is shown in FIG.
Input DR is the address from the CPU, WR is the ride request signal from the CPU, RAS is the row address strobe,
CA8 is a column address strobe.

A is a time division address signal for rows and columns, WE is a write enable, and DO is DRAM read data.

Z is data resulting from calculation of data from DO and CPU. The section indicated by ■ in FIG. 4 is the memory setup section, and ■ is the calculation (Modif y) section;
■ is the light section. In a normal memory write, the section ``■'' is eliminated, and one memory cycle y becomes shorter, but it is still more than half the time, so one Read Modify Write access takes more time than two Read and Write accesses. is shortened, and processing speed can be increased. 70-chat showing the process corresponding to FIG. 5 according to the present invention is shown in FIG.

Next, one embodiment of the present invention will be described.

FIG. 1 shows the memory circuit of this embodiment. In Figure 1,
1 is a control circuit, 2 is a memory element, and 3 is a DRAM driver)
a-RA, CNT, Cr are external control signals, DI is external data, Z is write data to the storage element, DO
is read data from the storage element, P and G are operation result states, A, WE, CAB.

RAS, ADR, and WR are the same signals as in FIG. 4.

As shown in FIG. 4, in this embodiment, the read data signal and external data DI are connected to an external control signal CNT.

The control circuit 1 performs calculations according to instructions from Cr, and writes write data 2 as a result of the calculations to the storage element 2. The control operation mode of the control circuit 1 is shown in FIG. External control signals CNT and C
When r is 0, the external data DI is the control signal for whether to pass the read data Do of the storage element 2 as is or to invert it. When the external control signal CNT is 0 and Cr is 1, the external data DI is This is a mode in which the data DI is passed through as is, and when the external control signal CNT is 1, it is a mode in which the read data DO, external data DI, and external control signal Cr are arithmetic added.

A specific example of a circuit realizing the above control operation mode is shown in FIG. In the seventh cause, G1. Arithmetic addition is realized by the ENOR gate of G2, and G6°G7. The condition that the external control signal CNT is 0 and Cr is 1 is detected at the gate of oa, and the gates of G5, G4 . E with the selector consisting of the gate of G5
Selects the output of NOR gate G2 or external data DI. G9 Carry Look ahead (D G
NAND gate that generates the generate signal G, G1
0 is the same (Carry Lookahead cr)
This is an AND gate that generates a propagate signal P. The logical expressions of the output signals Z, P, and G of the control circuit 1 are shown in FIG.
The d signals P and G have constant values when the external control signal CN is 0 (P=O).

Take G=1).

FIG. 8 shows the configuration of a 4-bit operation memory using four memory circuits of this embodiment. In FIG. 8, in order to simplify the explanation, only the part mainly in the arithmetic operation mode is shown. 11.12,13. i4 is the memory circuit shown in the first @,
G11 to 028 perform carry processing +7) Ca
The gate F constituting the rry Lookahead circuit is a register that stores the carry result after the operation.

The memory circuit 11 corresponds to the least significant bit, and the memory circuit 14 corresponds to the most significant bit. Although register F is omitted in the figure to avoid complexity, a circuit for setting it to 0 and 1 from the outside is added. Carry result (goo) G29
The output logical formula is G, +GS ・P, +G, -P3-P4+G, -P
, -P3-P, -)-Cr-PleP, ・P, ・P4
When the external control signal CNT is 0, Pi = 1
, Gi = 0 (where i is an integer from 1 to 4)
Therefore, the above logical formula becomes only C', and the value of register F does not change due to the write operation.
2. Similarly, Cr, , and Cr have the same value as Cr, so the five operating states when the external control signal CNT is 00 do not change due to the write operation. When the value of the external control signal CNT is 1, the carry control signals p, , pt, p, of the memory circuits 11, 12, 13, and 14.

P4, G1. C%, ()S, G4)j Car
ry J, ookahead er) signal, normal addition can be realized.

As shown in FIG. 6, although there are few operating modes of the control circuit 1, as an input of the external control signal Cr and external data DI,
Logic O2 Logic 1. By selecting the write data D and its inverted data D from a microprocessor or the like, the operational func- tion increases.

FIG. 9 shows an example in which the above circuits are combined. Figure 9(a)
is a concrete circuit of the least significant bit, and FIG. 9(b) is its operational function.

The gates 029 to G55 constitute a selector for the external control signal Or, and the gates 034 to G57 constitute a selector for the external data DI. S.O.S.
l is a select control signal of the selector of the external control signal Cr;
82 and 83 are select control signals for the external data DI selector. FIG. 9(C) shows a circuit for the upper bits. The difference from FIG. 9(a) is that when the external control signal CNT is 1, the gates 038 to G44 are configured to input a carry signal (:ri-1) from the lower bit to the external control signal Cr. The selector for the external data DI is shown in Figure 9 (
It has the same configuration as a). With the configuration shown in FIG. 9, the memory circuit can perform 16 types of logical operations and 6 types of arithmetic operations with one memory write access. For example, when superimposing the multivalued image data shown in FIG. 2, the select signal SO is set to 0. By setting S2 from 0.85 to 1, reading the multi-value image data memory and writing it to the operand multi-value image data memo IJ Ml, each data is added, resulting in the calculation result data M1', which is processed at high speed. This makes it possible to superimpose multivalued images. Similarly, select signal S
O to 1. Sl 182 1. By setting S5 to 1, subtraction is designated, and as shown in FIG. 10, it becomes possible to delete unnecessary portions (noise, etc.) of multivalued image data.

Similar to the superimposition process, this process can be realized by simply repeating reading of the deletion data memo IJM3 and writing to the operand data memory, so high-speed processing is possible.

According to this embodiment, (1) Multi-level image data processing changes from six memory access repetitions to two memory access repetitions, making it possible to speed up processing such as superimposition and deletion.

(2) Data calculation between memories is realized on the memory side, so it is not only possible to use devices such as microprocessors that have arithmetic functions, but also DAM (Direct Memory,
Multilevel image processing is possible even in a device that does not have an X function, such as a yF roller.

(5) By adopting the circuit configuration shown in Figure 8, carry processing is also performed during memory write access, so multiple-precision arithmetic operations can be realized only by memory writes, resulting in high-speed multiple-precision arithmetic operations. becomes possible.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to achieve the effect that multi-value image data synthesis processing and multi-value I# data deletion processing can be executed at high speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a storage circuit according to an embodiment of the present invention, Fig. 2 is a diagram for explaining multi-value image data processing, Fig. 5 is a flowchart showing multi-value image data processing, and Fig. 4 is a diagram for explaining multi-value image data processing. A timing chart showing memory access, a TGS diagram showing a flowchart showing multivalued image data according to an embodiment of the present invention, FIG. 6 a diagram for explaining the operation mode of the control circuit, and FIG. 7 a configuration of the control circuit. A diagram showing an example, Figure 8 is 4
FIG. 9 is a diagram showing an example of a bit operation memory configuration, FIG. 9 is a diagram for explaining an application example of this embodiment, and FIG. 10 is a diagram for explaining multivalued image data deletion processing. °1...control circuit, 2...memory element, 5...Di(, AM controller, 1
1.12, 13.14... Song memory circuit, DI...
・External input data, DO...Memory read data, Cr...
・External control signal (carry, etc.), CNT... External control signal (calculation mode), Z... Calculation write data.躬I Otsumo 2nd mouth 30th also 50th Q Gokude<C”;c< li \ (Q N Fig. 6 1O mouth r13' 7th mouth Z= (C#7' Cy-) □I Ten (0 below cr) - (o
r■D 00Cr) 8th mouth. -i Q

Claims (1)

[Scope of Claims] 1. In a memory element in which data can be read, written, and stored arbitrarily, the first data is stored in the memory from external first data and second data within the memory element. a normal write mode in which data is stored in the element; a logical operation mode in which data resulting from a logical operation of the first data and the second data is stored in the memory element; 1. A storage circuit comprising a control circuit that can take an arithmetic operation mode for storing data resulting from an arithmetic operation in the storage element. 2. The memory circuit according to claim 1, wherein the three modes in the control circuit are specified by a plurality of external control input signals. 3. The memory circuit according to claim 1, wherein the three modes in the control circuit are specified by two external control input signals. 4. The memory circuit according to claim 2 or 3, wherein one of the control input signals from the outside distinguishes the three modes into two types. 5. The memory circuit according to claim 4, wherein two types of the three modes are distinguished as a normal write mode, a logical operation mode, and an arithmetic operation mode. 6. Claims 2, 3, 4, or 5, characterized in that when specifying an arithmetic operation mode, one of the external control input signals is used as a carry input signal. Memory circuit described. 7. Claim 5, characterized in that the normal write mode and the logical operation mode are distinguished by a control input signal different from an external control input signal that specifies the distinction between the two types of the three modes. Memory circuit described. 8. The memory circuit according to claim 1, wherein the logical operation in the logical operation mode is an exclusive OR of the first data and the second data. 9. The storage circuit according to claim 1, wherein the arithmetic operation in the arithmetic operation mode is a carry addition of the first data and the second data. 10. The memory circuit according to claim 9, which outputs a carry result of arithmetic addition in an arithmetic operation mode. 11. Two selectors for selecting one data from a plurality of input data are provided, the output of the first selector of the two selectors is used as the input of the first data, and the output of the second selector is used as the input of the external data. According to claim 1, 2, 3, or 4, the output selection of the two selectors is specified independently from each other. memory circuit. 12. The memory circuit according to claim 6 or 7, wherein the carry input signal and the control input signal for distinguishing between the normal write mode and the logical operation mode are the same signal. . 13. The input data of the first selector in the arithmetic operation mode is the first data from the outside and its inverted data, and the input data of the second selector is 0 and 1. Claim 9 or 1
The memory circuit according to item 1.