JPS6352245A - Memory device - Google Patents

Abstract

PURPOSE:To process pictures at a high speed by providing a means which fetches a command from an address bus and a parameter from a data bus respectively. CONSTITUTION:This memory device consists of memory devices #iM (i=0-3) of the same constitution that forms a 4-screen frame memory. Each device #iM contains memories M0-M7, bit interfaces BTI0-7, a pixel interface PXI-0, and a timing command control TCC consisting of a timing control TC and a command control CC. The control CC holds the input of a command on an address bus by the control signals WE, CAS and CSW together with the input of parameters produced by the commands of data buses IO0-IO7. Then the control CC decodes those commands and delivers the control signal to a control TC. The control TC processes the memories M0-M7 and interfaces BTI0-7 by the control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" This invention, for example, stores image data and
The present invention relates to a memory device that can easily perform logical operations with predetermined data when writing image data.

``Prior Art'' Memory used for image display tends to become faster and larger in capacity in response to demands for multicolor display and high resolution display. The capacity of the frame buffer in which image data for image display is stored is proportional to the size and resolution of the display area, as well as the number of display screens (for example, when multiple screens are prepared in advance) and the number of display colors. increases accordingly.

For example, in the case of 16-color display, 4 bits are required as a color code, so frame memories FMO to FM3 for four sides are required as shown in FIG. In this case, data surrounded by a broken line (the direction of this broken line is hereinafter referred to as a pixel direction) at the same bit position in each frame memory FMO to FM3 corresponds to one dot on the display surface. When displaying an image, data is sequentially read out for each pixel of each frame memory FM0 to FM3 as the display surface is scanned, thereby making it possible to display multiple colors. In addition, in reality, four dual port memories are used as frame memories FMO to FM3.
from the serial data output end of each chip.
A method is generally adopted in which pixel data is read out synchronously. In the case shown in FIG. 18, the access direction when accessing in units of words is hereinafter referred to as the word direction (indicated by a dashed-dotted arrow in the figure).

"Problems to be Solved by the Invention" By the way, in image processing, it is better to add functions (special functions) to perform various processes to the memory section (or memory device) itself to make control easier and faster. It may be advantageous in some respects. Therefore, a device with various functions added to the memory section has been developed. By the way, in a system in which a plurality of memory sections are provided, there arises a demand to set special functions in common to all memory sections, and to supply parameters related to the special functions to each memory section individually.

However, there is no conventional memory device that satisfies the above requirements, and the development of one has been desired.

This invention was made in view of the above-mentioned circumstances, and although it has a simple configuration, special functions can be commonly given to each memory section, and parameters can be given individually.
Moreover, it is an object of the present invention to provide a memory device that can speed up the processing.

"Means for Solving the Problems" In order to solve the above-mentioned problems, the present invention is composed of a plurality of memory sections having a common address bus, and each memory section has a special function. The memory device is characterized in that each memory section is configured to commonly take in the function designation code from the address bus, and to take in parameters from the data bus.

"Operation" Since the function specification code is supplied to each memory section from a common address bus, the same function is necessarily specified for all memory sections, and the parameters are sent to each memory section via the data bus. Since the parameters are supplied to each section, individual parameters can be freely set as necessary.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Overall Configuration of Embodiment FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In this figure, M, -M.

are 1 bit x 64K (or 128K) memories, each of which is connected in parallel to form an 8 bit x 64K (or 128K) memory block MBO. BTl, ~BT I7 are memories M0 to M7, respectively.
It is a bit ink-face that controls data transfer between the PX
I-0 is a pixel interface that exchanges any l-bit data in the pixel direction (hereinafter referred to as pixel data) with the data bus IQp-o, and also reads chip select data or brain mask data to be described later. It is a circuit. This pixel interface circuit PXI-0 is a bit interface BTIo~BTI? Memory M via either. - Bit interface BTI is designed to exchange data with either M7, and also sends control signals for chip select data and plane mask data to the bit interface BTI.

~BTI7 and the timing command control circuit TCC.

Timing command control circuit '1' CC
are address data supplied from the outside via address buses AO to A7, an output enable signal (control signal) OE, a write enable signal 'vVE', a row address strobe signal Rt', S, and a column address strobe. This circuit controls access to memory block MBO and timing of each part of the circuit based on signals C, AS, etc. Additionally, the timing command control circuit TCC controls the memory M0 to M7 according to the value of bit mask data (described later) supplied from the bit interfaces BTIo to BTI7.
It is designed to control the write enable signal of.

Furthermore, timing command control circuit TC
C decodes the command data supplied from the address buses AO to A7, and controls each part of the circuit as appropriate based on the decoding result.

The above-described components constitute the memory device #OM. This embodiment consists of a total of four parts: a memory device #OM and memory devices #IM to #3N1 having the same configuration.

In this case, the memory block in each memory device #IM to #3M is MHI-Mn2, the pixel interface is PX I-1-PX I-3, and the data bus connected to each pixel interface is l0p- 1-
It is expressed as 10p-3 and distinguished.

FIG. 2 shows the connection state of the memory devices #0 to #3M, and as shown in this figure, each memory device #O
, M to i# 3 M data buses 100 to 107 are commonly connected for each bit, and each memory device #OM to #3
The M data buses Iop-o to 101)-3 are each individually wired.

@Configuration of each part of the embodiment Below, the configuration of each part of the circuit described above will be explained in more detail.

(1) Overview of operating modes for understanding the configuration First, in order to facilitate understanding of the configuration of each part of the circuit, the operating modes in this embodiment will be briefly explained.

(a) Normal mode This mode is a mode in which one of the memory devices #ON1 to #3M is selected and data access is performed in units of 8 bits for the selected memory device. Data in this mode is transferred to the data bus I Oo = I O?
input/output via . That is, this is a mode in which normal 8-bit parallel access is made to any one of the memory devices #OM to #3M.

(b) Mask mode In this mask mode, 2 or more bits of input/output data can be masked, and furthermore, any 1 or 2 or more of memory devices #OM to #3M can be masked. This is the mode that will become. This mode is further divided into word access mode and pixel access mode, and in the case of word access mode, data bus I
O. -10t, word direction data input/output is performed, and in pixel access mode, data bus 1
Data is input and output in the pixel direction via 0p-o to 10p-3. In the mask mode, it is also possible not to mask any bits or any memory devices.

In the word access mode, data in the word direction of memory blocks MBO to MB3 shown in FIG.
%%), and if you want to perform a bit mask, do the following. For example, if you want to access only bs, b'+ bits shown in FIG. 18, access memory block MBO in the word direction to access wd, (8 bits), and of this 8-bit data, bs, bits other than b7 are masked to prohibit access, and b3. access b.

Further, the pixel access mode is, for example, a mode in which access is performed in the pixel direction of memory blocks MBO-MB3 shown in FIG. 18 (see broken lines), and when bit masking is performed, it is performed as follows. For example, when accessing only the pbl and Pbx bits shown in FIG.
Pixel pCo is accessed, memory blocks MBO and MB3 are masked, and pbl and pbt bits are accessed.

The above is an abbreviation of the operation mode 'e1' in this embodiment.

(I[) Configuration of each part Next, the configuration of each part of the circuit shown in FIG. 1 will be explained.

Note that since the memory devices #OM to 3M all have the same configuration, the following configuration will be explained using the memory device #OM as an example.

[Timing command control circuit TCC] This timing command control circuit TCC is
As shown in Figure 1, the timing control convex circuit T
3 and 4, each of which is shown in FIGS. 3 and 4.

In FIG. 3, Ta=Te is a control signal input terminal, and the terminal Ta has a row address strobe signal RA.
S, a chip select signal C8W specifying whether or not to select the memory device #OM is applied to the terminal Tb, a column address strobe signal CAS is applied to the terminal Tc, a write enable signal WE is applied to the terminal Td, and the terminal An output enable signal OE is supplied to each Te. DL is the row address strobe signal RA
This is a delay that delays S to create the signal RASD, and OR1 is an OR gate that takes the logical sum of the row address strobe signal RAS and the signal RASD to create a signal RASW with a longer pulse width of the row address strobe signal RAS. It is. LFF1 is a latch type flip-flop (hereinafter referred to as L type flip-flop) that captures the value of the chip select signal C8W at the rising edge of the signal RASW, and ANI detects that the normal mode is specified and outputs the normal mode enable signal N M
The AND gate AN2 that outputs E detects that the mask mode is specified and outputs the mask mode enable signal M.
An AND gate AN3 that outputs ME is an AND gate that detects that a command write cycle, which will be described later, is designated and outputs a command enable signal MCE. LFF2゜LFF3. LFF4 is an L-type flip-flop that takes in the values of the enable signals NME, MME, and MCE at the rising edge of the signal RASW, and outputs the signals NMA, MKA, and MCC from its output terminal. Output. Also,
AN4 to AN9 are AND gates that create the illustrated signals based on the above signals and control signals supplied from other circuits, and AN10 = AN17.
are respectively bit interfaces BT1. ~BTI, bit mask signal B M o ” B M
t and the signal WEP supplied from the AND gate AN8. -Write enable signal WEPO~WEP of M7 (see FIG. 5)? It is an and gate that creates. A N l 9 ANDs the signal OEW with the output signal of the delay DL2 which delayed this signal OE W, and as a result delays the signal OE W;
This is an AND gate that creates a signal OEE with a narrowed pulse width. The L-type flip-flops LFFI-LFF4 in the above configuration are configured to latch data when a 1'' level signal is supplied to each latch terminal having a negative logic.

Next, referring to FIG. 4, the command control circuit C
C will be explained. TadO to Tad7 not shown in this figure
are address data input terminals, and these address data input terminals TadO to Tad7 are each connected to the input terminal of the command register I. A command in this embodiment is specified by an 8-bit command code (function designation code), and this command code is supplied via an address bus.

The command register l latches the command code at the rise of the row address strobe signal RAS,
This is output as command data MC0 to MC7. In this case, the upper 4 bits of the command data become main command data, and the lower 4 bits become subcommand data. However, as can be seen from the figure, the most significant bit MC7 of the command data is a don't care hit.

Here, m(1'6) of command data M C0 to MC7
The following table shows the relationship between the command name and the command name.

In addition, in the lower-order data column of the following table, M Cl =1
, MC2=1 means that if the relevant bit is "1", the other bits are don't care, and (coefficient) means that all of the lower data is coefficient data (described later).
It has been shown that it functions as

Table 1 Command Data Command Name Upper Lower 0 0 Word Access Mode 1 Pixel Access Mode 2 Conveyor Data Disable 3 Conveyor Data Enable 4 Plane Mask Disable 5 Plane Mask Enable 6 Bit/Chip Select Mask Disable 7 Bit/Chip Select Mask Enable S...E Raster operation disable F Raster operation enable 1 0 Read plane mask l Write plane mask 3 Plane pattern register 4 Plane destination register 6 Pattern register 7 Destination register F...2 ...... 3 (MC1=1) Pattern load enable (MC2.1) Destination load enable 4 (coefficient) Raster operation code (LOW
) 5 (coefficient) Raster operation code (HIG
H) S , = , = Note that Table 1 lists only commands related to this invention. Further, the functions of the described commands will be described later.

Next, the decoding circuit 3 shown in FIG.
It has 8g of D-type flip-flops numbered θ to 7th that output ME, PME, BCE, LSE, FSB, DBT, and ROE, respectively. A D type flip-flop is selected. That is,
The D type flip-flop whose number corresponds to the 3-bit data supplied to the input terminal is selected. Then, the data supplied to the data terminal DT is supplied to the input terminal of one of the D-type flip-flops selected at that time, and when the output signal MDS of the AND gate AN21 rises, the data is supplied to the input terminal of one of the D-type flip-flops selected at that time. It is now being incorporated into the That is, the signals PAM, CME, PME, BCE, LS are controlled depending on the values of the command data NIC1 to MC3.
E, FSB, DBT, ROE is selected, and the value of the selected signal is the value of command data MCO (“l”
/“0”). The clear terminal CL of the decode circuit 3 is supplied with a reset signal from the power-on reset circuit 5, and as a result, when the power is turned on, all of the D-type flip-flops numbered 0 to 7 are activated. It is now cleared. Also,
The output signal ROE of the decoding circuit 3 is an AND gate AN
35 is ANDed with the signal MKA, and the signal ROX
It is designed to determine the value of .

The main command decoder 4 decodes the 3-bit data supplied to the input terminal, and sets the signal of the corresponding number at the output terminal to "1". This main command decoder 4 is designed to output eight types of control signals, but in this figure, a signal R related to the present invention is shown.
Only GA, RL, C, and ROLXROU are shown. Further, the main command decoder 4 is configured to be in an enabled state when the yes word MC5T is supplied from the AND gate AN20.

The decoder 2 decodes the command data N4cO~~IC2 to create the control signal shown in the figure, and uses the signal 'vV supplied from the timing control circuit TC.
It is configured to enter the enabled state when EW becomes a "1" signal and signal RGA supplied from the main command decoder 4 becomes an "1" signal.

This decoder 2 outputs the signal RP W if the value of the command data MC0-MC2 is "O", the signal W P to V if the command data is rlJ, and the OR gate 0 if the value of the command data MC0-MC2 is "r4 j, r7".
The signal WTD, which is the output signal of R21, is
If it is 6J, the signal W TP which is the output signal of the OR gate 0R20 is set to "1", and if "5j, r6 J, r7 j", the signal MCW is set to "1".

The Renostaf captures command data MC1 and MC2 at the rising edge of the signal RLC, and outputs the captured control data MCI and MC2 to the signals PLE and DLE, respectively.
is supplied to one input terminal of each AND gate AN36 and AN37. The other input terminals of the AND gates AN36, 37 are respectively connected to the output terminals of an AND gate AN38, and the input terminal of this AND gate AN38 receives a signal CA S
', V.

OEE, MKA (these are supplied from the timing control circuit TC) and a signal BMi (described later) are supplied. Also, and gate AN3
Each of the output signals of 6.37 is supplied to one input terminal of the OR gate 0R20, 21, so that the output signal WTP
, WTD.

Registers 8 and 9 take in command data MCO to MC3 at the rising edge of signals ROL and ROU, respectively, and register 8 takes in command data MCO to MC3.
MC3 as signal ROCO-ROC3, register 9
is the command data M C0 to MC3 to the signals ROC4 to R
Output as OC7. These signals ROCO to ROC3 and ROC4 to ROC7 become data for determining coefficients in logical operations to be described later.

[Memory block MBO] FIG. 5 is a block diagram showing the configuration of memory block NIBO, and each memory ~1o~ in memory block MBO
~17 takes in the row address output on the address buses AO~A7 at the rising edge of the row address strobe HAS, and inputs the row address output to the column address strobe CAS.
At the rising edge of , the column address on address buses AO to A7 is fetched and the access address is determined. During a read cycle, data is output when the signals OE to V (output enable signal) rise after the access address is determined, and during a write cycle, the signal WEP, when the access address is determined or after that, is output.
~WEP? Data is written to the memory whose level is set to high.

[Human Interface BTIiJ Figure 6 shows the bit interface BTIi(f
FIG. 2 is a block diagram showing the configuration of the i-0 to i-7, and the same shall apply hereinafter. In the figure, 'r I Oi is a data input/output terminal.

In this figure, data input from the data input/output terminal Tl0i is transmitted to the 0th. Second. It is supplied to the third bit input terminal, the 0th bit input terminal of the selector 13, and the input terminal of the L-type flip-flop LFF6.

In the selector IO, the signal PAM is “L” and the signal NMA is “L”.
0", the 0th, 2nd, and 3rd bit input terminals are selected and the data supplied to the bus IOi is output from the output terminal Y, and the signal HM A is "0" and the signal PAM is "1'', the first bit input terminal is selected and pixel direction data DIP supplied from the pixel interface PXI-0 (see FIG. 7) is output from the output terminal Y.

The output signal W D Ti of this selector IO is supplied to the input terminal of the D type flip-flop DFF7, and the D type flip-flop DFF7 receives the signal supplied from the timing control circuit TC. At the same time, the signal 'vV D T i is taken in.

Output signal 5RCi of D type flip-flop DFF7
are supplied to the 8th to 15th bit input terminals and the first bit select terminal of the selector 14, and therefore,
When the data supplied to the 0th to 3rd bit select terminals of selector l = 1 are "8" to "15j (decimal)," data 5RCi is output from output terminal Y of selector 14 as data D to Vi. , buffer BFF3 and data bus DTi sequentially, and the data is supplied to the corresponding memory M i (see FIG. 1). In this case, if the value of the signal ROX is "0", the select terminal of the selector 14 is Since the value of the supplied data is always "8" or more, for writing in the word direction, the data supplied to the input/output terminal Tl0i is transferred from the buffer BFF I to the selector 10-D.
It is supplied to the memory Mi through the path of type flip-flop DFF7 - selector 14 → buffer BFF3, and for writing in the pixel direction, input/output terminal '
The data supplied to rxop-o is sent to buffer BFF
l O-selector 10 → D type flip-flop DF
It is supplied to the memory Mi via the path F7-selector 14-buffer BFF3. In this case, the signal ROX is
As will be described later, this signal becomes "L" only when the mode for performing ethical calculations is set, so in that mode in which logical calculations are not performed, the data supplied to the input/output terminal T10i is routed through the above-mentioned path. It is supplied to the memory Mi through. Further, the buffer BFF3 is enabled when the signal WEP supplied from the timing control circuit TC is "1".

The L-type flip-flop LFF6 is configured to take in data when the signal RASW supplied from the timing control circuit TC rises, and its output signal FB~11 is input to the first bit input terminal of the selector 11. It is now being supplied. The selector 11 has a positive voltage applied to the 0th bit via a pull-up resistor, and selects the 0th bit input terminal when the signal BCE supplied from the command control circuit CC is "0". When the signal BCE is "L", the first bit input terminal is selected.
The output signal of is supplied to the timing control circuit TC as bit mask data B Ml.

The selector 13 selects the 0th . The 0th to 3rd bit input terminals are selected according to the values of the signals MCW and MCC supplied to the 1st bit select terminal, and the 0th bit input terminal selects the data (word direction) from the input/output terminal Tl0i. data) is supplied to the first bit input terminal, pixel data from the pixel interface PXI-0 (or PXI-1 to PXI-3) is supplied to the first bit input terminal, and the second . The data read from the memory Mi at the third bit is stored in the buffer BF.
It is designed to be supplied via F2. The output terminal Y of this selector 13 is a D type flip-flop DF.
It is connected to the input terminals of F8 and DFF9. The D-type flip-flops DFF8 and DFF9 each receive a signal W.
It is configured to take in the supplied data when TD and WTP rise, and output the taken data as signals DSTi and PTNi.

The signal DSTi is supplied to the first bit input terminal of the selector 30 and the 0th bit select terminal of the selector 14, and the signal P T N i is supplied to the 0th bit input terminal of the selector 30 and the second bit input terminal of the selector 14. ing. The selector 30 selects the first . This selects one of the second bits, and its output terminal Y
is connected to the data input end of the output data buffer 31. The output data buffer 31 is
When the output signal of the AND gate AN30 becomes "L", it enters the enable state and outputs the data supplied to the input end to the data bus IOi. AND GATE AN
30 is "l" when the signal RGA supplied from the command control circuit CC and the signal OE to V supplied from the timing control circuit TC both become "l".
Output a signal.

Furthermore, the output end of the buffer BFF2 is connected to the data input end of the output data buffer 12 and the buffer BFF5.
is connected to the input end of the The output data buffer 12 receives a signal O supplied from an AND gate AN25.
When Ei is "1", data supplied to the input terminal is output to the data input/output terminal Tl0i. B
FF6 is a buffer whose input end is grounded, and this buffer BFF6 and buffer BFF5 are connected to each other when the signal 0EPi supplied from the AND gate AN26 is "L".
It is enabled only when , and supplies each output signal D Oi, -OE Pi to the pixel interface PXI-0. Output data buffer 12.31 and buffer BF in the above configuration
Each F5.6 is configured such that its output is an open drain output.

, AN 27 and AN 28 are the signals M KA , B M i , RP M P , respectively.
, the signal RWX and the signal RP based on PAM
The AND gate AN26 is a gate for creating the signal 0EPi, and the AND gate AN26 performs the logical product of the signal RPX and the signal OEW to create the signal 0EPi.

Further, the OR gate 0RIO is a gate that takes the logical sum of the signal RWX and the signal NC8, and the AND gate AN25 takes the logical product of the output of the OR gate Or'tlO and the signal OEW to generate the signal OEi.

In addition, each bit interface BTIO-BT I
D type flip-flop DFF7 in T is 81m11
Similarly, 8 sets of D-type flip-flops DFF8 form a destination register, 891 sets of D-type flip-flops DPF9 form a pattern register, and 891 sets of D-type flip-flops DPF9 form a pattern register. Eight LFFs 6 form a set I, each forming a bit mask register. That is, each memory device #OM to #3M has a source register, a destination register, a pattern register, and a bit mask register.

[Vixel Interface] FIG. 7 is a block diagram showing the configuration of the pixel interface PXI-0. In this figure, 'rIop
-o is a pixel data input/output terminal, and the data input from this pixel data input/output terminal Tl0p-0 becomes data DIF via the buffer BFF 10.
After this, L type flip-flop LFF10, D type flip-flop DFF 11, DFF! BT1.2 and the aforementioned bit interfaces BT1. -It is supplied to the first bit input terminal of each selector 10 and selector 13 in BTIt (see FIG. 6). L type flip flop Ll
"F l O is the timing control circuit TC (
When the signal RASW supplied from the D-type flip-flops DFF1 and DFF+
2 takes in the data being supplied to the input terminal when the signals WPW and RP~■ supplied from the command control circuit CC respectively rise. It's happening. L type flip-flop LFFlo,D
Each output signal FCS, FWP, FRP of type flip-flop DFF+1.12 is selected from selector+5.16.
．． 17, and this selector l
A positive voltage is applied to the 0th bit input terminals of 5, 16, and 17 via pull-up resistors, respectively. Selector 15
selects the 0th bit input terminal when the signal BCE supplied from the command control circuit CC is "0",
When the signal BCE is "1", the 0th bit input terminal is selected. In addition, the selectors 16 and 17 each receive a signal PME supplied from the command control circuit CC.
When the signal PME is "0", the 0th bit input terminal is selected, and when the signal PME is "I", the 1st bit input terminal is selected.In this case, are the selectors 16 and 17 actually one selector? , here, for convenience of explanation, they are shown as two cell nocturners.

18 is a pixel output data buffer configured to be an open drain output;
When the "l" signal is supplied to the enable terminal E, the signal supplied to the data terminal is outputted to the pixel data input/output terminal Tl0p-0. In this case, a positive voltage is applied to the data terminal via the pull-up resistor, and the bit interface BT
Data DOo-Do is supplied from I7. Further, the enable terminal E of the pixel output data buffer 18 receives signals -0EPo to -0 from the bit interfaces BTIO to BTI.
E.P.

A positive voltage is applied to the input terminal of the inverter INV5 via a pull-up resistor.

The above is the configuration of each part of the circuit in this embodiment.

@Operation in the evening of implementation Next, the operation of this embodiment with the above configuration will be explained.

(1) Operation of mask mode ■ Setting of mask mode First, as mentioned above, this embodiment has 2N operation modes of normal mode and mask mode in the memory read/write cycle. Since the logical operation processing that is the operation is performed in the mask mode, only the mask mode will be explained below.

In the mask mode, it is possible to mask each bit or each memory device in data writing or data succession. To set this mask mode, when the row address strobe signal RAS rises at time t1 shown in FIG. 9, the column address strobe signal CAS and the output enable signal OE are at the "0" level. , furthermore, the write enable signal W is set to "l" as shown at point P3 in the same figure (d).
The condition is that you are at the same level.

That is, when the above-mentioned conditions are satisfied, the output signal MME of the AND gate A N 2 shown in FIG. Thereafter, the output signal MKA of the L type flip-flop LFF3 maintains the "L" level and enters the mask mode. Next, time t! When the column address strobe signal CAS rises, the column address is taken in at this point, and the address to be accessed is determined. And the light at this time
If the enable signal WE is at the "0" level, a read cycle begins to be executed, and then when the signal OE becomes the "L" level, at time 4, when a predetermined time has elapsed since the access address was determined, the read cycle is executed. The data of the corresponding address is output.

Furthermore, when the write enable signal WE goes to "L" level when the access address is determined, data is written to the corresponding address in the memory (time t in FIG. 10).
41).

Here, FIG. 11 shows the mask state when reading in the word direction. In this figure, the signals RP MP in the memory devices #OM and #3M are "0", and the memory device; M, #2 Signal RP in M
P becomes “l-”, and the signal B M ? ~ B Mo (
The case where the contents of the mask register) is (oozzoo) is shown. When the signals BM0 to BM and the signals RP-MP reach the values shown in FIG. 11, the common data bus f Oo'
= The 7th, 6th, 1st, and 0th bits of IO7 are high.
It becomes an impedance shape @ (r-J symbol in the figure), and the fifth
, the fourth, third, and second bits have a value of (0100).

That is, only the data of the memory device whose signal RP M P is "1" and the data of the bit whose signal 13 M i is "1" is in the output permission state,
Furthermore, if there is a conflict between the output data, the "0" signal takes priority. FIG. 12 shows the mask state when data is read in the pixel direction. In this case, the data is from the memory device where the signal RPMP is "1" and the signal B
Only the bits whose Mr is "l" are enabled for output, and the corresponding bits in each memory device are output to the input terminals 'rop-o to Tl0p-3, respectively.

At this time, if there is a data conflict within the same memory device, the "0" signal is given priority and output as in the above case.

On the other hand, in the write cycle, bit-by-bit masking is performed by the signal B M i in the same manner as described above, and memory device-by-bit masking is performed by the signal WPMP (masked with "0") as shown in FIG. 7. If the same bit number is enabled for writing in the word direction, the same data is written to these bits, and in the case of data writing in the pixel direction, the memory to which writing is enabled is enabled. The same data is written to the unmasked bits of the device (see FIGS. 13 and 14).

■Writing to bit mask register BMR Next, write processing of bit mask register BMR and signal B
The functions of M i on the circuit will be explained.

At time 1+ shown in FIG. 9(f) (or time L4° shown in FIG. 10), the mask data (8 pits) are transferred to memory device
Supply to M~#3M. This mask data is data in which the bits to be masked are set to "0" and the bits not to be masked are set to "1", as described above. Then, one bit of the mask data is transferred to the data bus I shown in FIG.
Oi is supplied to the input terminal of the L-type flip-flop LFF6 via the buffer BPF1 (common to each memory device).

And the L type flip-flop LFF 6 is connected to the signal R
At the rising edge of A SW (at the same timing as the rising edge of RAS), the mask data supplied to the input terminal is taken in and supplied to the first bit of the selector 11 as a signal P B M i. Writing to this L-type flip-flop LPF6 is performed simultaneously in each memory, so that the mask register B? Writing to l/I R is completed. As can be seen from the above, writing to the mask register BMR can be performed every read cycle or every write cycle.

Next, the function of the signal B M i on the circuit in the read cycle will be explained. First, as shown in FIG. 6, the output signal F B of the L type flip-flop LFP6
M i is output as the signal BMi if the signal BCE is "bi", and if the signal BCE is "0", the signal BMi is always a "1" signal. That is, the signal BC
If E is not "l", the signal F corresponding to the mask data
B M i becomes invalid. And the signal B M i
are supplied to each input terminal of AND gates AN27 and AN28 to output data buffer 12 and buffer BPF5 . Signal O, which is the enable signal of BFF6
Contributes to turning on/off Ei and 0EPi. In this case, as is clear from FIG. 3, the signal NCS is not output in the mask mode.

Then, when the output data buffer 12 is enabled, the data read from the memory Mi (see FIG. 1) is outputted to the data bus IOi by sequentially operating the buffer BFF2 and the output data buffer 12. . Also, buffer BFF5. When BFF6 is enabled, the data read from memory M i is transferred to the pixel output data buffer 1 shown in FIG. 7 via buffer BFF2 and buffer BFF5.
8, the inverter INV
Since the output signal of 5 becomes "1" and the pixel output data buffer 18 is enabled, the data read from the memory M i is transferred via the pixel output data buffer 18. Input/output terminal Tl0p-0 (or Tl0p-1-TIOp-3
) is output. That is, the signal OEi determines permission/non-permission of word-direction data output, and the signal 0EPi determines permission/non-permission of pixel-direction data output, and the values of these signals are controlled by the signal B M i. .

The above is the function of the signal B M i in the read cycle.

Next, the function of the signal B M i in the write cycle will be explained. In the write cycle, the signal BM
, ~B M , are supplied to one input end of the AND gate ANIO~AN17 in the timing control TC shown in FIG. 3, thereby causing the memory M. - Write enable signal 'vV E to M7.

~WE? control. That is, the signal BMI is “1”.
``If not, the write enable signal for the corresponding memory will not rise, and the memory of the relevant bit will be masked.

Also, as you can see from the above, for the bit mask to be effective in both read and write modes,
Signal BCE must be set to "l". Here, the process of setting the value of the signal BCE will be explained. The value of this signal BCE is determined by the command “
This is a signal that becomes "1" when "bit/chip select mask enable" is supplied, and writing of a command in this case is performed as follows.

First, as shown in FIG. 15, at time tlo, the row address strobe signal RAS rises. If the column address strobe signal CAS and the write enable signal WE are at "L" level at this point, the command write cycle is started. selected. That is,
Column address strobe signal CAS and write
When the enable signals W and E are both "1", the signal M CE which is the output signal of the AND gate AN3 shown in FIG.
becomes "L", and this "I" signal is taken into the L-type flip-flop LFF4 at the rise of the row address strobe signal RAS. Therefore, after time t1°, the L type flip-flop L
The output signal MCC of FP4 becomes "L", and the command write cycle is confirmed. As a result, and gate A
The output signal MCD of N9 becomes "1" while both the row address strobe signal RAS and the signal RASD are "1". That is, the signal NlCD rises slightly later than the rise timing of the row address strobe signal RAS.

On the other hand, a "bit/chip select mask enable" command is supplied to the command register l shown in FIG. 4 via address buses AO to A7, and this command is taken in at the rise of the row address strobe signal RAS. The command “Bit/Chip Select Mask Enable” is expressed in hexadecimal as (0) as shown in Table 1.
7), so the command register l
The outputs of MCO to MC2 are "L" signals, and the other outputs are "0" signals, and the "L" signals are supplied to the 0th and 1st bit input terminals of the decoding circuit 3. As a result, the decoding circuit 3 becomes in a state where it can set the signal BCE corresponding to the decoding result "3" of the input signal to "1", and sets the signal BCE to "1" at the timing when the signal MDS supplied to the clock terminal rises. do. And the signal MDS
rises slightly later than the row address strobe signal RAS, so the signal BCE rises at time t shown in FIG.
The signal becomes "L" at a timing slightly delayed from 1°.

The above is the process until the signal BCE becomes "1".

■Signal RP M P settings Next, the setting operation of the signal RP MP will be explained.

To set the value of the signal RPMP, the command "read plane mask" shown in Table 1 is executed, and during this execution mask data is supplied from the input/output terminals rtop-o to 'rIop-3. Execution of the command "read plane mask" is performed as follows. First, Figure 16 (a)
As shown in , at time t30 when the row address strobe signal RAS rises, the column address strobe signal CAS and the write enable signal W E
If is "1", a command write cycle is set. The operation up to this point is similar to the case shown in FIG. 15 described above. However, the value written to the command register 1 (FIG. 4) at time t30 is (10) in hexadecimal as shown in Table 1. As a result, among the outputs of the command register I, only the MC4 becomes an "l" signal, and a "1" signal is supplied to the 0th bit input terminal of the main command decoder 4. The main command decoder 4 receives the signal MCS T supplied to the enable terminal.
When RGA rises, it decodes the input signal and outputs the signal RGA from the first output terminal. In this case, the value of signal MC5T is determined by the AND of signal MCD and signal CS'VIP. In the command write cycle, the signal ~ICD becomes "L" at the rising edge of the signal RASD (Figure 3) and remains at the "L" level thereafter, and the signal CSMP (see Figure 7) If the signal BCE mentioned above is “0”, it is always “l”, and the signal BC
If E is "l", it is a signal whose value corresponds to chip select data. Therefore, writing of the command "read plane mask" is performed at the rising edge of the signal RAS under the conditions that the signal BCE is "1" and the chip select data is "1", or the signal BCE is "0". The main command is not written under conditions other than the above.

As mentioned above, the time is . , the command [read plane mask] is written to the command register l. However, at this time t30, the first
In Figure 6 (A), the signal RASD is “0” as shown by the dashed line.
” signal, the signal MCD does not become a “1” signal (
(see FIG. 3), as a result, the signal MC5T shown in FIG. 4 does not become an "L" signal.

Therefore, main command decoder 4 is not enabled. Next, at time L31, the row address strobe signal RAS, the signal RASD, and the column address strobe signal CAS.

The signals ~VE both become "l" signals, and as a result, the main command decoder 4 becomes enabled and sets the signal RGA to "l". Moreover, at time t31,
The signal W E W becomes "1" (third examination, light), and as a result, the decoder 2 becomes enabled.

At this time, since the command data MC0 to MC2 supplied to the input terminal of the decoder 2 are "0" signals, the decoder 2 sets the signal RPW to "1" at the timing when the decoder 2 becomes enabled. Since this signal RPW is supplied to the clock terminal of the D-type flip-flop DFF12 shown in FIG. 7, at this point, the D-type flip-flop DFF12 takes in the data supplied to its input.

On the other hand, mask data for each memory device (hereinafter referred to as read plane mask data) is obtained at time t3 shown in FIG.
1, the mask data is supplied from the input/output terminals Tl0p-0 to 'rtop-g, and this mask data is sent to the D-type flip-flop DF via the buffer BFFlO shown in FIG.
It is supplied to the input end of F12. As a result, the read plane mask data is taken into the D-type flip-flop DFF12 at time t31, and matches the value of the output signal F'RP of the D-type flip-flop DFF12 or the value of the read plane mask data. Since the signal FRP is supplied to the first bit input terminal of the selector 17, if the signal PME is "1", the signal RPMP
The value of matches the value of the read plane mask data. This signal RPMP is applied to the AND gate AN27 shown in FIG.
．． The above-mentioned signal 0EPi is supplied to the input terminal of AN28.
and contributes to turning on/off the signal OEi.

In addition, the signal PME becomes “1” when the command “plane mask enable” (see Table 1) is executed.
This is the signal. Writing this command “plane mask enable” is similar to the case of the command “bit/chip select mask enable” described above.
This is done at the timing shown in Figure 5. As can be seen from the above, there are two types of commands in this embodiment: commands that write data to a predetermined flip-flop in the memory device, and commands that do not involve writing data. The timing shown in Figure 16 is the one that does not involve data writing.
Each is written according to the timing shown in the figure.

■Signal W P~f f) setting signal\V? Setting of MP is performed by executing the command "Light Plane Mask". This command "write brain mask" is a command that is executed in the same manner as the above command "read plane mask", and is executed at the timing shown in FIG. 16.

Then, in the command "Read Plane Mask", the signal RP'IV became an "I" signal and mask data was written into the D-type flip-flop DFF12, but in this "Write Brain Mask", the signal R
Instead of PW, the signal WP'iV becomes the "l" signal,
As a result, mask data is written to the D-type flip-flop DFFII. Other operations are the same as the command “read brain mask j.

(n) Logical operation processing ■Outline of logical operation processing First, an overview of logical operation processing will be explained.

The source register mentioned above (i.e. DFP7) has
Data supplied during the write cycle is stored, and data is written to the destination register (DFF8) and pattern register (DFF9) by predetermined commands at the beginning of each logical operation. Various logical operations are performed between the registers, and the results of these logical operations are written into memory. In this case, no matter what the logical formula is, the logical operation result R can be expressed as a sum of eight terms as shown in the following formula.

R=b7PSD+b,PSI)+bSPSD+b,PS
I)+bsP S D +b2P S D +b+P
S D +boP S D... (1) In the above formula (1), P, S, and D indicate the contents of the pattern register, source register, and destination register, respectively, and the ones with - are It shows the inverted value of the contents of each register.

The coefficients s, ~b0 in equation (1) are coefficients that are set to "l" or "0° depending on the content of the logical operation, and the terms for which "0" is set as the coefficient value are the coefficients in equation (1). Here, FIG. 8 shows the above-mentioned coefficient b7.
This is a diagram for showing the meaning of the term corresponding to ~b0, and the circle P
, S, and D correspond to the pattern register, source register, and destination register. Each numbered area indicates a term with the same coefficient number; for example, area 1 indicates the term PSD corresponding to coefficient b1, and area 7 indicates the term PSD. Next, as an example of calculation processing using equation (1), PS (corresponding to area 6.7) and P
The case of adding D (area 1.3) will be explained. As can be easily seen from the figure, the result of this calculation should be the shaded area (area 1, 3.6.7). First, P
Transforming D+PD, PS+FD=PS(D+D)+P(S+1)D=P
S D + P S D + P S D + P S
D...(2) becomes. Then, the transformation result according to equation (2) and equation (1)
Comparing each term in the equation, the equation (2) has the coefficient (b7.be, bs, b, , b3.b2.bl) in the equation (1).
, bo) is (1°1.0.0.l, 0,1.0). That is, it is sufficient to set coefficients that make only the four terms that are the calculation results of equation (2) valid and make the other terms invalid. The first term of the calculation result of equation (2) corresponds to area 7 shown in FIG. 8, and the second, third, and fourth terms correspond to area 6, area 3, and area l, respectively. do. Therefore, the sum of these areas is the area shown with diagonal lines in FIG. 8, and it can be seen that equation (2) is correct. Similarly to the above case, all other operations are performed using coefficients (b7, be, bs, b-, b3 .
By appropriately setting the values of bz, bl, bo), it can be expressed using equation (1).

Then, the coefficients (b,,b,,bs,b,,b3.b,,
b,,b,) are the selector 14 shown in FIG. 6 on the circuit.
The signal no supplied to the 0th bit to 7th bit input terminal of
c.

.about.ROC7 (the setting of this signal value will be described later), and the above logical operation is performed by the select operation of the selector 4. That is, the D type flip-flop DFF8 that constitutes the destination register
, the output of the D-type flip-flop DFF7 constituting the source register, and the output of the D-type flip-flop DFF9 constituting the pattern register are supplied to the Oth bit, the first bit, and the second bit of the selector 14, respectively. Therefore, when the output of each of these D-type flip-flops is "l", each of them becomes S.

P, and if each output is "0", then each;

If p, the signal supplied to the select input terminal of the selector 14 will be a signal corresponding to one of the terms shown in equation (1). Furthermore, if the signal ROX is "L", the signals ROCO to ROC7 are selected by the above-mentioned 3-bit signal supplied to the select input terminal. and its coefficient will match. Therefore, the operation of the selector 14 is substantially the same as the calculation shown in equation (1), and the values of the signals ROCO to ROC7 corresponding to the 7th signal supplied to the 0th to 2nd bit select input terminals are If is set to "l", a "1" signal is output from the output terminal Y,
If "0" is set, a "0" signal is output from the output terminal Y.

The above is an outline of the logical operation processing in this embodiment.

■Writing data to each register Next, the operation of writing data to each register described above will be explained.

(a) Writing to the source register Writing to the source register is performed by normal write processing if a write cycle is set.

That is, the D type flip-flop DF shown in FIG.
F7 is the selector 10 when the signal W E W becomes “L”.
Since the output signal of is captured, the signal RAS'v
Writing to the source register is completed at the timing 1) when V and the write enable signal WE (see FIG. 3) both become "L".

Then, if the signal PAM is "1" and the signal HMA is "0", the data written at this time is written on the data bus rOp.
-0 (or [0p-1 to 3)], and in other cases, data bus I
This is data in the word direction supplied from Oi.

Furthermore, if the signal ROX is "0", the data written in the D-type flip-flop DFF7 is supplied to the memory M1 via the selector I4 and the buffer BFF3 in sequence.

(b) Writing to the pattern register and destination register Data writing to the pattern register and destination register is performed by the following three types of processing.

First, the data bus l0p-0 (or 101)-
Command to write 1-bit data in the pixel direction supplied from 1 to 10p-3) to all bits of the pattern register or destination register at once [
This is the execution of a ``plane pattern register'' or ``brain destination register''.

Second, the data bus 100-10. This is the execution of the command ``pattern register'' or ``destination register'' to write 8-pit data in the word direction supplied from the 8-bit data into the pattern register or destination register in bit correspondence.

The third step is to execute a command [pattern load enable] or "destination load enable" that reads data from memory blocks MBO-MB3 and writes the read data to the pattern register or destination register in bit correspondence. .

Next, each command will be explained for each type of write processing.

(1) Commands "Plane Pattern Register" and "Plane Destination Register" The command "Plane Pattern Register J" is executed at the timing shown in FIG. 16. That is, at the time shown in FIG. 16, the command code ( 13) is supplied from address buses AO to A7.

This command code (13) is latched into the command register l and output as command data MCO to MC7. As a result, data "3" is supplied from the command register 1 to the input terminal of the decoder 2, and the main command decoder 1 changes the signal RGA to the "1" signal. Next, a little bit at time 131 shown in FIG. 16: 'I'
4, “ to write from data bus 1op-〇
This data is supplied to the first bit of the selector 13 shown in FIG. 6 after passing through the buffer BFF l O shown in FIG. 7. Then, at time t3 , the signal WE rises as shown in FIG. 16, and as a result, the signal WE shown in FIG.
W stands up. When the signal WEW rises, the decoder 2 becomes enabled and the signal WTP becomes "1".
Stand up at the traffic light. When the signal WTP rises to the "L" signal, the D type flip-flop DFF9 forming the pattern register takes in the output data of the selector 13. At this time, the selector 13 determines that the signal MCW is “
0" and the signal MCC is "L", so the first bit input terminal is selected. As a result, the data that was being supplied from the data bus Iop-o to the first bit input terminal of the selector 13 is At t31, D via the selector 13
It is taken into type flip-flop DFF9. At this point, writing to the pattern register is completed.

Next, the command "plane destination register" will be explained. Similar to the above command, this command is also executed at the timing shown in FIG. 16, resulting in almost the same processing as above. That is, when a command code (I4) is supplied from the address buses AO to A7 at time t3° and predetermined data is supplied from the data bus 10p-0 at time t3+, the decoder 2 shown in FIG. VTD is set to the "1" signal, and as a result, the above data is taken into the D-type flip-flop DFF8 via the selector 13. This results in
Writing to the destination register is completed.

(11) Commands "Pattern Register" and "Destination Register" The command "Pattern Register" is executed at the timing shown in FIG. 16 similarly to the upper S command. First, a little before time t30, command code (16) is supplied from address buses AO to A7.

As a result, the command register l shown in FIG.
At time L3° when S rises, the above command code is latched and output as command data MC0 to MC7. As a result, the data "6" is supplied to the input terminal of the decoder 2, and the main command decoder 4
A signal RGA is output from. Next, data to be written is supplied to the data bus (2) 0° to 107 from a little before time t31.

This data is supplied to the 0th bit input terminal of selector I3 via buffer BFFI in bit interface BTIi. Then, at time t31, when the write enable signal WE and the signal WEW rise, the decoder 2 changes the signal MCW to an "L" signal, and
Let the signal WTP be an "l" signal. As a result, the D type flip-flop DFF 9 shown in FIG.
capture the output signal of At this time, the selector 13 has signals MCW and MCC both at "l", so
The 0th bit input terminal is selected, so that the data supplied to the data bus 10i is taken into the D type flip-flop DFF9.

This operation applies to each bit interface BT I.

.about.BTI, the data writing for each bit to the pattern register is completed at this point. Further, this writing is also performed simultaneously in other memory devices. However, in a memory device in which the signal C3MP (the output signal of the selector 15 shown in FIG. 7) is a "0" signal, the signal MC8T shown in FIG.
Since the main command decoder 4 is not enabled, writing to the pattern register is not performed.

Next, the command "destination register" will be explained. This command is a command that performs the same process as the above-mentioned "pattern register" (command code is (17)), except that the write target is the D-type flip-flop DFF8. In other words, in the command "Destiny no Yon Reno Star"
At time t31 shown in FIG. 6, when the signal W E rises, the decoder 2 shown in FIG.
” signal, which causes the D type flip-flop D
Data supplied from the data bus IOi is written into the FF 8 via the selector 13.

Further, in executing the commands "pattern register" and "destination register", the contents of the pattern register and destination register can also be read. In this case, time t in FIG.
31, the write enable signal WE is set to a "0" signal as shown by the broken line, and the signal OE is raised to set the signals OE to V to "1" signals. In this way,
The AND gate AN30 shown in FIG. 6 outputs the "L" signal and the output data buffer 31 is enabled, and the data in either the destination register DFF8 or the pattern register DFF9 is sent to the selector 30 and the output data buffer 31. The signals are sequentially output to the data bus IOi. In this case, if the signal MCO supplied from the command control circuit CC is "L", the selector 30 selects the D-type flip-flop DFF8, and if the signal MCO is "O", the selector 30 selects the D-type flip-flop DFF8. Flossop DFF 9 is to be selected.

This allows the command [destination register]
When the command ``pattern register j'' is executed, the selector 30 selects the D-type flip-flop C knob DFF8, and when the command ``pattern register j'' is executed, the selector 30 selects the D-type flip-flop DFP9.

(iii) Command “pattern load enable”, [
Destination Load Enable" The command "Pattern Load Enable" is performed as described below. That is, when a command code is supplied in which the upper bit is expressed in binary (0011) and the lower first bit is "l" (other bits are don't care), the register 7 shown in FIG.
An "L" level signal ~ICI is supplied to the input terminal of the main command decoder 4, and the main command decoder 4 sets the signal r (LC to
” signal to enable the register 7. As a result, the signal PLE becomes the “l” signal, and the AND/KATE A
One input terminal of N36 becomes "L" level. here,
If the output signal of the AND gate AN38 is a "1" signal, the AND gate AN36 outputs a "1" signal, and as a result, the signal WTP rises to a "1" signal.

When the signal WTP rises to the "l" signal, the D-type flip-flop DFF9 shown in FIG. C.A.S.W.S.O.
E E and M K A are all “L” signals, but the value of signal B M i is determined when setting the value of the mask reno star, and signal CA SW is the column address signal.
When the strobe signal CAS rises, it becomes "L",
The signal MKA is a signal that is already an "L" signal when the mask mode is set.The signal OEE is a signal that becomes an "I" signal after a predetermined time delay after the output enable signal OE rises. In other words, the AND gate AN38 outputs the "L" signal after a predetermined period of time has passed since the output enable signal OE rises.Therefore, after n after executing the above command, the lead shown in FIG. When the cycle is executed, the signal OEE becomes the 'l' signal after a predetermined period of time has elapsed from time t3 when the output enable signal OE rises, and as a result, the data read from the memory Mi is transferred to the signal O.
At the time when EE becomes “L” signal, buffer BF
F1, the selector 13 is sequentially activated, and the signal is taken into the D type flip-flop DFF9. That is, in a read cycle, data is read from the memory and at the same time, the read data is written to the pattern register. In this way, the reason why the rising timing of the signal OEE is delayed from the rising timing of the output enable signal OE is because the timing at which data is completely read from the memory M i (data is finalized) is delayed. This is for writing to the pattern register.

Here, FIG. 17 shows an example of execution of the command "pattern load enable". As shown in this figure, for read control from memory, signals RP't, ・I
P and B M i perform masking functions, and for writing to the pattern register, signals P L E and B M
i like the mask function. Note that the symbol "." shown in the figure indicates a bit that is not written.

Further, the command "destination load enable j" is executed in the same manner as the above command "pattern load enable". That is, when a command code is supplied in which the upper bit is expressed in binary (0011) and the lower second bit is "l" (other bits are don't care), the register 7 shown in FIG. A signal MC2 of "L" level is supplied to the input terminal of the main command decoder 4, and the main command decoder 4 sets the signal RLC to "L".
The register 7 is enabled as a signal. As a result, the signal DLE rises to the "l" signal, and the signal WTD
is a “1” signal. Therefore, the D type flip-flop DFF9 constituting the destination register
takes in the output data of selector I3. As you can see from the above, the mask processing in this command is as follows:
It is the same as the command "pattern load enable" (
(See Figure 17).

Also, as a command code, the upper 4 bits are expressed in binary (0011), and the lower 1st and 2nd bits are both “1”.
(other bits are don't care), the commands "pattern load enable" and "destination load enable" are executed simultaneously.

(2) Coefficient setting process of logical operation Next, the setting process of coefficients b7 to bo shown in equation (1) will be explained. This coefficient setting is performed using the command “Raster Operation Code (LOW)” for the lower 4 bits.
) The upper 4 bits are processed by executing the command "raster operation code (HIGH) J." These commands will be explained below.

First, start with the command “Raster operation code (LOW
)'' is a command code in which the upper 4 bits are expressed in binary (0011) and the lower 4 bits are coefficients b3 .
The values correspond to the values of b, , b, , b (see Table 1). When this command code is supplied to the address buses AO to A7 at time tlo shown in FIG. 15, the command register 1 latches it and outputs it as command data NiC0 to MC7. As a result, the coefficient b3. Signal corresponding to the value of b, , b, , b: 'vlc3. Mc2゜MC1,N, ICO are supplied, and the main command decoder 4 receives the signal R.
Let OL be the "l" signal.

As a result, register 8 is enabled and coefficient b
3. b,,b,,bonofa+,: corresponding signal ROC
3, ROC2, ROC1, and ROCO are output. And the cono signal ROC3, ROC2, 110C1, ROC
0 are supplied to the third to zeroth bit input terminals of the selector 14 shown in FIG. 6, thereby causing the coefficients b3. The settings for bz and b1°bo are completed.

Next, use the command “Rask Obereyon Code (I (I
When executing GH)J, the upper 4 bits of the command code are set to (0101), and the lower 4 bits are used as a coefficient. b6. b3. Let the value correspond to b.

Then, when this command code is supplied to the command register l at the timing shown in FIG.
, b4 corresponding command code NIC3.

MC2,? vlC1 and MCO are supplied, and the main command decoder 4 sets the signal ROU to the "l" signal. As a result, register 9 is enabled, and coefficients bt, bs, b5 . Signal R07 corresponding to b4(7) value
, RO6, RO5, and RO4 are output. This output R0
7, RO6, RO5, and RO4 are supplied to the seventh to fourth bit input terminals of the selector 14 shown in FIG. 6, so that the coefficients b7. b6. The settings for b, , b, are completed.

As mentioned above, the coefficients are To set -b7, execute both the commands “raster operation code (t, oW) j” and “raster operation code (HI G H) J”.

(2) Execution of logical operations Next, the execution of logical operations based on the contents of the butter register, destination register, source register, and coefficients b7 to bbo set as described above will be explained.

When executing a logical operation, execute the command "raster operation enable" shown in Table 1.

That is, at time tlo shown in FIG. 15, a command code (OF) is supplied to the address bus AO-A7. As a result, the command register l shown in FIG. 4 supplies command data MC3, MC2, MCI, and MCO whose value is "l" to the decoding circuit 3, and also outputs the output signal of the AND gate AN2+. MDS becomes the "l" signal and the decoding circuit 3 becomes enabled, and thereby the decoding circuit 3 outputs the signal ROE as the "l" signal. On the other hand, in the mask mode, the signal MKA becomes "l".
Therefore, when the signal R'OE becomes an "l" signal, the signal ROX, which is the output signal of the AND gate AN35, becomes a "1" signal. When this signal ROX becomes a "1" signal, The third bit select terminal of the selector 14 shown in FIG.
When becomes the "L" signal, the data supplied to the Oth to third bit select terminals will not exceed 8 in decimal notation. Therefore, the D type flip-flop DFF
7 (source register output signal 5RCi is selected by selector 1)
4 to the memory Mi, and the output signals of the D-type flip-flops DPF7, DFF8, and DFF9 all function as select signals. And each D type flip-flop DFF7, DFF8,
When the output signal of DFF 9 is "l", the S term, D term, and P term of equation (1) are used, and when each output signal is "0", the equation 9 of equation (1) is used. term, D term, and p term, the selection operation of the selector 14 corresponds to the calculation shown in equation (1).

In this case, writing to the D-type flip-flop DFF7, which is the source register, is performed by a write cycle in a normal memory cycle (see section 101D, b), so the contents of the source register are written sequentially in each memory cycle. There are three things you can do to change it.

In addition, in the above-described embodiment, logical operations between destination data, pattern data, and source data can be easily and efficiently performed. The advantage is that high-speed processing such as the following can be realized. Furthermore, even when there are many color codes to be calculated and many types of calculations, there is an advantage that the processing for specifying the calculations is simple.

Furthermore, in the above embodiment, an example of instantaneous rewriting of the destination register and pattern register was shown, but with a similar configuration, it is also possible to perform high-speed rewriting processing of registers that store data for comparison detection, etc. .

Further, in the above embodiment, parameters are written in each memory device in the pixel direction using individual input/output data paths top-o to Iop-3;
In the word direction, 1. This is performed by an input/output data path (2) 0° to 107 common to each memory device. In this case, the word-oriented data bus 10. ~10. are commonly connected, but when writing parameters, individual parameters are set for each memory device by masking each memory device using the signal CSMP (or signals P-LE, DLE). It is now possible.

Further, in the above embodiment, the row address strobe signal RA
Although command cycles are formed by combinations of levels such as S, other combinations are possible, and a control line for special function instructions may be separately provided and a command cycle may be specified from this control line.

Furthermore, the connection relationships among the bit interface, pixel interface, timing command control circuit, and memory section and the assignment of various functions are not limited to those shown in the above embodiments, and various modifications are possible.

For example, as shown in FIG. 19, memory blocks 70 to 73 having a memory interface MI and memory block interfaces 75 to 78 are provided, and the memory interface MI is provided with a write bit mask function. ~78 may be made to have one ton of each type of machine.

Furthermore, if the memory capacity is large, a configuration as shown in No. 201A may be used. In this figure, 80.81
Each memory block is a 4 bit x 64 K x 4 brain (4 planes), and each memory block 80, 81 is provided with a memory interface LiI. In this case, each memory interface ~1■ is configured to exchange data in units of 4 bits with the memory block interface N1BI. The memory block interface MBI is configured to send and receive data to and from an external circuit in units of 8 bits in the word direction and in units of 1 hit in the -pixel direction.

In the example shown in FIG. 20, memory interface M
The functions required for I are a word direction/pixel direction switching function, a read/write bit mask function, a write plane mask function, and a read plane mask function.

As a result, when the input/output data of the memory interface M+ is switched to the word direction:
Switch in the pixel direction. This will result in pixel data for each surface. Additionally, during read/write cycles, bit masking and brain masking can be performed for each surface.

Next, the functions required for the memory block interface are pattern registers (for 4 planes), destination registers (for 4 planes), logical operation function, word direction/pixel direction switching function, read bit mask, and read plane mask. be.

The reason why four pattern registers and four destination registers are required is to allow calculations to be performed using arbitrary data for each surface. In this case, since logical operations are performed one by one, only one logical operation circuit is required. First, when switching to the word direction, the 4-bit data input/output by each memory interface MI becomes 8 bits in total, and this 8-bit data is input/output as word data according to the read plane mask. do. On the other hand, when switched in the pixel direction, each memory interface Ml inputs and outputs the pixel data of each heavy color that corresponds to the same surface by ANDing them according to the lead pit mask.

"Effects of the Invention" As described above, according to the present invention, in a memory device that is composed of a plurality of memory sections having a common address bus, and in which each memory section has a special function, Each memory section is configured to commonly take in the machine 11 episode designation code from the address bus and the parameters from the data bus, so although the structure is simple, special functions can be shared in each memory section. , Ka,
Parameters can be given individually, and this has the advantage of speeding up the processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the connection state of memory devices,
3 is a block diagram showing the configuration of the timing control circuit TC, FIG. 1 is a block diagram showing the configuration of the command control circuit CC, FIG. 5 is a block diagram showing the configuration of the memory block, and FIG. 6 is a block diagram showing the configuration of the command control circuit CC. FIG. 7 is a block diagram showing the configuration of the bit interface, FIG. 7 is a block diagram showing the configuration of the pixel interface, FIG. 8 is a diagram showing the arithmetic processing in the same embodiment, FIG. 9 is a timing chart of control signals in the read cycle, Figure 1O is a timing chart of control signals in a write cycle, Figures 11 and 12 are diagrams each showing the relationship between the mask state and output data in a read cycle, and Figures 13 and 14 are diagrams each showing the mask state in a write cycle. Figures 15 and 16 show the relationship between and human data.
17 is a diagram showing an execution example of the command "pattern read enable", FIG. 18 is a schematic diagram showing the relationship between the frame memory and the display surface, and FIG. Figure 19 and 2nd
FIG. 0 is a block diagram showing other examples of connections between the memory section and various interface functions in the present invention. 8.9...Register, 14...Selector,
TCC...Timing command control, MBO~MB3...Memory block, BTl
, ~BTl, ... bit interface, PXI
-0...Pixel interface, 10. −
10°...Person output data path (word direction data bus), 1Op-0 to I op-a...Input/output data path (pixel direction data bus), DFF7.
...D type flip-flop (source register,
register), DFF8...D type flip-flop (destination register: register), DF
F9...D type flip-flop (pattern register: register).

Claims (2)

[Claims] (1) In a memory device composed of a plurality of memory sections having a common address bus, each memory section having a special function, each memory section commonly receives a function designation code from the address bus, A memory device characterized in that the parameter is configured to be fetched from a data bus. (2) The memory device according to claim 1, further comprising masking means for masking parameters supplied via the data bus in units of memory units.