JPS6352246A - Memory device - Google Patents

Abstract

PURPOSE:To access to data for each bit by providing a means which performs a bit mask action in a mask mode where a memory part is masked. CONSTITUTION:Each of memory devices #0M-#3M of the same constitution consists of memories M0-M7, bit interfaces BTI1-7, a pixel interface PXI-0 and a timing command control TCC. The control TCC supplies the bit mask data to the mask registers in the interfaces BTI0-7 from data buses IO0-IO7 when the commands of mask modes are supplied from address buses A0-A7 by the control signals CSW, CAS and WE. The interfaces BTI0-7 input the data on the corresponding memories M0-M7 to the input registers in the interfaces and then output these data to the buses IO0-IO7 when the value of the bit mask data is equal to 1.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a memory device suitable for use in storing image data and program data in, for example, an image processing apparatus.

"Prior Art" The capacity of a frame buffer in which image data for image display is stored is proportional to the size and resolution of the display area, and also depends on the number of display screens (such as when multiple screens are made in advance). is also proportional. When displaying in color, the frame memory is expanded to correspond to the number of colors to be displayed.

For example, in the case of 16-color display, 4 bits are required as a color code, so four frame memories F-10-FM3 are required as shown in FIG. In this case, the direction of dashed line data (hereinafter referred to as pixel direction) at the same bit position of each frame memory FMO to FM3 corresponds to one dot on the display surface.

Then, when displaying an image, each frame memory F M
Data is read out sequentially into a sea of pixels O to F to 13 as the display surface is scanned, thereby making it possible to display multiple colors. In addition, in actuality, in response to higher image quality, dual port memories are provided in quadruple sub-rows as frame memories FMO to FM3, and pixel data is synchronized from the serial data output terminal of each side. A reading method is generally adopted.

[Problems to be Solved by the Invention] By the way, in the above-mentioned conventional memory device, color code reading when displaying an image can be performed satisfactorily, but it is difficult to access and rewrite each pixel data individually. Furthermore, when rewriting two or more desired bits within a certain pixel, the process becomes extremely complicated. That is, each frame memory FMO
~FM3 normally performs word direction reading in 8-bit units (see the dashed line in FIG. If you read out a part containing the same data in word units, you will have to extract two or more bits that you need, and the series of processing will be complicated and will require more processing time. The problem arose that it ended up happening.

Also, as mentioned above and here, the memory for images generally has a large capacity, but in this case, it is possible to use part of the storage area as a program area. 34-b is also advantageous in terms of memory usage efficiency and circuit mounting space. however,
This sort of memory usage has not been done at all in image memories using conventional memory devices because access processing becomes complicated and the memory cannot be easily used as a program area.

This invention was made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a memory device that can easily and quickly rewrite data on a pixel-by-pixel or bit-by-bit basis, and can also use a storage area as an image data area and a program area at high speed.

``Means for Solving the Problems'' Second, the present invention solves the above-mentioned problems.Secondly, the present invention has l or a plurality of memory sections provided in the plane direction, and selects any one of the memory sections. Normal mode selects a memory section based on select data that instructs, bit mask based on bit mask data that instructs masking of any bit, or plain mask data that instructs masking of any memory section. a mask mode for masking the memory section based on the above, and selecting either the normal mode or the mask mode according to the value of a predetermined memory control signal when the memory access start control signal becomes active. It is characterized by having means.

"Operation" Normal mode and mask mode are switched depending on the value of a predetermined memory control signal when the memory access start control signal becomes active.
Each mode can be switched instantly every memory cycle. Further, the bit mask data, plane mask data, and select data can also be rewritten every memory cycle.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Overall Configuration of Embodiment FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In this figure, M, -M.

are 1 bit x 64K (or 128K) memories, each of which is connected in parallel to form an 8 bit x 64K (or 128K) memory block ~IBO. BTIO to 13TI are memories M, respectively. -M7
and data bus 10. ~10? It is a bit interface that controls data exchange between PX and
I-0 is a pixel interface that exchanges data of any one bit in the pixel direction (hereinafter referred to as pixel data) with the data bus 10p-0, and also reads chip select data or plane mask data to be described later. It is a circuit. This pixel interface PXI-0 is a bit interface B
T1. - Memories M0 to M7 via any of BTI7
It is designed to exchange pixel data with either of the bit interfaces BT1 o""' B T I ? and a timing command control circuit TCC.

The timing command control circuit TCC receives address data supplied from the outside via address buses AO to A7, an output enable signal OE, a write enable signal 'vV E , a row address strobe signal RAS, and a column address signal RAS. This circuit controls access to memory block MBO and timing of each part of the circuit based on strobe signal CAS and the like. In addition, the timing command control circuit T
CC is the bit interface B T I o= I
3 T I? The memory M is set according to the value of bit mask data (described later) supplied from the memory M. - It controls the write enable signal of M7. Further, the timing command control circuit 'rcc decodes the command data supplied from the address buses AO to A7, and appropriately controls each part of the circuit based on the decoding result.

The above-described components constitute the memory device #OM. This embodiment consists of a total of four memory devices: memory device #OM and memory devices #IM to #3M having the same configuration. In this case, the memory blocks in each memory device #1M to #3M are M B 1
= M B 3 and pixel interface is PXI
-1-PXI-3 and the data buses connected to each pixel interface are expressed as l0p-1-10p-3 to distinguish them.

FIG. 2 shows the connection state of these memory devices #OM to #3M, and as shown in this figure, each memory device #OM
~#3M data bus 10. -■07 are commonly connected for each bit, and the data buses Iop-o to l0p-3 of each memory device xOM to #3M are each individually wired.

Configuration of each part of the embodiment Below, the configuration of each part of the circuit described above will be explained in more detail.

(I) Outline of Operation Mode for Understanding the Configuration First, the operation mode in this embodiment will be briefly explained in order to facilitate understanding of the configuration of each part of the circuit.

(a) Normal mode This mode is for any one of memory devices #OM to #3M.
This is a mode in which one is selected and data access is performed in units of eight pits for the selected memory device. Data in this mode is output via the data bus IOo=IO7. In other words, use the normal 8-bit parallel access mode for any one of the memory devices #OM to #3M.

Further, this mode is used when a predetermined area within memory blocks MBO to MBa is used as a program memory area.

(b) Mask mode This mask mode is a mode in which any one or more bits of human output data can be masked, and any one or more of memory devices #OM to #3M can be masked. be. This mode is further divided into word access mode and pixel access mode, and in word access mode, the data bus
Word direction data input/output is performed via IOv, and in pixel access mode, data bus l0p-
Data is input and output in the pixel direction via 0 to 1op-3.

That is, in the word access mode, data (-) in the word direction of memory blocks MBO to MB3 shown in FIG.
(see dot-dashed line), and if you want to perform a bit mask, do as follows. For example, if you want to access bits bs and b7 shown in FIG. 18, access memory block MBO in the word direction. (8 bits), of this 8-bit data, bits other than bs and b7 are masked to prohibit access, and b, , b7 are accessed.

In addition, the pixel access mode is, for example, a mode in which access is performed in the pixel direction (see broken line) of memory blocks MBO to MB, 3 shown in FIG. . For example, the first
When accessing the pb+ and pb2 bits shown in FIG. 8, pixel PCo is accessed, memory blocks MBO and MI33 are masked, and b1. I)
Access the b2 bit.

Note that in the mask mode, it is also possible not to mask any bit or any memory device.

The above is an overview of the operation modes in this embodiment.

(II) Composition of each part Next, the configuration of each part of the circuit shown in FIG. 1 will be explained.

Note that since the memory devices #OM to #3M all have the same configuration, the following configuration will be explained using the memory device #OM as an example.

[Timing command control circuit TCC] This timing command control circuit TCC is
As shown in Figure 1, the timing control circuit TC
and a command/control circuit CC, the configuration of each of which is shown in FIGS. 3 and 4.

In FIG. 3, Ta-Te are control signal input terminals, and terminal Ta has a row address strobe signal RA.
A chip select signal csw for specifying whether or not to select the memory device #OM is applied to the terminal Tb, a column address strobe signal CAS is applied to the terminal Tc, and a write enable signal WE is applied to the terminal Td. An output enable signal OE is supplied to each terminal Te. DL is the row address strobe signal R
This is a delay that delays AS to create the signal RASD, and ORI is a signal RA S that is the OR of the row address strobe signal RAS and the signal RASD to lengthen the pulse width of the row address strobe signal RA S.
It is an or gate that creates W. LFF1 is a launch type flip-flop (hereinafter referred to as L type flip-flop) that takes in the value of the chip select signal CSW at the rising edge of the signal RASW, and ANl detects that the normal mode is specified and outputs the normal mode enable signal N. An AND gate AN2 outputs a mask mode enable signal MME and an AND gate AN3 detects that a mask mode is specified and outputs a mask mode enable signal MME.
is an AND gate that detects that a command write cycle, which will be described later, is designated and outputs a command enable signal MCE. LFF2゜LFF3. LFF4 receives the enable signals NME, MME,
This is an L-type flip-flop that takes in the value of MCE at the rise of signal RASW, and outputs signals NMA and MKAJICC from its output terminal. Further, AN4 to AN9 are AND gates that create the illustrated signals based on the above-mentioned signals and control signals supplied from other circuits, and ANIO to AN17 are bit interfaces, respectively.
I? Bit mask signal B M o ” supplied from
BM? This is an AND gate that takes the AND of the signal WEP supplied from the AND gate AN8 and creates a write enable signal WEP (1-WEP7) for the memories M0 to Mt (see FIG. 5).
The type flip-flops LFFI-LPF4 are designed to latch data when an "L" level signal is supplied to the latch terminals each having a negative logic.

Next, referring to FIG. 4, the command control circuit C
C will be explained. Tad“0～Tad” shown in this figure
7 are address data input terminals, and these address data input terminals TadO to Tad7 are each connected to the input terminal of the command register l. A command in this embodiment is specified by an 8-bit command code, and this command code is supplied via an address bus. Command register l latches the command code at the rising edge of row address strobe signal RAS, and outputs command data MC.
It is designed to output as O to MC7. and,
The command register I sends data MCO, which is the least significant bit of the command data, to the data terminal DT of the decoding circuit 3 and the input terminal of the decoder 2.
C5 is supplied to the 0th to 2nd bit input terminals of the decoding circuit 3, and data MC4 to MC6 are supplied to the 0th to 2nd bit input terminals of the main command decoder 4, respectively. In this case, the upper 4 bits of the command data become main command data, and the lower 4 bits become subcommand data.

However, as can be seen from the figure, the most significant bit MC7 of the command data is a don't care bit. here,
Values of command data MCO to MC7 (displayed in hexadecimal),
The relationship with command names is shown in the table below.

Table 1 Note that Table 1 lists only commands related to the present invention, and the functions of the listed commands will be described later.

The decoding circuit 3 receives signals PAM, CME,
PME.

It has 0th to 7th D-type flip-flops for outputting BCE, LSE, FSB, DBT, and ROE, respectively, and one of the D-type flip-flops is selected depending on the 3-bit data supplied to the input terminal. is now selected. That is, the D type flip-flop whose number corresponds to the 3-bit address data supplied to the input terminal is selected. Then, the data supplied to the data terminal DT is supplied to the input terminal of one of the D type flip-flops selected at that time, and when the output signal MDS of the AN21 rises, the data supplied to the D type flip-flop is It is now being incorporated into the That is, depending on the value of the command data MCl=MC3, the signal PAM
, CME, PME, BCE, L
One of S E , FSB, DBT, and ROE is selected, and the value of the selected signal is rewritten to the value (“l”/“0”) of command data MCO. Further, the clear terminal CL of the decoding circuit 3 is supplied with a reset signal from the power-on reset circuit 5, and as a result, when the power is turned on, the 0th to 7th D-type flip-flops are activated. Everything is now cleared.

The main command decoder 4 outputs the °l" signal from the output terminal of the number corresponding to the 3-bit data supplied to the input terminal. This main command decoder 4 outputs 8 types of control signals. However, in this figure, only the signal RGA related to the present invention is shown.Mainly, the main command decoder 4 is enabled when the signal MC5T is supplied from the AND gate AN20. .

The decoder 2 is supplied with the signal WEW from the timing control circuit TC, and the main command decoder 4
When the signal RGA is supplied from the circuit, it becomes enabled, and if the data MCO is "0", it outputs the signal RPW, and if the data MCO is "1", it outputs the signal WPW.

[Memory Block MBO FIG. 5 is a block diagram showing the configuration of memory block MBO, and each memory M in memory block MBO. -M7
captures the row address output on address buses AO-A7 at the rising edge of the row address strobe RAS, and captures the column address on the address bus AO-A7 at the rising edge of the column address strobe CAS to determine the access address. do. and,
During a read cycle, data is output when the signal OE W (output enable signal) rises after the access address is determined, and during a write cycle, the signals WEP and -W are output when the access address is determined or after that.
Data is written to the memory in which EP7 is set to high level.

[Bit Interface BTIi] Figure 6 shows the bit interface BTIi (
1 is a block diagram showing the configuration of TIO1 (i=0 to 7, and the same applies hereinafter);
) is the data output terminal. Data person output terminal T
The data input from IOi is sent to the 0th... of selector 10 via buffer BFFI. The signal is supplied to the second and third bit input terminals and to the input terminal of the L-type flip-flop LFF6. Selector IO is the signal PAM
is “L” and the signal NMA is other than “0”, the O1 and the second
．． The third bit input terminal is selected to output the data supplied to the terminal Tl0i, and only when the signal PAM is "L" and the signal NMA is "0", the first bit input terminal is selected and the pixel interface PXI- 0 (see FIG. 7). The output signal W D T i of the selector IO is a D-type flip-flop DFF.
7 is supplied to the input end of the D-type flip-flop DF
F7 is a signal W D when the signal W E W supplied from the timing control circuit TO rises.
Take in T i. This D type flip-flop DF
The output signal 5RCi of F7 is supplied to the corresponding memory Mi by sequentially validating the buffer BPF3 and the data bus DTi (see FIG. 1). The buffer BFF3 is enabled when the signal WEP supplied from the timing control circuit TC is "1".

The L type flip-flop LFF6 is designed to take in data when the signal RASW supplied from the timing control circuit TC rises, and its output signal F B M i is supplied to the first bit input terminal of the selector 11. It is now possible to do so. A positive voltage is applied to the 0th bit input terminal of the selector 11 via a pull-up resistor, and the command control circuit CC
When the signal BCE supplied from the circuit is "0", the 0th bit input terminal is selected, and when the signal BCE is "1", the 1st bit input terminal is selected. The output signal of the selector 11 is supplied as bit mask data B M i to the timing control circuit TC.

BFF2 is a buffer whose input end is connected to the data bus DTi, and whose output end is connected to the data input end of the output data buffer 12 and the input end of the open-drain output buffer BFF5. The output data buffer 12 is an AND gate A N
When the signal OEi supplied from 25 is "L", the data supplied to the input terminal is output to the data input/output terminal Tl0i. BFF6 is an open-drain buffer whose input terminal is grounded, and this buffer BFF6 and buffer BFF5 are connected to an AND gate AN.
When the signal 0EPi supplied from 26 is "L", it becomes an enable state, and each output signal D O1
1-OE Pi Pixel Interface PXI-
Supply to 0.

AND gates AN27 and AN28 each receive a signal M
K A , B M i , R P M P , P A
This is a gate that generates a signal RWX and a signal RPX based on M, and an AND gate AN26 generates a signal 0EPi by ANDing the signal RPX and the signal OEW.

Further, the OR gate 0RIO is a gate that takes the logical sum of the signal RWX and the signal NC8, and the AND gate AN25 takes the AND of the output of the OR gate 0RIO and the signal OEW to create the signal OEi.

[Pixel Interface] FIG. 7 is a block diagram showing the configuration of pixel interface PXI-0. In this figure, Txop-
o is a pixel data input/output terminal, and the data input from this pixel data input/output terminal Tl0I)-〇 becomes data DIF via the buffer BFF I O, and is then input to the L type flip-flop L'FFl0. It is supplied to each input terminal of the D-type flip-flops DFF I l and DFF 12, and is also supplied to each selector 10 (see FIG. 6) in the bit interface BT I o'=B T I described above. It has become. The L-type flip-flop LFFIO takes in the data supplied to the input terminal when the signal 11A SW supplied from the timing control circuit TC (Fig. 3) rises, and inputs the data supplied to the input terminal of the D-type flip-flop D.
FFil and DFF I2 are signals W P W supplied from the command control circuit CC, respectively.
The data supplied to the input terminal is taken in when RPW rises. L type flip-flop LFFIO, D type flip-flop DFFI
1. The output signals FC9, PWP, and FRP of I2 are respectively supplied to the first bit input terminals of selector l5.16.17, and the 0th bit input terminal of selector l5.16.17 is connected to a pull-up resistor. A positive voltage is applied through the terminal. The selector 15 is a command control circuit CC
The 0th bit input terminal is selected when the signal BCE supplied from the circuit is "0", and the 1st bit input terminal is selected when the signal BCE is "1". Further, the selectors 16 and 17 each select the 0th bit input terminal when the signal PME supplied from the command control circuit CC is "0", and select the 1st bit input terminal when the signal PME is "L". Select the input end. In this case, selector 16.17 is actually II
For convenience of explanation, it will be displayed as two selectors.

Reference numeral 18 denotes a pixel output data buffer, which, when an "1" signal is supplied to the enable terminal E, outputs the signal supplied to the data terminal to the pixel data input/output terminal Trop-o. In this case, a positive voltage is applied to the data terminals via the pull-up resistors, and the bit interfaces BT1. ~BTI? Data D0° to D07 are supplied from. The enable terminal E of the pixel output data buffer 18 receives signals -0Epo to -0EP from the bit interfaces BTIO to BTI.

is supplied via an inverter INV5, and a positive voltage is applied to the input terminal of the inverter INV5 via a pull-up resistor.

The above is the configuration of each part of the circuit in this embodiment.

Operation of the Embodiment Next, the operation of this embodiment with the above configuration will be explained.

In this embodiment, as described above, there are two operating modes in the memory read/write cycle: normal mode and mask mode. On the other hand, there is a command write cycle for writing commands, which is completely separate from the above cycle. Therefore, in the following explanation, we will explain the read cycle and write cycle in this order.
Further, in each cycle, the normal mode, mask mode, and command write cycle will be explained as appropriate.

(1) Read cycle (a) Normal mode As shown in FIG. 8(a), when the row address strobe signal RAS rises at time t1, the level of the column address strobe signal CAS is "0", Further, when the write enable signal WE and the output enable signal OE are at the "0" level as shown at P1 and P in the figure, the normal mode is selected. That is, if the above-mentioned conditions are satisfied, the output signal NME of the AND gate AN1 shown in FIG. 3 becomes "l" and the normal mode is selected. and,
This signal NME is the row address strobe signal R.
At the rising edge of AS, that is, at the rising edge of the signal RASW, it is taken into the L-type flip-flop LPF2, and thereafter the output signals N to IA of the L-type flip-flop LFF2 maintain "I", thereby establishing the normal mode. be done.

Next, at time t shown in FIG.
When the strobe signal CAS rises and the write enable signal WE at this point is at the "0" level,
A read cycle operation is initiated. Also, at this point, the column address is determined, and as a result,
The address to be accessed is determined. Therefore, the same addresses of the memories MBO to MB3 in each of the memory devices #OM to #3M are accessed all at once, and data within the addresses is read out. Then, the read data is transferred to the output data buffer 1 by sequentially valves the data bus DTi and the buffer BFF2, as shown in FIG.
The output data buffer I2 is supplied to the data terminal No. 2, and is output to the data bus O1 at the timing when the output data buffer I2 is enabled.

The timing at which the output data buffer 12 becomes enabled is the same as the timing at which the signal OE W becomes an "l" signal if the OR gate onto outputs an "l" signal, and the timing when the signal ○E W becomes "1". ”, as shown in FIG. 3, the output enable signal OE is “1” while the column address strobe signal CAS and the signal RASW are “lo”.
In other words, in the example shown in FIG. 8, when the output enable signal OE becomes "1" at time t, the above conditions are met and the output signal of the AND gate AN25 becomes "L". becomes “1”, the output data buffer 12 becomes enabled, and the eighth
Data is output at the timing shown in the figure (f).

Next, the conditions under which the OR gate 0RIO outputs the "l" signal will be explained. In order for the OR gate ORI O to output the °l" signal, either the signal RWX or the signal NCS needs to be "l"; however, in this normal mode, as can be seen from Fig. 3, the signal M M fE ,
, ~iKA do not go to the "L" level, so the signal RWX, which is the output signal of the AND gate AN27, never goes to "1". Therefore, the output signal of the OR gate ORI O is uniquely determined by the value of the signal SOS. The signal NCS will be explained below.

At time t shown in FIG. 8, when the row address strobe signal RAS rises, it is the input timing of the chip select data, and the 4-bit chip select data is applied to the input/output terminals TIop-o to Tl0p.
-Supplied from 3. Then, the chip select data supplied at this time is the pixel interface PXI-
0~L type flip-flop LFF in PXI-3
10 (see FIG. 7) at the rising edge of the signal RASW. For example, the 0th chip select data
Assuming that the bit is supplied from the input/output terminal Tl0p-0 shown in FIG. 7, this signal is supplied to each input terminal of the L-type flip-flop LFF10 and the D-type flip-flop DFFI15DFF12 via the buffer BFF10. In this case, the signal RA SW is at time t1
However, the signal RP~v, w p w
As will be described later, is not output at this point, so the chip select data is taken only into the L-type flip-flop LFFIO and the D-type flip-flop DFFII.

It is not included in 12. As a result, the value of signal FC8 corresponds to the chip select data, and instead of being "1", it becomes "0".
”, and the first bit input terminal of the selector 15 is “l”.
Alternatively, a "0" signal is supplied. And selector 1
5, the value of the output signal CSMP of the selector 15 is equal to the signal FCSO value (
In other words, regardless of the chip select data value),
If the value of the signal BCE is “l”, the signal CS
MP has the same value as the chip select data value.

This signal C8MP is applied to the AND gate AN5 shown in FIG.
, where it is ANDed with the signal NMA, which is already an "L" signal.

As a result, the value of the output signal NC5 of the AND gate AN5 is determined by the value of the signal CSMP. Therefore, if the signal BCE is "l", the value of the signal NC3 is uniquely determined by the value of the chip select signal. It is determined.

The signal NC8 is the OR gate 0RIO shown in FIG.
is supplied to one input terminal of the OR gate 0RIO to determine the output signal value of the OR gate 0RIO.

As can be seen from the above, selector 15 (Fig. 7)
If the value of the signal BCE supplied to the chip select data is "l", the output data buffer 12 is enabled according to the value of the chip select data when the data is "l". That is, among the memory devices 2#OM to #3M, only the memory device whose chip select data is "1" sends read data. For example, as shown in FIG. 9, memory device #IM! ,: If only the supplied chip select data is “l”, the memory device #
1 to 8-bit data D. -D7 is output.

In this figure, the symbol "X" indicates a don't care bit. In other words, the output terminal of the output data buffer 12 of the memory device that does not output data becomes high impedance. Furthermore, if the chip select data for two or more memory devices is "1", data will be output from these memory devices at the same time, causing a contention condition on the common data bus ■0° to IO7 (see Figure 2). ), in this case "0" is given priority for each bit. This is because the output data buffer 12 in each memory device is an oven-drain output (however, data is normally read from any one memory device).

As can be seen from FIG. 9, when reading in this normal mode, you can specify any memory block and perform 8-pit parallel reading individually.
This is suitable for cases where areas within memory blocks MBO to MBs are used as program areas.

On the other hand, the signal BCE supplied to the selector 15 (FIG. 7)
When is "0", the chip select function does not work.

Here, signal BCE will be explained. This signal BCE
The value is “l” when the command “Bit/Chip Select Mask Enable” shown in Table 1 above is supplied.
This is the signal, and writing the command in this case is
This is done as follows.

First, as shown in FIG. 1θ, at time trot, the row address strobe signal RAS rises, and at this point the column address strobe signal CAS
If the write enable signal WE is at the "L" level, the command write mode is selected. That is, when both the column address strobe signal CAS and the write enable signal WE are "L", the signal =M which is the output signal of the AND gate AN3 shown in FIG.
CE becomes “L” and this “L” signal becomes the row address.
At the rise of the strobe signal RAS, it is taken into the L type flip-flop LFF4. Therefore, after time tlG, the output signal MCC of the L-type flip-flop LFF4 becomes "L" and the command write cycle operation begins. Also, and gate A
The output signal MCD of N9 becomes "L" while both the row address strobe signal RAS and the signal RASD are "B".In other words, the signal MCD is slightly delayed from the rise timing of the row address strobe signal RAS. stand up.

On the other hand, a "bit/chip select mask enable" command is supplied to the command register l shown in FIG. 4 via address buses AO to A7, and this command is taken in at the rise of the row address strobe signal RAS. As shown in Table 1, the command [Bit/Chip Select Mask Enable] is expressed in decimal notation (0
7), so the command register l
The output of MC0 to MC2 is ``bi signal'', and the output of MC2 is ``bi signal''.
0" signal, and the "l" signal is supplied to the 0th and 1st bit input terminals of the decoding circuit 3. As a result, the decoding circuit 3 changes the signal BCE corresponding to the decoding result r3B of the input signal to "l". Then, the signal BCE is set to "1" at the timing when the signal MDS supplied to the clock terminal rises.Then, the signal MD
Since S rises slightly later than row address strobe signal RAS, signal BCE becomes a "1" signal at a timing slightly delayed from time tlG shown in FIG. 1O. As can be seen from the above, when the memory device according to this embodiment is used as a normal memory, the signal BC
E is set to "0", and when it is desired to enable the pit/chip select mask, the signal BCE is set to '1'.

The above is the process until the signal BCE becomes "1". The above-mentioned command "Bit/chip select mask enable" is normally written before normal mode access, and during normal mode operation,
Chip select data is set to be valid for memory devices #OM to #3M. That is, during normal mode access, the input/output terminals top-o to l0p- are activated at the timing shown in FIG.
Supply chip select data from 3 to memory device #O
Any one (or two or more) of M to #3M is selected, and in subsequent data reading at time t4, data other than the selected memory device is masked.

Similarly, at the next access timing t, chip select data for selecting a desired memory device is supplied from the input/output terminals 109-0 to Iop-3. In this way, a desired memory device can be selected prior to accessing it within a memory read cycle, and chip selection can be effectively performed at extremely high speed.

The above is the normal mode operation in the read cycle.

(b) Mask mode Next, the operation in mask mode in the read cycle will be explained.

The signal conditions for each part of the circuit for setting the mask mode are as described above for the normal mode setting, except that the write enable signal WE is at the "L" level at the rise of the row address strobe signal RAS. The conditions are the same as those for

That is, if the row address strobe signal RA S rises at the time shown in FIG. 8, then
At this point, the column address strobe signal CA
The conditions are that S and output enable signal OE are at the "0" level, and the write enable signal WE is at the "1" level as shown at point P in FIG.

When the above-mentioned conditions are satisfied, the output signal MME of the AND gate AN2 shown in FIG. 3 becomes the "l" signal, and this "l" signal becomes the row address strobe signal R.
L type flip-flop LFF when AS rises
3, and since then L type flip-flop LFF
The output signal MKA of No. 3 maintains the "L" level, and the mask mode is established.

Next, when the column address strobe signal CAS rises at time t, the column address is taken in at this point, and the address to be accessed is determined. Then, at time t4, when a predetermined period of time has elapsed after the access address was determined, the write enable signal WE is "0" and the output enable signal OE is "1". Data is output, but this data is appropriately masked bit by bit and memory device by memory device. Here, the data output state when mask processing is performed will be explained.

FIG. 11 shows the mask state when reading in the word direction.
MP indicates the values of the signals shown in FIGS. 6 and 7, respectively. In this figure, memory device #OM,
#3 Signal RPMP in M is “0”, memory device #I
The signal RP MP in M and #2M becomes “l”, and the signal B
The case where M 7 to B Mo is (00111100) is shown. In addition, signal BM.

~BM? is the same value in each of the memory devices #OM to #3M, which will be described later.

Now, signal B M o = B M 7 and signal RP
When MP reaches the value shown in Figure 11, the common data bus IO
8-10? The 7th, 6th, 1st, and 0th bits of
The fourth, third, and second bits have a value of (0100). That is, only the data of the memory device where the signal RPMP is "1" and the data of the bit where the signal B M i is "1" is in the output enabled state, and furthermore,
If there is a conflict between the output data, the "0" signal takes priority.

The above is the data output after mask processing when reading in the word direction.

FIG. 12 shows a mask state when data is read in the pixel direction, and the texture of the symbols shown in the figure is the same as that shown in FIG. 11. In this case, only the data of the memory device whose signal RPMP is “L” and the bit whose signal B M i is “L” is enabled for output, and the data of each memory device is The corresponding bit is input terminal 'rxop-o~Tl
Each is output to 0p-3. At this time, if there is a data conflict within the same memory device, the "0" signal is given priority and output.

The setting of the value of the signal B M i and the value of the signal RP M P and the read operation after the setting will be described below.

■Bit-by-bit mask setting The bit-by-bit mask is stored as bit mask data (8 bits) in the memory device Z#OM via the common data bus IOo~■0° at time 1 shown in FIG.
~ #3M are respectively supplied. This bit mask data is data in which the bit to be masked is set to "0" and the bit not to be masked is set to "1". Then, either the I pit in the bit mask data or the data bus IO shown in FIG.
i, supplied to the input terminal of L-type flip-flop LFF6 via buffer BFFI (common to each memory device)
. The L-type flip-flop LPF6 takes in the mask data supplied to its input terminal at the rising edge of the signal RASW (at the same timing as the rising edge of RAS), and supplies it to the first bit of the selector 11 as the signal F B M i. . Here, if the signal BCE is set to "1" by the above-mentioned command writing, the output signal B M i of the selector 11 matches the value of the mask data and becomes "1".
0" or "l". Then, this signal B M
i is supplied to each input terminal of AND gates AN27 and AN28, thereby output data buffer 12 and buffer BFF5 . It contributes to turning on/off the signal OE ilo E P i which is the enable signal of BFF6. Furthermore, as is clear from Fig. 3, the signal NC8
is not output in mask mode.

In this case, when the output data buffer I2 is enabled, the data read from the memory Mi (see FIG. 1) is sequentially processed through the buffer BFF 2 and the output data buffer 12 to be shared by each memory device. It is output to data bus IOi. Also, buffer BFF
5. When BFF6 is enabled, the data read from the memory M i is supplied to the input end of the pixel output data buffer 18 shown in FIG. Since the output signal of becomes "1" and the pixel output data buffer I8 is enabled, the data read from the memory Mi is transferred to the pixel output data buffer 1.
input/output terminal Tl0p-0 (or T I
Op-1-TI 0p-3). That is, the signal OEi determines permission/non-permission of word direction data output, and the signal ○EPi determines permission/non-permission of pixel direction data output.

■Mask setting for each memory device The mask data for each memory device can be set at the input/output terminal T when executing the command “Read Plane Mask” shown in Table 1.
Supplied from l0p-0 to 'riop-3. Figure 13 shows that when executing the command "Read Plane Mask", the row address
At time t30 when the strobe signals R and AS rise, if the column address strobe signal CAS and the write enable signal WE are "1", a command write cycle is started. The operation up to this point is the same as that described above and shown in FIG. 10. After one cycle, the value written to the command register l (FIG. 4) at time ho is (10) in hexadecimal as shown in Table 1. As a result, “l” of the output of command register 1
The MC4 is the only signal that is doubled, and the "l" signal is supplied to the 0th bit input terminal of the main command decoder 4. When the signal MC9T supplied to the enable terminal rises, the main command decoder 4 decodes the input signal and makes the signal RGA an "L" signal. In this case, the value of signal MC5T is equal to the value of signal M CD and signal c S
Determined by the logical product of M P. And signal M
In the CD command write cycle, the signal RA is
It becomes “1” when SD (Fig. 3) rises, and thereafter it becomes “1”.
This is a signal that maintains the l'' level, and the signal Cs y
IP (see FIG. 7) is a signal that is always "1" if the signal BCE mentioned above is "0", and has a value corresponding to the chip select data if the signal BCE is "1".

Therefore, writing of the command "Read Plane Mask" is performed at the rising edge of the signal RAS under the conditions that the signal BCE is "1" and the chip select data is "L", or the signal BCB is "0". It is held at the time of

As described above, at time tzo, the command "read plane mask" is written to the command register l. However, at this time t30, the first
In Figure 3 (a), the signal RASD is “0” as shown by the dashed line.
” signal, the signal MCD does not become an “L” signal (see Figure 3), and as a result, the signal MCS shown in Figure 4
T does not become a “1” signal.

Therefore, main command decoder 1 is not enabled. Next, at time t3□, the row address strobe signal RAS, the signal RASD, and the column address strobe signal CAS.

Both signals WE become "1" signals, and as a result, the main command decoder 4 becomes enabled and the signal R
Set GA to “1”. Also, at time t3□, the signal 'VVEW becomes "1" (see Figure 3, qq).
, As a result, the decoder 2 becomes enabled.

At this time, since the command data to ICO supplied to the input terminal of the decoder 2 is a "0" signal, the decoder 2 receives the signal RPW at the timing when it is enabled.
is "1". Since this signal RPW is supplied to the clock terminal of the D-type flip-flop DFF12 shown in FIG. 7, at this point, the D-type flip-flop DFFI2 takes in the data supplied to its input.

On the other hand, mask data for each memory device (hereinafter referred to as read plane mask data) is obtained at time t3 shown in FIG.
1 from input/output terminals Tl0p-0 to T10p-3, and this plain read mask data is supplied to the input end of a D-type flip-flop DFF12 via a buffer BFF IO shown in FIG. As a result,
The read plane mask data is D at time t31.
Type flip-flop DFF] is taken into 2,
Output signal F'R of D type flip-flop DPF12
It matches the value of P or the value of the read plane mask data.

Since the signal FRP is supplied to the first bit input terminal of the selector 17, if the signal PME is "1", the value of the signal RPMP matches the value of the read plane mask data. This signal RPMP is applied to the AND gate AN27. It is supplied to the input terminal of AN28 and contributes to turning on/off the signal 0EPi and signal OEi described above.

The signal PME is a signal that becomes "l" when the command "plane mask enable" (see Table 1) is executed. Writing of this command "plane mask enable" is performed at the timing shown in FIG. 10, similar to the case of the command "bit/chip select mask enable" described above. There are two types of commands in this embodiment: those that write data to a predetermined flip-flop in the memory device, and those that do not involve writing data. Commands that involve data writing are based on the timing shown in FIG. , those that do not involve data writing are written at the timing shown in FIG. 1O.

■The functions of the signal B M i and the signal RP M P The signal B M that contributes to bit-by-bit masking
i and a signal RPMP that contributes to the masking of each memory device.
are set, and these signals are connected to the computer (Antogame) AN27. A
Supplied to N28. This AND gate AN27. AN
28 output signals or contributing to the on/off of the signals OE i, o E P i and the signals OE i, o E
It has already been mentioned that P i contributes to data output enable in the word direction and pixel direction, respectively, and the relationship between these signals will be explained in detail below.

First, as you can see from Figure 6, the AND gate, AN27
and/! The conditions for MJ28 to output the "1" signal are the same except for the conditions for signal PAM.

This signal PAM is generated according to the timing shown in FIG.
This signal becomes "l" when the command "pixel access mode" (see Table 1) is written, and is cleared when the power is turned on and when the command "word access mode" is written.

That is, after executing the command "pixel access mode" to set the pixel access mode, the signal P
A~1 becomes “1” and AND gate AN28 becomes “l”
When the signal output is enabled and the word access mode is set, the signal PAM becomes "0" and the AND gate AN27 becomes the "1" signal output enabled state.

Assuming that word access mode is currently selected,
AND gate AN27 is now able to output an “L” signal, but
Among the signals supplied to the AND gate A N 27, the signal MKA (see Figure 3) is set to mask mode and is set to 1.
After this, the signal becomes "L" constantly, so the output signal of the AND gate AN27 ends up being the signal BM1 and the signal R.
Determined by logical AND with PMP. That is, when both the signal B M i and the signal RPM P are "1", the output signal of the AND gate AN27 becomes "1", and the signal O supplied to one input terminal of the AND gate AN25 becomes "1".
When Ew becomes "1", the signal OEi becomes "1" and the output data buffer 12 becomes enabled. Therefore, as illustrated in FIG.
~11 and the signal I P MP are both “1”, and only those bits are output to the data bus I Oo=I O7.

In addition, if the pixel ac mode is selected, the anchor AN28 will be “capable of outputting the bi-signal, but
The output signal of the AND gate 8N 28 is determined by the AND of the signal B M i and the signal RP M P in exactly the same way as in the above case. Therefore, as shown in FIG. 12, only the bit data for which both the signal B M i and the signal RPMP are "L" is sent to the input/output terminal 'r+op-o.
~Tl0p-3.

The above is the read cycle operation in mask mode, and the desired memory device and desired bit can be appropriately masked prior to access within the read cycle, and these settings and switching can be performed at extremely high speed. be able to.

The conditions for setting the states shown in FIGS. 11 and 12 are summarized as follows: In the case shown in FIG. 11, mask mode setting, signal PME.

The conditions are that the signal BCE is "1" and the signal PAM is "0", and in the case shown in FIG. 12, the mask mode setting, the signal PAM, and the signal PSI are
The condition is that E and signal BCE are "1". Furthermore, as shown in FIG. 18, when reading out pixel data (4 bits) corresponding to one dot, the signal RPMP in all memory devices is set to "B" and (
(see FIG. 12), the signal B M i at the position corresponding to the dot to be read may be set to "B".

(It) Write Cycle Next, the write cycle will be explained. Similar to the read cycle described above, the write cycle also includes a normal mode and a mask mode, and in addition to these cycles, there is a command write cycle. These will be explained below.

(a) Normal mode This mode is similar to the normal mode in the read cycle, and as shown in Figure 9, data can only be written to memory devices whose chip select data is "1". This is a word-wise mode.

The setting of this mode is exactly the same as in the read cycle, and when the row address strobe signal RAS rises at time t40 shown in FIG.・If the enable signal W E and the output enable signal OE are at the "0" level, the normal mode is set, and the signal N M E and the signal N M shown in FIG. 3 are set.
A becomes a "1" signal one after another, and the normal mode is established.

Next, at time t4□ shown in FIG. 14, the column address strobe signal CAS rises, and the write enable signal WE at this time is "1".
Write cycle execution begins. Also, at this point, the column address is determined, and as a result, the address to be written is determined. Therefore, the same address in each memory device #OM to #3M is accessed all at once, and the common data bus 10. -10? The above data will be written at the same time. In this case, as in the read cycle described above, writing of depth select data is possible at time t40 when the row address strobe signal RAS rises, and chip select data is supplied at this timing, and If the signal BCE is "l", data is written only to the memory device whose chip select data is "l". This chip select operation will be explained below.

First, at time 41, which is a data write timing, the data on the supply data bus IOi is transferred to the 0th...
Second. The signal is supplied to the third input terminal. In this case, in the normal mode, since the signal NMA is an "L" signal, the selector IO selects the second or third bit input terminal. Therefore, the data supplied to the second or third bit input terminal of the selector 10 passes through the selector IO, and is taken into the D-type flip-flop DFF7 at the rising edge of the signal WEW, and is input to the signal 5RCi. is output as This signal 5RCi is supplied to the memory Ml when the buffer BFF3 is enabled, but the signal WEP that enables the buffer BFF3 requires that the signal NC3 becomes "1" as shown in FIG. Otherwise, it will never become an "L" signal. Then, the value of signal NC5 is equal to the value of signal NMA and signal CSMP.
Therefore, when the chip select data is "0" and the signal CSMP is "0", the signal WEP does not become "I" and the signal 5RCi is not supplied to the memory M i.

Furthermore, if the signal WEP is not output, the signal 'wV E P o -W E P ?' shown in FIG. 3 is output. Memory M is not output at all. -A write enable signal is not supplied to M7 (see FIG. 5), and no write operation is performed. As described above, when the signal B CE h<l, data is written only to the memory device whose chip select data is "l".

Note that if the signal C9MP is "L" by the OR gates 0R30 to 0R37 shown in FIG.
becomes “I” without being affected by. That is, in the normal mode, each memory M. - It is possible to write to M7 all at once.

(b) Mask mode In the state shown in FIG. 14, if the write enable signal WE is at the "L" level at time t4, the mask mode is set. That is, when the write enable signal WE is set to "L" in the state shown in FIG. 14, the signal MME and signal MKA shown in FIG. execution begins. Next, when the column address strobe signal CAS rises at time t41, the column address is taken in at this point, and the address to be accessed is determined. Then, at time t41 when the address to be accessed is determined, data is immediately written to the corresponding address as shown in FIG. In this case, the data written to the memory is appropriately masked for each bit and each memory device.

The data write state when mask processing is performed will be described below.

FIG. 15 shows a mask state when data is written in the word direction, and the signal WPMP shown in the figure is the output signal of the selector 16 shown in FIG. In FIG. 15, the signals W P M P in the memory devices #IM1 #2M and #3M become "l", and the signals B M ? ~B
The case where M o is (00110011) is shown.

The signal 13 Mo-B M 7 has the same value in each memory device, which is the same as in the mode described above.

Now, the signal B l'/1 o -B M 7 and the signal W P M P are in the state shown in FIG. 15, and the data D7 to Do are (00101110
) is supplied, the memory Mi of the memory device in which the signal W P M P is “1” and the signal B M
o-B Data is written only to bit positions corresponding to bit positions where M7 is "1". In this case, the memory device W #IM ~ #
For 3M, all data is written in the same way.

FIG. 16 shows the mask state when data is written in the pixel direction, and in the state shown in this figure,
The memory M i of the memory device in which the signal 'vV P M P is "1" and the signal BMo-BM7
The memory Mi corresponding to the bit position where is “l”
Data is written only to the In this case, the bits that can be written in each memory device #ON1 to #3M have input/output terminals Tl0p-0, respectively.
The data supplied from ~Tl0p-3 is written in common.

Signal B M o −B 'S shown in FIGS. 15 and 16
The value of '17 is set in the same manner as in the read cycle described above, and the value of signal WPMP is set as follows.

First, execute the command "j-write brain mask" shown in Table 1, and at the time of execution, input/output terminals Trop-o~
Mask data is supplied from Tl0p-3. This command "write brain mask" is a command for writing data into the D type flip-flop DPF 11 shown in FIG. 7, and the command writing is performed at the timing shown in FIG. 13. That is, at time t3 shown in FIG.
1, the signals W P to V shown in FIG. 4 rise, thereby causing the input/output terminals T10p-0 to
At the same time t31, the mask data supplied from p-3 is taken into the D-type flip-flop DFF 11 via the buffer BFF 10 shown in FIG. 7, and output as signals F to ■P. As a result, the value of signal FWP matches the value of mask data. Since the signal FWP is supplied to the first bit input terminal of the selector 16, if the signal PME is "1", the output signal WPMP of the selector 16 is a signal whose value matches the mask data. becomes. In addition, the signal PME is “
l”.

Next, the effects of the signal B M i and the signal W P M P will be explained. These signals all contribute to turning on/off the write enable signals WEP and -WEP7, as shown in FIG. In other words, the signal ~■PM! ' is "0", the output signal M of AND gate A N 6
WP becomes "0", and as a result, the output signal of OR gate OR2 becomes "0" (signal NCS is always "0" in mask mode). Therefore, the output signal WEP of the AND gate AN8 becomes "0" and the write enable signal WEPO to WEP? to each memory Mi is output. are all “0”
Therefore, writing to either memory is not permitted.

Also, the signal W P M P becomes "l" and the signal WEP
Even if it becomes "I" at a predetermined timing, if either signal BM or -BM7 is "0", the write enable signal W E P i of the bit that is "0" is No output. That is, writing is permitted for the signals W P M P and the signals BM, ~
Only bits in which both BM and BM are "L" are included.

Data writing in the word direction is performed from common data bus l0i to buffer 13FFI (Fig. 6) → selector 1.
0th 0. Second. Data to be written is transferred through the path 3rd bit input terminal -> D type flip-flop DFP7 - buffer BFF3 - memory Mi, and data writing in the pixel direction is performed through input/output terminals Tl0p - i - buffer BFP10 (Figure 7). The data to be written is transferred through the following path: - first bit input terminal of selector IO (FIG. 6) - D type flip-flop DFF7 - buffer BFF3.

The above is the operation of the mask mode in the write cycle. The desired memory device and desired bit can be appropriately masked prior to access within the write cycle, and these settings and switching can be performed at extremely high speed. be able to.

-To summarize the conditions for setting the states shown in FIGS. 15 and 16, in the case shown in FIG. 15, the mask mode setting, signal PME, and signal BCE are
", and the signal PAM force is 0", and in the case shown in FIG. 16, the mask mode setting, signal PAM, signal PME, and signal BC
The condition is that E is "1".

Furthermore, this embodiment has a late write cycle mode which is a write cycle with a different timing from the write cycle shown in FIG. In this write cycle, as shown in FIG. 17, data is written after a predetermined period of time (time t52) after a column address is fetched and ltf has elapsed.

The above is the configuration and operation of this embodiment.

Note that a serial I10 buffer for serially inputting and outputting data may be added to this embodiment, thereby configuring a triple port memory.

Furthermore, although the above embodiment is an example in which four memory devices are combined in parallel, one or more memory devices may be used depending on the purpose.

Furthermore, the connection relationships among the bit interface, pixel interface, timing command control circuit, and memory section and the assignment of various functions are not limited to those shown in the above embodiments, and various modifications are possible.

For example, as shown in FIG. 19, memory blocks 70 to 73 having a memory interface MI and memory block interfaces 75 to 78 are provided, and the memory interface MI is provided with a write bit mask function. may be provided with various other functions.

Furthermore, if the memory capacity is large, a configuration as shown in FIG. 20 may be used. In this figure, each memory block 80.81 is a 4bx64kx4 plane (4 planes), and each memory block 80.81 is provided with a memory interface Ml. In this case, each memory interface Ml is configured to exchange data in units of 4 bits with the memory block interface MBI. The memory block interface MBI is configured to send and receive data to and from external circuits in units of 8 bits in the word direction and in units of 4 bits in the pixel direction.

In the example shown in FIG. 20, memory interface M
The functions required for I are a word direction/pixel direction switching function, a read/write bit mask function, a write plane mask function, and a read plane mask function.

As a result, when the input/output data of the memory interface Ml is switched to the word direction, it becomes the data of the word direction of the selected l or multiple planes, and when it is switched to the pixel direction, it becomes the data of the word direction of the selected plane or multiple planes. It becomes pixel data. Further, in read/write cycles, bit masking can be performed for each surface.

Further, the memory block interface requires a word direction/pixel direction switching function, a read bit mask, and a read plane mask. Then, when the word direction is switched, the 4 bits of data input/output by each memory interface M1 are combined into 8 bits, and these 8 bits of data are input/output as word data according to the read plane mask. On the other hand, when switching is made in the pixel direction, each superimposed pixel data outputted from each memory interface Ml is inputted and outputted by ANDing the data corresponding to the same surface according to the read hit mask.

"Effects of the Invention" As explained above, according to the present invention, one or more memory sections are provided in the plane direction, and the memory section normal mode, which selects a memory section; and a mask mode, which performs a bit mask based on bit mask data that instructs masking of any bit, or a memory section mask based on plane mask data that instructs masking of any memory section. and has a selection means that selects either the normal mode or the mask mode depending on the value of a predetermined memory control signal when the memory access start control signal becomes active, so that Each mode can be switched, thereby providing the effect that a program area and an image data storage area can be mixed in the memory section, and these can be switched and used at high speed. Therefore, memory usage efficiency can be greatly improved. Furthermore, by accessing data bit by bit, there is an advantage that image data etc. can be rewritten efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the connection state of memory devices,
Figure 3 is a block diagram showing the configuration of the timing control circuit TC, and Figure 4 is the command control circuit C.
5 is a block diagram showing the configuration of the memory block, FIG. 6 is a block diagram showing the configuration of the bit interface, FIG. 7 is a block diagram showing the configuration of the pixel interface, and FIG. 8 is a block diagram showing the configuration of the pixel interface. 9 is a timing chart of the read cycle of the same embodiment, FIG. 9 is a diagram showing the data output state of each memory device in normal mode, FIGS. 10 and 13 are timing charts of the command write cycle, and FIG. 11 is a diagram showing the data output state of each memory device in normal mode. , FIG. 12 is a diagram showing the relationship between the mask state and output data during a read cycle, FIG. 14 is a timing chart of a write cycle, and FIGS. Diagram showing the relationship with the included data, No. 17
The figure is a timing chart of a late write cycle, FIG. 18 is a conceptual diagram showing the relationship between the frame buffer and the display surface, and FIGS. 19 and 20 are connection modes of memory blocks and various interface sections in this invention, respectively. FIG. TCC...Timing command control, MBO...Memory block, BTl,~13
TI7...Bit interface, PXI-0...
...Pixel interface.

Claims (4)

[Claims] (1) A normal mode that has one or more memory sections provided in the plane direction and selects a memory section based on select data that instructs selection of one of the memory sections; It has a bit mask mode based on bit mask data that instructs masking, or a mask mode that performs memory section masking based on plain mask data that instructs masking of any memory section, and the memory access start control signal is active. 1. A memory device comprising selection means for selecting either the normal mode or the mask mode according to the value of a predetermined memory control signal when . (2) The memory device according to claim 1, wherein a predetermined command instructs whether or not to execute memory section masking using the plane mask data. (3) One or more memory sections provided in the plane direction, a word direction data bus provided in common in the word direction for the same bit number of each memory section, and one word direction data bus provided for each of the memory sections. mask data storage means to which mask data instructing masking of any bit is supplied from a word direction data bus; and select data instructing selection of any one of the memory sections is pixel direction data. a select data storage means supplied from a bus, and a plane mask data storage means supplied from a pixel direction data bus with plane mask data instructing one of the masks in the memory section; A normal mode in which a memory section is selected based on selection data, and a mask mode in which a bit mask is carried out based on mask data in the mask data storage means, or a memory section mask is carried out based on plane mask data in the plane mask data storage means. and a selection means for selecting either the normal mode or the mask mode according to the value of a predetermined memory control signal when the memory access start control signal becomes active. . (4) The memory device according to claim 3, wherein a predetermined command instructs whether or not to execute the memory section mask based on the plane mask data.