JPH0721765A - Memory card - Google Patents

Abstract

PURPOSE:To reduce terminal capacity in a memory card and to reduce the operation current of the memory card by dividing the address line of the memory card to plural blocks with a logic circuit and connecting them to a memory. CONSTITUTION:A card address 2 from a connector 1 is supplied to the input buffer 8 of the logic circuit 5, and the output is divided into two blocks and supplied to the output buffers 9, 10. The output of the buffer 9 is stored in a first memory group 6 as a memory address 12, and the output of the buffer 10 is stored in a second memory group 7 as the memory address 13. At this time, when a main body using the memory card accesses the memory card, a rapid signal like a clock signal is inputted to the card address 2. Then, the operation current of the buffers 9, 10 depend on the terminal capacity connected to the output buffers. Thus, by dividing the card address and storing them in the memory, the terminal capacity is reduced, and the operation current of the memory card is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address line and a data line in a memory card.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional memory card including at least a memory control logic circuit and a plurality of memories.

In FIG. 5, the connector 1 to the logic circuit 5
A card address 2, a card control 3, and a card data 4 are connected to. The card address 2 is connected to the input buffer 8 in the logic circuit 5. The outputs of 8 are connected to the output buffer 31. 31 is connected to the memory group 51 as a memory address 53.
3 is connected to the control circuit 52 in 5 and the output of 52 is connected to 51 as a memory control 54. The card data 4 is connected to 51 as memory data 55.

As described above, generally, the address line input to the memory card is connected to the logic circuit. The address line output from the logic circuit was commonly connected to a plurality of memories. Moreover, the data line of the memory card forms a common bus line for a plurality of memories.

[0005]

In recent years, due to the progress of packaging technology, it has become possible to mount a large number of memories on a thin memory card, and the capacity of the memory itself has increased. Has become.

As a result, the current consumption of the memory card is becoming larger than ever before.

On the other hand, in recent years, many small and lightweight devices have appeared. Most of these devices are driven by batteries, and there is a strong demand for ultra low power consumption of memory cards.

However, in the above-described conventional technique, a large number of memories are connected to one system of address lines and data lines, the terminal capacitance of the address lines and data lines increases, and the operating current of the memory card increases. There was a problem.

Therefore, the present invention has been made to solve such a problem, and the purpose thereof is to:
This is to prevent the operating current of a memory card having a large number of memories from increasing.

[0010]

The memory card of the present invention comprises: (1) In a memory card composed of at least a logic circuit for controlling the memory and a plurality of memories, the address line input to the memory card is It is characterized in that it is divided into a plurality of blocks by a logic circuit, and the divided address lines are connected to the memory.

(2) In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, an address line input to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. The address lines to the memory groups that are not operating are fixed by the logic circuit.

(3) In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, a data line connected to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. The data line is connected to the memory.

(4) In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, a data line connected to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. The data line is connected to the memory, and the data line to the inactive memory group is fixed by the logic circuit.

[0014]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of a memory card showing an embodiment of the present invention.

In FIG. 1, the connector 1 to the logic circuit 5
A card address 2, a card control 3, and a card data 4 are connected to. The card address 2 is connected to the input buffer 8 in the logic circuit 5. The output of 8 is connected to the output buffer 9 and the output buffer 10. 9 is the first memory group 6 as the memory address 12
, And 10 is connected to the second memory group 7 as a memory address 13. 3 is connected to the control circuit 11 within 5, and the output of 11 is the memory control 14, 15
Are connected to 6 and 7, respectively. Card data 4 is connected to 6 and 7 as memory data 16.

When a main body using a memory card accesses the memory card, a fast signal such as a clock signal is generally input to the card address 2. The operating current of the output buffers 9 and 10 at this time largely depends on the terminal capacitance connected to the output buffer. When the terminal capacitance increases, the operating current increases dramatically.

In the embodiment of the present invention, since the card address is divided into a plurality of numbers and connected to the memory as the memory address, the terminal capacity of the memory address is smaller than that when the card address is not divided and is connected to the memory.

FIG. 2 is a block diagram of a memory card showing another embodiment of the present invention.

In FIG. 2, the names and functions of 1 to 7 are the same as in FIG.

In FIG. 2, from the connector 1 to the logic circuit 5
A card address 2, a card control 3, and a card data 4 are connected to. The card address 2 is connected to the input buffer 8 in the logic circuit 5. The output of 8 is connected to the gate 21 and the gate 22. The gates 21 and 22 are, for example, AND gates, and control whether the output signals of 8 are output to the outputs 21 and 22 or fixed without being output, depending on the states of the control lines 23 and 24, respectively. When accessing the first memory group 6, the output of the input buffer 8 is output to the gate 21 and the gate 22 is fixed. When accessing the second memory group 7, the output of the input buffer 8 is output to the gate 22 and the gate 21 is fixed. 21 and 22 are connected to the output buffer 9 and the output buffer 10, respectively.
9 is connected to the first memory group 6 as a memory address 12, and 10 is connected to the second memory group 7 as a memory address 13. 3 is connected to the control circuit 11 in 5, and the outputs of 11 are connected to 6 and 7 as memory controls 14 and 15, respectively. Card data 4 is connected to 6 and 7 as memory data 16.

When the main body using the memory card accesses the memory card, a fast signal such as a clock signal is generally input to the card address 2. The operating current of the output buffers 9 and 10 at this time largely depends on the terminal capacitance connected to the output buffer. When the terminal capacitance increases, the operating current increases dramatically.

In the embodiment of the present invention, since the card address is divided into a plurality of numbers and connected to the memory as the memory address, the terminal capacity of the memory address is smaller than that of the case where the card address is not divided and is connected to the memory.

The operating currents of the output buffers 9 and 10 largely depend on their operating speeds.

As the operating speed increases, the operating current increases dramatically.

In the embodiment of the present invention, since the divided output buffers 9 and 10 are controlled by the independent control lines 23 and 24, the signals of the output buffers connected to the memory groups which are not accessed are fixed. Operating current does not flow.

FIG. 3 is a block diagram of a memory card showing another embodiment of the present invention.

In FIG. 3, the names and functions of 1 to 7 are the same as in FIG.

In FIG. 3, from the connector 1 to the logic circuit 5
A card address 2, a card control 3, and a card data 4 are connected to. The card address 2 is connected to the input buffer 8 in the logic circuit 5. The outputs of 8 are connected to the output buffer 31. Reference numeral 31 is connected as a memory address 32 to the first memory group 6 and the second memory group 7. 3 is connected to the control circuit 33 in 5, and the outputs of 33 are connected to 6 and 7 as memory controls 34 and 35, respectively. The card data 4 is connected to the control circuit 36 within 5. Within 36, the data line is divided into a plurality of data lines. The divided data lines are connected to 6 and 7 as memory data 37 and 38, respectively.

When the main body using the memory card accesses the memory card, a fast signal such as a clock signal is generally input / output to / from the card data 4. At this time, the operating current of the first memory group 6 or the second memory group 7 and the operating current of the control circuit 36 largely depend on the terminal capacitance connected to the operating memory data 37 or 38. When the terminal capacitance increases, the operating current increases dramatically.

In the embodiment of the present invention, the card data is divided into a plurality of pieces and is connected to the memory as the memory data. Therefore, the terminal capacity of the memory data is smaller than that when the card data is not divided and is connected to the memory. .

FIG. 4 is a block diagram of a memory card showing another embodiment of the present invention.

In FIG. 4, the names and functions of 1 to 7 are the same as in FIG.

In FIG. 4, from the connector 1 to the logic circuit 5
A card address 2, a card control 3, and a card data 4 are connected to. The card address 2 is connected to the input buffer 8 in the logic circuit 5. The outputs of 8 are connected to the output buffer 31. Reference numeral 31 is connected as a memory address 32 to the first memory group 6 and the second memory group 7. 3 is connected to the control circuit 33 in 5, and the outputs of 33 are connected to 6 and 7 as memory controls 34 and 35, respectively. The card data 4 is connected to the control circuit 36 within 5. Within 36, the data line is divided into a plurality of data lines. Generally, the data lines are bidirectional, but the divided data lines that are output from the connector side to the memory side are connected to the gate 41 and the gate 42, respectively. The gates 41 and 42 are, for example, AND gates, and control whether the output signals of 36 are output to 41 or 42 or fixed without being output depending on the states of the control lines 43 and 44, respectively. First memory group 6
To read the output of the control circuit 36 to the gate 41
And the gate 42 is fixed. The second memory group 7
To read the output of the control circuit 36 to the gate 42
And the gate 41 is fixed. 41 and 42 are connected to an output buffer 45 and an output buffer 46, respectively. Reference numeral 45 is connected to the first memory group 6 as the memory data 37, and 46 is connected to the second memory group 7 as the memory address 38.

When the main body using the memory card accesses the memory card, a fast signal such as a clock signal is generally input / output to / from the card data 4. At this time, the operating current of the first memory group 6 or the second memory group 7 and the operating current of the control circuit 36 largely depend on the terminal capacitance connected to the operating memory data 37 or 38. When the terminal capacitance increases, the operating current increases dramatically.

In the embodiment of the present invention, since the card data is divided into a plurality of pieces and connected to the memory as the memory data, the terminal capacity of the memory data is smaller than that of connecting the card data to the memory without dividing the card data. .

The operating currents of the output buffers 45 and 46 greatly depend on their operating speeds.

As the operating speed increases, the operating current increases dramatically.

In the embodiment of the present invention, since the output buffers 45, 46 divided into a plurality are controlled by the independent control lines 43, 44, the signals of the output buffers connected to the unread memory groups are fixed. Operating current does not flow.

[0040]

As described above, according to the present invention, by dividing the address line or the data line of the memory card into a plurality of blocks and connecting them to the memory, the terminal capacity inside the memory card can be suppressed to a low level, and the memory card Operating current can be reduced.

Further, among the divided address lines or data lines, by fixing the address line or data line connected to the memory group which is not operating, the output connected to the memory group which is not read. The signal of the buffer can be fixed and the operating current can be prevented from flowing.

This has the effect of reducing the current consumption of the memory card.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory card of the present invention in which an address line input to the memory card is divided into a plurality of blocks by a logic circuit and the divided address lines are connected to the memory. .

In the memory card of the present invention, an address line input to the memory card is divided into a plurality of blocks by a logic circuit, the divided address lines are connected to the memory, and a non-operating memory group is formed. Block diagram of a memory card when the address line of FIG.

FIG. 3 is a block diagram of the memory card of the present invention in which a data line connected to the memory card is divided into a plurality of blocks by a logic circuit, and the divided data lines are connected to the memory.

In the memory card of the present invention, a data line connected to the memory card is divided into a plurality of blocks by a logic circuit, the divided data lines are connected to the memory, and a memory group not operating The block diagram of a memory card when fixing a data line with a logic circuit.

FIG. 5 is a block diagram of a conventional memory card.

[Explanation of symbols]

 1 Connector 2 Card Address 3 Card Control 4 Card Data 5 Logic Circuit 6 First Memory Group 7 Second Memory Group 8 Input Buffer 9 Output Buffer 10 Output Buffer 11 Control Circuit 12 Memory Address 13 Memory Address 14 Memory Control 15 Memory Control 16 memory data 21 gate 22 gate 23 control line 24 control line 31 output buffer 32 memory address 33 control circuit 34 memory control 35 memory control 36 control circuit 37 memory data 38 memory data 41 gate 42 gate 43 control line 44 control line 45 output buffer 46 Output Buffer 51 Memory Group 52 Control Circuit 53 Memory Address 54 Memory Control 55 Memory Data

Claims (4)

[Claims] 1. In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, an address line input to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. A memory card, characterized in that an address line is connected to the memory. 2. In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, an address line input to the memory card is divided into a plurality of blocks by the logic circuit, and the division is performed. A memory card, wherein an address line is connected to the memory, and an address line to a memory group that is not operating is fixed by the logic circuit. 3. In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, a data line connected to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. A memory card, characterized in that a data line is connected to the memory. 4. In a memory card including at least a logic circuit for controlling a memory and a plurality of memories, a data line connected to the memory card is divided into a plurality of blocks by the logic circuit, and the blocks are divided. A memory card, wherein a data line is connected to the memory, and the data line to a memory group that is not operating is fixed by the logic circuit.