KR100299179B1 - High-speed semiconductor memory device - Google Patents

Abstract

PURPOSE: A high-speed semiconductor memory device is provided to improve an operating speed by rearranging a color register from an interface block to a read/write block so as to reduce power consumption at a block write operation. CONSTITUTION: A memory cell block(30) includes a memory cell and a sense amplifier for reading and amplifying data stored in the memory cell. An input/output line(io) transfers data read output from the memory cell block(30) and data to be written to the memory cell block(30). A read/write block(20) reads data from the memory cell block(30) to transfer the read data to the input/output line, or writes data from the outside to the memory cell block through the input/output line. A global input/output line(gio) transfers data read out from the memory cell block, or data to be written to the memory cell block. An interface block(10) transfers external data to the global input/output line, or data on the global input/output line to the outside. A color register(40) is disposed in the read/write block(20), and temporarily stores data, used frequently, among externally supplied data in order to use at a block write operation.

Description

High speed action semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast-acting semiconductor memory device, and more particularly, when a block write operation is performed by changing the position of a color register from an interface block to a read / write block. The present invention relates to a fast-acting semiconductor memory device capable of improving power consumption by reducing power consumption.

According to the present invention, all memories such as DRAM having block write function, Synchronous Graphics RAM (SGRAM), Video RAM (VRAM), Window RAM (WRAM), etc. It can be applied to an element and used.

FIG. 1 is a block diagram briefly showing the structure of a conventional semiconductor memory device in which the color register 4 is placed in the interface block 1.

As shown in FIG. 1, a semiconductor memory device may be divided into three parts.

First, a memory cell block 3 including a memory cell and sense amplifiers reading data stored in the cell, and reading data from the memory cell block 3 or reading the data from the memory cell block ( 3) a read / write block 2 for writing data to the data, and a part for interfacing with the outside of the memory integrated circuit to receive external data or to output data to the outside. It consists of an Interface Block (1).

The line connecting the interface block 1 and the read / write block 2 is called a global input / output bus line (gio), and the read / write block 2 and the memory cell block 3 are referred to as global input / output bus lines (gio). ) Is called an input / output line (io). In a conventional semiconductor memory device, when performing a block write operation, external data is first transferred to the interface block 1 where the color register 4 is located, and then the data is transmitted through a global input / output bus line (gio). The read / write block 2 was transferred to the memory cell block 3 from the read / write block 2 to the memory cell block 3 through an input / output line.

However, in the conventional semiconductor memory device configured as described above, since the global input / output bus lines (gio) are shared by a plurality of read / write blocks 2, the bus line length is long and the number of transistors connected thereto is large. The load capacitor had a big disadvantage. Therefore, when performing the block write operation, when load data is loaded on the global I / O bus line with a large load capacitor, a lot of power is consumed. When the same data is input, the data from the interface block 1 to the read / write block 2 is In this process, there is a problem in that a delay occurs in time to slow down the operation speed of the entire memory device.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to place a color register from the interface block to the read / write block, thereby increasing the operation speed by reducing power consumption during block write operation. It is to provide a semiconductor memory device.

1 is a block diagram of a conventional semiconductor memory device in which a color register is placed in an interface block.

2 is a block diagram of a semiconductor memory device according to an embodiment of the present invention in which a color register is placed in a read / write block.

3 is a detailed block diagram of the lead / light block shown in FIG.

<Description of the symbols for the main parts of the drawings>

10: interface block 20: lead / light block

30: memory cell block 40: color register

50: lead block 60: light block

In order to achieve the above object, a high-speed semiconductor memory device according to the present invention comprises a memory cell block consisting of a memory cell and sense amplifiers for reading and amplifying data stored in the memory cell, and the data from the memory cell block. An input / output line for transmitting data to read or write data to the memory cell block, a read block for reading data stored in the memory cell block and transmitting the data to the input / output line, and data input from an external device and loaded on the input / output line A write block for writing to the memory cell block, a global input / output bus line for transferring data read from the memory cell block by the read block or data to be written to the memory cell block, and external data. Take the global I / O bus An interface block which transmits data to a line or outputs data carried on the global I / O bus line to the outside, and data frequently used among data input from the outside through the interface block connected between the global I / O bus line and the light block. It is characterized by including a color register to temporarily store for use in the block write operation.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a semiconductor memory device according to the present invention, which includes a memory cell block 30 including a memory cell and sense amplifiers for reading and amplifying data stored in the memory cell, and the memory cell block 30. Input / output line (io) for transmitting data to read data from or writing data to the memory cell block (30), and data stored in the memory cell block (30) for transmission to the input / output line (io) Or a read / write block 20 that writes data input from the outside to the memory cell block 30 through the input / output line, and transfers data read from the memory cell block 30 or the memory cell block ( A global input / output bus line (gio) for transmitting data to be written to 30) and external data to the global input / output bus line (gio). An interface block 10 for transmitting or outputting data contained in the global input / output bus line (gio) to the outside, and among the data inputted from the outside through the interface block 10 and disposed in the read / write block 20. And a color register 40 which temporarily stores frequently used data for use in a block write operation.

For the block write operation, first, data input from the outside is transmitted to the global I / O bus line through the interface block.

The data loaded on the global input / output bus line gio is then stored in the color register 40 in the read / write block 20. This series of operations is called a "load color register".

After that, if the data again inputted is the same as the data previously input, since the data is already stored in the color register, the data in the color register is transferred to the input / output line io as it is, and is transferred to the memory cell block 30. It is not necessary to repeat the above operation since it is necessary to write.

In addition, when the memory cell block 30 is classified into bank units, since the read / write block 20 is connected to each bank, the color register 40 may be used for each bank.

Therefore, flexibility and freedom in memory use during block write operations can be improved.

FIG. 3 shows a detailed block diagram of the read / write block 20 shown in FIG. 2, in which the "lcr" signal is a command signal for storing data carried on the global input / output bus line (gio) in the color register 40. As shown in FIG. The "normal_write" signal is a signal for sending data on the global input / output bus line (gio) to the memory cell block 30, and the "color register_write" signal is used to send data in the color register 40. The signal is sent to the memory cell block 30.

The operation of the semiconductor memory device of the present invention configured as described above will be described with reference to the drawings.

For the block write, the first data input from the outside by the "lcr" signal is first stored in the color register 40 in the read / write block 20 through the global input / output bus line gio. The data stored in this manner is transferred to the memory cell block 30 through the input / output line io by the "color register_write" signal and written to the memory cell block 30. When the next input data is different from the data stored in the color register 40, the data transferred through the global input / output bus line gio is transferred directly to the input / output line io through the write block 50 to the memory cell. If the next data inputted from the outside is the same as the data stored in the color register 40, the content stored in the color register 40 is inputted and output through the write block 50 as it is. On line io.

As described above, the fast-acting semiconductor memory element in which the color register according to the present invention is placed in the read / write block 20 is arranged by placing the color register 40 in the read / write block 20. When the same data as that stored in 40 is inputted, the inputted data does not go through the global I / O bus line (gio), but immediately transfers the data of the color register 40 to the memory cell block 30 to write. This eliminates the large power dissipation in the global I / O bus lines (gio), reducing the delay in time, resulting in greater margin in timing design for block writes.

In addition, when the memory cell blocks are classified into bank units and color registers are disposed in each bank, flexibility and freedom in using the memory can be improved.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (2)

A memory cell block comprising a memory cell and sense amplifiers for reading and amplifying data stored in the memory cell, and an input / output line for transmitting data to read data from or write data to the memory cell block And a read block for reading data stored in the memory cell block and transmitting the data to the input / output line, a write block for writing data input from the outside to the memory cell block through the input / output line, and a memory by the read block. A global input / output bus line for transferring data read from a cell block or writing data to the memory cell block to the write block, and receiving external data and transmitting the data to the global input / output bus line or the global input / output bus line On An interface block that outputs data to the outside, and is connected between the global I / O bus line and the write block to temporarily store data frequently used among the data input from the outside through the interface block for use in the block write operation A high speed acting semiconductor memory device comprising a color register. A plurality of banks in which a memory cell block including a memory cell and sense amplifiers for reading and amplifying data stored in the memory cell is connected in a predetermined number unit, and reading data from or writing data to the memory cell block; Input / output lines for transferring data, a plurality of read blocks connected to each bank to read data stored in memory cell blocks of each bank, and transmitted to the input / output lines, and data input from outside connected to each bank. A write block written to the memory cell block of each bank through the input / output line, a global input / output bus line transferring data read from a bank by the read block or data to be written to the bank, and external The global I / O bus receiving data An interface block that transmits data to a line or outputs data on the global input / output bus line to an external device, and is connected between the global input / output bus line and the respective write block to be frequently used among data input from the outside through the interface block. A high speed acting semiconductor memory device comprising a plurality of color registers for temporarily storing data for use in a block write operation.

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