JPH11143820A - Data transferring system and bus circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transferring system executing both of a random access system and a burst access system while satisfying both of access efficiency and the using efficiency of a signal line. SOLUTION: The number of all the signal lines is made not smaller than a number required for random access and the number of all the signal lines includes respectively prescribed signal line numbers of high order bus and low order bus. In the case of transferring data by the random access system, a switching device 10 is switched by a control signal from a control signal generator 20 to transfer an address signal through the high order bus and to transfer a data signal through the low order bus. In the case of transferring data by the burst access system, the switching device 10 is switched by a control signal from the control signal generator 20 to halve the data signal into high order and low order data signals to transfer a head address signal and the high order data signal through the high order bus and to transfer the low order data signal through the low order bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus circuit and a data transfer method for performing data transfer using the bus circuit.

[0002]

2. Description of the Related Art In general, two types of data transfer systems for performing data transfer using a bus circuit, a random access system and a burst access system, are known.

In the random access system, a bus circuit having an address signal line and a data signal line is used. Then, an address to be accessed is transmitted through an address signal line, and data to be read / written from or to the address is transmitted through a data signal line. In the random access method, an arbitrary address can be designated each time an access is performed. Therefore, the access procedure is the same regardless of whether the address is continuous over a plurality of accesses or a random address for each access.

On the other hand, the burst access system uses a bus circuit having a signal line shared for address signals and data signals. Then, first, the first address to be accessed is specified, and thereafter, a predetermined number of continuous data are read and written. In the burst access method, the access efficiency indicating the amount of data transfer per access is higher as the amount of transfer performed in one burst access transfer is larger. For this reason, in the burst access method, if an access is made to a random address in which only one data transfer can be performed in one access, access efficiency is extremely poor.

[0005] The data transfer method depends on the application.
It may be sufficient if only one of the random access scheme and the burst access scheme is implemented. But,
Usually, both access methods are often required. A data transfer method for realizing both access methods in this way is disclosed in Japanese Patent Application Laid-Open Nos. 8-153030 and 5-146361. The former discloses a shared memory device in which address ranges to be accessed by both access methods are separated and simultaneously accessible. In the latter, a system for transferring data between computers by both methods is disclosed.

[0006]

Here, consider the signal lines physically required to realize each of the random access system and the burst access system.

[0007] The random access method requires two types of signal lines, an address signal line and a data signal line. Therefore, for example, when each signal radiation of the address signal and the data signal is 32 bits, a total of 64 signal lines are required. Although a method in which the address signal line and the data signal line are made common, that is, a method in which the same signal line is alternately used for the address signal and the data signal can be considered, this method is a random method in the burst access method described above. This is the same as when accessing. That is, the access efficiency is extremely poor.

On the other hand, in the burst access method, it is not necessary to separately prepare an address signal line and a data signal line. Therefore, if each signal width of the address signal and the data signal is 32 bits, for example, only 32 signal lines are required.

On the other hand, in order to realize both the random access method and the burst access method, the number of signal lines must be equal to the number of signal lines of the random access method which is required in a large number, for example, 64 signal lines. It is necessary to prepare. However, when performing burst access,
Only half of the 32 are used, and the remaining 32 are wasted.

In other words, the conventional data transfer system and bus circuit for realizing both the random access system and the burst access system cannot satisfy both the access efficiency and the use efficiency of the signal lines.

It is an object of the present invention to provide a data transfer system capable of performing both a random access system and a burst access system while satisfying both access efficiency and signal line use efficiency.

Another object of the present invention is to provide a bus circuit capable of performing both a random access method and a burst access method while satisfying both access efficiency and signal line use efficiency.

[0013]

According to the present invention, in a data transfer system in which data can be transferred by a random access method and a burst access method using a bus circuit, the bus circuit has a total number of signal lines. In addition to the number required for random access, the total number of signal lines includes an upper bus and a lower bus of a predetermined number of signal lines, respectively. While transferring the address signal,
When the data signal is transferred on the lower bus and the data transfer is performed by the burst access method, the data signal is divided into an upper data signal and a lower data signal, and the head address signal and the upper data signal are transferred on the upper bus. In addition, a data transfer method characterized by transferring a lower data signal through a lower bus is obtained.

According to the present invention, the data transfer system in which the upper bus and the lower bus have the same number of signal lines is obtained.

According to the present invention, there is further provided an address input terminal for inputting an address signal, an upper data input terminal for receiving an upper data signal, and an upper bus output terminal connected to the upper data bus. When the data transfer is performed by the access method, the address input terminal is connected to the upper bus output terminal. When the data transfer is performed by the burst access method, the address input terminal is connected to the upper bus output terminal. The data transfer system provided with a switch for connecting the upper data input terminal and the upper bus output terminal is obtained.

According to the present invention, a mode signal for discriminating between a random access method and a burst access method is input, and an access method is determined based on the mode signal to perform data transfer by the random access method. The switch controls the address input terminal and the upper bus output terminal to be connected, while the switch switches the address input terminal and the upper bus output terminal when performing data transfer in a burst access method. After the connection for a predetermined time, the data transfer system is provided with a control signal generator for outputting a control signal for controlling connection between the upper data input terminal and the upper bus output terminal to the switch. .

According to the present invention, further, in a bus circuit capable of transferring data in each of the random access system and the burst access system, the bus circuit has a total number of signal lines equal to or greater than the number required for random access, and Each includes an upper bus and a lower bus of a predetermined number of signal lines, and when performing data transfer by a random access method, while transferring an address signal on the upper bus,
When the data signal is transferred on the lower bus and the data transfer is performed by the burst access method, the data signal is divided into an upper data signal and a lower data signal. , And a lower data signal is transferred on a lower bus.

According to the present invention, the bus circuit according to claim 5, wherein the upper bus and the lower bus have the same number of signal lines.

According to the present invention, there is further provided an address input terminal for inputting an address signal, an upper data input terminal for receiving an upper data signal, and an upper bus output terminal connected to the upper data bus. When the data transfer is performed by the access method, the address input terminal is connected to the upper bus output terminal. When the data transfer is performed by the burst access method, the address input terminal is connected to the upper bus output terminal. The bus circuit having a switch for connecting the upper data input terminal and the upper bus output terminal is obtained.

According to the present invention, when a mode signal for identifying a random access method and a burst access method is input, an access method is determined based on the mode signal, and data transfer is performed by the random access method. The switch controls the address input terminal and the upper bus output terminal to be connected, while the switch switches the address input terminal and the upper bus output terminal when performing data transfer in a burst access method. After a predetermined period of time, the bus circuit having a control signal generator for outputting a control signal for controlling connection between the upper data input terminal and the upper bus output terminal to the switch is obtained.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a bus circuit according to an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the present bus circuit is a bus circuit capable of transferring data in each of a random access system and a burst access system. The bus circuit has a total number of signal lines equal to or greater than that required for random access, and the total number of signal lines is equal to the number of signal lines,
For example, it has an upper bus and a lower bus having 32 signal lines. When data transfer is performed by the random access method, an address signal is transferred on an upper bus and a data signal is transferred on a lower bus. On the other hand, when performing data transfer by the burst access method, the data signal is divided in advance into an upper data signal, which is an upper part thereof, and a lower data signal, which is a lower part thereof. At the same time, the lower data signal is transferred on the lower bus.

The bus circuit further includes an address input terminal 11a to which an address signal is input, an upper data input terminal 11b to which an upper data signal is input, and an upper bus output terminal 12 connected to the upper data bus. When the data transfer is performed by the random access method, the address input terminal 11a is connected to the upper bus output terminal 12, while when the data transfer is performed by the burst access method, the address input terminal 11a is connected to the upper bus output terminal 12. After that, there is provided a switch 10 for connecting the upper data input terminal 11b and the upper bus output terminal 12.

Further, in the bus circuit, a mode signal for identifying the random access method and the burst access method is input from the mode input signal 21, and the access method is determined based on the mode signal, and the random access method is used. When data transfer is performed, the switch 10 controls the connection between the address input terminal 11a and the upper bus output terminal 12, while when performing data transfer in a burst access method, the switch 10 is connected to the address input terminal 11a and the upper bus output terminal 12. A control signal generator for outputting a control signal for controlling the connection between the upper data input terminal and the upper bus output terminal to the switch after connecting the bus output terminal for a predetermined time; I have. Control signal generator 2
0 is the mode output terminal 22a and the address output terminal 22a.
b.

Further, this bus circuit has a lower data input terminal 31 to which a lower data signal is input, and a lower bus output terminal 32 connected to the lower data bus. In this example, the lower data input terminal 31 and the lower bus output terminal 32
Is a through circuit.

Next, a data transfer method according to an embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 1, in this data transfer method,
In the case of a random access write operation using the bus circuit shown in FIG. 1, a logical value “0” as a mode signal is given to the control signal generator 20 through the mode input terminal 21 to access the address input terminal 11a. An address signal indicating an address is input, and a data signal is input to the lower data input terminal 31. At this time, FIG.
As shown in (a), the data signal whose address signal is output to the upper bus by the switch 10 is output from the lower data output terminal 32 to the lower bus.

Assuming that the signal width of the address and data is 32 bits, as shown in FIG. 2A, the address signal and the data signal are simultaneously output to half of all the buses, and random access can be performed.

On the other hand, in the case of a burst access write operation, the head address of the address to be accessed is input to the address input terminal 11a, and the lower data input terminal 3
1, a lower data signal to be written is input, and an upper data signal to be written is input to the upper data input terminal 11b. When a logical value "1" as a mode signal is given to the control signal generator 20 through the mode input terminal 21, the control signal generator 20 first switches so that the switch 10 outputs an address signal, and FIG. As shown in (1), while the head address signal is output to the upper bus, an address signal is also output to the bus through the address output terminal 22b to notify that the head address value is currently being output.

Thereafter, the control signal generator 20 switches the switch 10
Is switched to output the upper data signal, and the upper data signal is output to the upper bus. The lower data signal is output to a lower bus.

Thereafter, when data to be sequentially written is input to the lower data input terminal 31 and the upper data input terminal 11b, the data is output to the upper and lower buses, respectively. In this case, as shown in FIG. 2B, data is continuously output using the entire bus width, and high-speed burst transfer can be performed. When the transfer length of the burst access is long, the data width is twice as large as in the case of the random access, so that the data transfer speed is almost double.

[0032]

According to the data transfer system and the bus circuit of the present invention, random access can be performed efficiently, and at the time of burst access, a signal line is effectively used to obtain a transfer speed almost twice that of random access. Can be. That is, the data transfer system and the bus circuit according to the present invention can perform both the random access system and the burst access system while satisfying both the access efficiency and the use efficiency of the signal lines.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a bus circuit according to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams for explaining a data transfer method according to an embodiment of the present invention, wherein FIG. 2A shows a signal line use situation at random access, and FIG. 2B shows a signal line use situation at burst access; Is shown.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Switch 11a Address input terminal 11b Upper data input terminal 12 Upper bus output terminal 20 Control signal generator 21 Mode input terminal 22a Mode output terminal 22b Address output terminal 31 Lower data input terminal 32 Lower bus output terminal

Claims (8)

[Claims] 1. In a data transfer method capable of transferring data by a random access method and a burst access method using a bus circuit, the bus circuit has a total number of signal lines equal to or more than that required for random access. The total number of signal lines includes an upper bus and a lower bus of a predetermined number of signal lines, respectively. When data transfer is performed by a random access method, an address signal is transferred by the upper bus and the lower bus is transferred. When the data signal is transferred by the burst access method, the data signal is divided into an upper data signal and a lower data signal, and the top address signal and the upper data signal are transferred by the upper bus. A data transfer method characterized by transferring a lower data signal through a lower bus. 2. The data transfer method according to claim 1, wherein the upper bus and the lower bus have the same number of signal lines. 3. An address input terminal to which an address signal is input, an upper data input terminal to which an upper data signal is input, and an upper bus output terminal connected to the upper data bus, wherein data is transferred by a random access method. When performing the data transfer, the address input terminal is connected to the upper bus output terminal. When performing the data transfer by the burst access method, the address input terminal is connected to the upper bus output terminal. 3. The data transfer method according to claim 1, further comprising a switch for connecting the output terminal to the upper bus output terminal. 4. A mode signal for discriminating between a random access method and a burst access method is inputted, an access method is determined based on the mode signal, and when the data transfer is performed by the random access method, the switch is used. While controlling so as to connect the address input terminal and the upper bus output terminal, the switch connects the address input terminal and the upper bus output terminal for a predetermined time when performing data transfer by a burst access method. 4. The data transfer method according to claim 3, further comprising a control signal generator for outputting a control signal for controlling connection between the upper data input terminal and the upper bus output terminal to the switch. 5. A bus circuit capable of transferring data in each of a random access system and a burst access system, wherein the bus circuit has a total number of signal lines equal to or greater than a number required for random access, and the total number of signal lines includes a predetermined signal. When data transfer is performed by a random access method including an upper bus and a lower bus having the same number of lines, an address signal is transferred on the upper bus, and a data signal is transferred on the lower bus. When data transfer is performed by the, the data signal is divided into the upper data signal and the lower data signal, and the top address signal and the upper data signal are transferred on the upper bus, and the lower data signal is transferred on the lower bus. A bus circuit characterized by: 6. The bus circuit according to claim 5, wherein the upper bus and the lower bus have the same number of signal lines. 7. An address input terminal to which an address signal is input, an upper data input terminal to which an upper data signal is input, and an upper bus output terminal connected to the upper data bus, wherein data transfer is performed by a random access method. When performing the data transfer, the address input terminal is connected to the upper bus output terminal. When performing the data transfer by the burst access method, the address input terminal is connected to the upper bus output terminal. 7. The bus circuit according to claim 5, further comprising a switch for connecting the output terminal to the upper bus output terminal. 8. A mode signal for discriminating between a random access method and a burst access method is input, the access method is determined based on the mode signal, and when the data transfer is performed by the random access method, the switch is used. While controlling so as to connect the address input terminal and the upper bus output terminal, the switch connects the address input terminal and the upper bus output terminal for a predetermined time when performing data transfer by a burst access method. 8. The bus circuit according to claim 7, further comprising a control signal generator for outputting a control signal for controlling connection between the upper data input terminal and the upper bus output terminal to the switch.