JPH05233482A - Data transfer system - Google Patents

Abstract

PURPOSE:To enable the efficient use of a prefetch data buffer and highly reliable data transfer. CONSTITUTION:This system is equipped with a channel controller having a data buffer control flag group 305 wherein the use state of the prefetch data buffer 302 whose data holding area is divided into unit areas is recorded, a channel control circuit 301 which extracts data transfer performance corresponding to a transfer-destination input/output device from a transfer performance table 308 and sets the data buffer control flag group 305 corresponding to the data transfer performance and also corresponding to the data holding area of the prefetch data buffer 302, and a prefetch data buffer control circuit 303 which specifies the addresses of the prefetch data buffer 302 regarding the transfer-destination input/output device as write and read addresses of memory reply data by referring to the data buffer control flag group 305.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of channel devices to which input / output devices are respectively connected, and memory reply data read from a storage device, to which a transfer destination is designated by an input / output command for instructing data transfer. The present invention relates to a data transfer system having a channel controller for transferring to an output device.

[0002]

2. Description of the Related Art A conventional data transfer system is shown in FIG.
Will be described.

In the data transfer system shown in FIG. 3, n channel devices 900 are subordinate to a channel control device 800.
_{1 to} 900 _n are connected, and the input / output device 10 is connected to each of the channel devices 900 _{1 to} 900 _n.
00 _{1 to} 1000 _n are connected.

Each of the channel devices 900 _{1 to} 900 _n
Have the same configuration, and the main storage device 70
0 reply data from is stored, and a prefetch data buffer 903 ₁ ~903 _n fixed-size.

In such a data transfer device, when data transfer is performed between the main memory device 700 and each of the input / output devices 1000 _{1 to} 1000 _n , an input / output instruction is issued from the central processing unit 600 and the input / output is performed. Upon receiving the instruction, the channel control device instructs the channel device 900 to which the input / output device designated by the input / output command is connected to execute data transfer. The channel device 900 instructed to execute the data transfer makes a memory request within the capacity of the prefetch data buffer 903, and the input / output device 10
The transfer data to be transferred to 00 is prepared. Sufficient transfer data to start data transfer is prefetched data buffer 9
I / O interface control circuit 9
04 transfers the transfer data to the input / output device 1000. When the data transfer is completed, the channel device 900 notifies the channel control device 800, and the notified channel control device 800 sends to the central processing unit 600 an end report indicating the end of the data transfer related to the input / output command. Then, the operation is ended and the operation of the channel control device 800 is ended.

[0006]

However, in the above-described conventional data transfer system, the prefetch data buffer provided inside each channel device has a fixed size, and the input / output devices having different transfer performances are subordinate to the channel device. If you connect to the I / O device, the pre-fetch data buffer required for data transfer by the I / O device with high transfer performance will be prepared. There is a problem that waste occurs. In addition, since the data transfer system in recent years has become faster and faster and the combination of input / output devices having high transfer performance and input / output devices having low transfer performance cannot be avoided, there is a problem that the waste of the prefetch data buffer is also increased. Further, if a prefetch data buffer of a channel device fails, the channel device becomes unusable.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and the prefetch data buffer can be used efficiently, and highly reliable data transfer can be performed.
It is intended to provide a data transfer system.

[0008]

According to the present invention, a plurality of channel devices to which input / output devices are respectively connected and memory reply data read from a storage device are designated by an input / output command for instructing data transfer. In a data transfer system having a channel control device for transferring to a transfer destination input / output device, the channel control device has prefetched data in which a data holding area is divided into a plurality of unit areas and a spare unit area for occurrence of a failure is provided. A buffer, and in-use information indicating whether or not the memory reply data is stored in the unit area, corresponding to each unit area of the prefetch data buffer, and memory reply data stored in the unit area. I / O information indicating the transfer destination I / O device,
When a failure occurs in the unit area, failure information indicating use prohibition of the unit area is recorded, and a data buffer management flag group including a plurality of data buffer management flags and data transfer performance of each of the input / output devices are recorded. A transfer performance table stored in advance and a data transfer performance corresponding to the transfer destination input / output device when the input / output command is issued, are extracted from the transfer performance table, and the prefetch corresponding to the data transfer performance is extracted. When the used bit and the input / output device information are set in the data buffer management flag corresponding to the data holding area of the data buffer, and the failure occurs in the prefetch data buffer unit area being used, the data buffer management of the spare unit area is performed. A channel control circuit that sets a bit in use and input / output device information in a flag,
Referring to the data buffer management flag group, an address indicating a unit area of the prefetch data buffer relating to the data buffer management flag in which a busy bit is set for the transfer destination input / output device of the memory reply data,
A prefetch data buffer control circuit for designating a write address of the memory reply data to the prefetch data buffer and also for designating a read address for reading the memory reply data already held by the prefetch data buffer; By referring to the memory reply data read from the buffer, it is checked whether or not the memory reply data is normal, and if an error occurs, the memory reply data is related to the unit area corresponding to the read address read from. And an error detection circuit for recording the failure information in a data buffer management flag, wherein each data buffer management flag of the data buffer management flag group of the channel control device has a failure in a unit area of the prefetch data buffer. At the occurrence of Fault information indicating the disabling of the unit region is fault bit is provided to be set, further,
The channel control device refers to the memory reply data read from the prefetch data buffer, checks whether the memory reply data is normal, and if an error occurs, the memory reply data is read. A case where an error detection circuit for setting the fault information in a data buffer management flag relating to the unit area corresponding to a read address is provided, and a preparatory data buffer of the channel control device is provided with a spare unit area for occurrence of a fault. The channel control circuit of the channel control device is
In some cases, when a failure occurs in the prefetch data buffer unit area being used, a bit in use and input / output device information are set in the data buffer management flag of the spare unit area.

[0009]

According to the data transfer system of the present invention, the data holding area of the prefetch data buffer provided in the channel controller is divided and used in a plurality of amounts according to the transfer performance of the input / output device for data transfer. The prefetch data buffer can be efficiently used even in a system in which I / O devices having different transfer performances are mixed.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the data transfer system of the present invention.

In the data transfer system of this embodiment, a central processing unit 100, a main storage unit 200, a channel control unit 300, and n channel units 400 ₁ to which input / output units 500 _{1 to} 500 _n are connected respectively. To 400 _n , the main storage device 200 and the input / output device 500 are provided.
Data is transferred between _{1 and} 500 _n .

The central processing unit 100 is a device for performing arithmetic processing, and when performing input / output processing, the channel control device 3 is used.
Input / output instruction 1 is issued to 00. In addition, when the channel control device 300 is initialized, the channel control device 30
The transfer performance information 17 about all the input / output devices connected under the control of 0 is given to the channel control device 300.

The main storage device 200 is a central processing unit 100.
And the channel control device 300, the memory reply 4 of 1 word is transmitted for each memory request 3 issued from the channel control device 300.

The channel control device 300 controls each of the channel devices 400 _{1 to} 400 _n in accordance with the input / output instruction 1 issued by the central processing unit 100 so that the main memory device 200 and the input / output devices 500 _{1 to} 500 _n are connected to each other. Is a device for transferring data.

The channel devices 400 _{1 to} 400 _n are devices for controlling the interface with the input / output devices 500 _{1 to} 500 _n, and the main storage device 200 and the input / output devices 500 _{1 to} 500 _n are instructed by the channel control device 300. Data transfer between.

Here, the configuration of the channel control device 300 will be described.

The channel control device 300 of this embodiment comprises a channel control circuit 301, a prefetch data buffer 302, a prefetch data buffer control circuit 303, a data transfer control circuit 304, a data buffer management flag group 305, a data input register 306 and a data output. Register 307, input / output device transfer performance table 308, and error detection circuit 30
9 and 9.

The input / output device transfer performance table 308 stores transfer performance information 17 of each of the input / output devices 500 _{1 to} 500 _n transferred from the central processing unit 100 at the time of initial setting.

The prefetch data buffer 302 is a buffer for storing transfer data read from the main storage device 200 prior to data transfer, and is designated by a read address 15 and a write address 16 issued by the prefetch data buffer control circuit 303. The transfer data is read and written in the unit area.

The data buffer management flag group 305 corresponds to one prefetch data buffer management flag per unit area of the prefetch data buffer 302. Here, each prefetch data buffer management flag of the data buffer management flag group 305 will be described with reference to FIG.

FIG. 2 is a diagram showing the relationship between the prefetch data buffer management flag and the unit area of the prefetch data buffer 302.

The prefetch data buffer management flag of this embodiment includes a fault bit indicating whether or not there is a fault in the unit area of the prefetch data buffer 302 and a busy bit indicating whether or not the unit area is in use. , And a channel device number indicating the channel device in use.

When both the fault bit and the in-use bit are "0", it indicates that the corresponding unit area of the prefetch data buffer 302 is available. Further, the prefetch data buffer 302 has a spare unit area for occurrence of a failure, and the spare unit area is normally used when the failure occurs.
It is set to (disabled state). The error detection circuit 309 sets the error detection information 20 (“1”) in the failure bit when a failure occurs in the unit area of the prefetch data buffer 302. This fault bit is a flag that is not reset once set.

The channel control circuit 301 is a circuit for decoding and processing the input / output instruction 1 from the central processing unit 100, and the designated input / output apparatus information 18 indicating the input / output apparatus designated by the input / output instruction 1. The transfer performance information 19 of the input / output device is read from the input / output device transfer performance table 308 based on the
2. Secure the used unit area of 2.

To secure the used unit area of the prefetch data buffer 302, the channel control circuit 301
The usage status (usage status display signal 10) of the prefetch data buffer 302 is monitored with reference to the data buffer management flag group 305, and when the input / output instruction 1 is executed, the prefetch data is read from the number of words of the prefetch data required. The required number of unit areas of the buffer 302 is calculated. Then, the channel device number and the in-use bit of the channel device to be used are set in the prefetch data buffer management flag corresponding to the required unit area. In addition, the channel control circuit 301
Gives a data transfer instruction 8 to the data transfer control circuit 304. Further, after securing the use unit area of the prefetch data buffer 302, the transfer start instruction 9 is sent to the corresponding channel device, and when the data transfer of the transfer amount designated by the input / output instruction 1 is completed, the central processing is performed. The end report 2 is sent to the device 100.

The prefetch data buffer control circuit 303 is
With reference to the data buffer management flag group 305, the prefetch data buffer 30 is stored according to the usable unit area.
A read address 15 and a write address 16 are designated for 2. Read address 15 and write address 16
Is transmitted after receiving the memory reply reception signal 21 from the data input register 306. Further, the channel device corresponding to the input / output device for transferring the data, that is, the channel device number recorded in the data buffer management flag in use is sent to the data output register 307 as the channel device number information 11. Further, when the usage status display signal 10 indicates that the unit area of the prefetch data buffer 302 assigned to the input / output device for transferring data is full, the request transfer signal 13 is sent to the data transfer control circuit 304. Is output.

The data transfer control circuit 304 is a circuit for accessing the main memory device 200 in accordance with the data transfer instruction 8 from the channel control circuit 301. The prefetch data buffer control circuit 303 outputs a request inhibit signal 13 for each channel device. Until then, the memory request 3 for each channel device is continuously sent to the main memory device 200. Also, every time the memory request 3 is transmitted, the request transmission signal 14 for each channel device is transmitted to the prefetch data buffer control circuit 303.

The data input register 306 is a register for writing the memory reply data 4 from the main storage device 200 into the prefetch data buffer 302. When the memory reply data 4 is received, the prefetch data buffer control circuit 303 receives the data. The memory reply reception signal 21 is transmitted to the memory.

The data output register 307 transfers the data read from the prefetch data buffer 302 to the channel device number information 1 from the prefetch data buffer control circuit 303.
This is a register for sending to the channel device designated by 1. When the data sending is completed, the data sending completion signal 12 is sent to the prefetch data buffer control circuit 303.

The error detection circuit 309 is a circuit for detecting a fault by referring to the read data 6 read from the prefetch data buffer 302. Once the fault is detected, the fault address area of the prefetch data buffer 302 is read from the read address 15. The determination is made, the error detection signal 20 is issued, and "1" is set to the failure bit of the data buffer management flag group 305 corresponding to the failure occurrence area. Also, when a failure occurs,
An error occurrence report 23 is sent to the central processing unit 100, and a data transfer stop signal 22 is sent to the channel devices 400 _{1 to} 400 _n .

Next, the operation of this embodiment will be described.

First, the central processing unit 100 gives the channel control device 300 all the transfer performances of the input / output devices connected under the control of the channel control device 300 at the time of initialization.

After that, when an input / output command is issued from the central processing unit 100, the channel control device 300 decodes the input / output command 1 by the channel control circuit 301 and recognizes the input / output device for data transfer. Check the transfer performance of the output device. Subsequently, the channel control circuit 301 refers to the in-use bit and the failure bit of the prefetch data buffer management flag group 305, and determines the unit area that can be used to execute the input / output instruction 1 based on the usage state of the prefetch data buffer 302. It is determined whether or not is empty. As a result, if the used unit area of the prefetch data buffer 302 required to execute the input / output instruction 1 is insufficient, the central processing unit 100 is notified that the prefetch buffer is BUSY and cannot be executed.

On the other hand, when the input / output instruction 1 can be executed,
The channel control circuit 301 sets the channel device number and the busy bit “1” in the prefetch data buffer management flag group 305.
Is set, and the unit-of-use area of the prefetch data buffer 302 necessary for executing the input / output instruction 1 is secured. Then, the channel control circuit 301 issues a transfer start instruction 9 to the channel device to which the input / output device designated by the input / output instruction 1 is connected, and also gives the data transfer instruction 8 to the data transfer control circuit 304 so that the memory Start access.

Upon receiving the data transfer instruction 8, the data transfer control circuit 304 starts sending the memory request 3 and
Every time a memory request is made, the request transmission signal 14 is sent to the prefetch data buffer control circuit 303.

Upon receiving the request transmission signal 14, the prefetch data buffer control circuit 303 refers to the prefetch data buffer management flag group 305 and allocates the memory reply data for the memory request of the input / output device during data transfer to the input / output device. Prefetched data buffer 3
When the usage unit area 02 is full, the request inhibition signal 13 is output to the data transfer control circuit 304. The data transfer control circuit 304 that has received the request inhibition signal 13 suspends the transmission of the memory request 3.

On the other hand, when the memory request 3 is accepted, the main storage device 200 for the memory request 3 is received.
The memory reply 4 is received by the data input register 306. At that time, the memory reply reception signal 21 is sent from the data input register 306 to the prefetch data buffer control circuit 303.

When the prefetch data buffer control circuit 303 receives the memory reply reception signal 21, the prefetch data buffer control circuit 303 sends out the read address 15 and the write address 16 to the prefetch data buffer 302, whereby the memory reply 4 becomes the memory reply data 5. , Is stored in the area designated by the write address 16, and
The data (read data 6) in the area designated by the read address 15 is read, and the data output register 307
Stored in.

When the data output register 307 receives the read data 6, the prefetch data buffer control circuit 30 receives the read data 6.
3 is sent to the channel device specified by the channel device number information 11 as transfer data 7, and when the sending is completed, the pre-fetch data buffer control circuit 303 is sent a data sending completion signal 12 notifying the completion of data output. To do.

Further, the prefetch data buffer control circuit 30
3 receives the data transmission completion signal 12 from the data output register 307 while the request inhibition signal 13 is issued, a space is available in the unit usage area of the prefetch data buffer 302 assigned to the input / output device during data transfer. Then, the transmission of the request inhibition signal 13 is stopped, and the data transfer control circuit 304 restarts the transmission of the memory request 3.

When the data transfer is completed by repeating the above operation until the transfer amount designated by the input / output instruction 1 is completed, the channel control circuit 301 outputs the end report 2 of the input / output instruction 1 to the central processing unit 100. Then, the operation of the channel control device 300 ends. Further, when the error detection circuit 309 detects an error in the read data 6 of the prefetch data buffer 302 during data transfer, the unit area of the prefetch data buffer 302 in which the failure is considered to occur from the read address 15 for the read data 6 Is determined, and the failure bit of the corresponding buffer management flag group 305 is set. At the same time, the in-use bit of the flag of the spare unit area used when a failure occurs is reset. In addition, the data transfer stop signal 22 indicating “stop of data transfer” due to an error is issued to all the channel devices 400 _{1 to} 400 _n under the control of the channel control device 300, and the prefetch data buffer 302 is sent to the central processing unit 100. Error report 2 that indicates the detection of an error
Notify 3.

Receiving the error occurrence report 23, the central processing unit 100 re-initializes the channel control device 300 and issues all the input / output instructions 1 for which the data transfer is stopped again. In this case, when the channel control device 300 secures a used unit area in the prefetch data buffer 302, the unit area in which the failure bit of the data buffer management flag group 305 is set cannot be used as in the BUSY state, and instead, The area of the spare prefetch data buffer 302 is used for. By setting the flag of the spare unit area, the reallocation is performed using the unit area of the spare prefetch data buffer 302 without using the failure area.

[0044]

As described above, the present invention has the following effects.

(1) A plurality of channel devices to which input / output devices having different transfer capacities are connected share a prefetch data buffer, and the amount of use of the prefetch data buffer depends on the transfer capability of the input / output device performing the transfer operation. Because it can be set,
It is possible to efficiently share the prefetch data buffer even with respect to input / output devices having different transfer performances, and to significantly reduce the hardware.

(2) In recent years, the speed of input / output devices has increased and competition for input / output devices with high transfer performance and low input / output devices has increased. The size of the data holding area of the data buffer is variable, so if you prepare a channel device that supports high-speed transfer, you can select I / O devices with high and low transfer performance without being conscious of the transfer performance of the channel device. You can connect freely, and there is no waste in the prefetch data buffer.

(3) Even if a part of the prefetch data buffer fails, it can be prevented that the channel device cannot be used on the spot, so that the reliability of the device is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transfer system of the present invention.

FIG. 2 is a diagram showing an example of a data buffer management flag group.

FIG. 3 is a block diagram showing an example of a conventional data transfer system.

[Explanation of symbols]

 100 central processing unit 200 main memory 300 channel controller 301 channel control circuit 302 prefetch data buffer 303 prefetch data buffer control circuit 304 data transfer control circuit 305 data buffer management flag group 306 data input register 307 data output register 308 input / output device transfer Performance table 309 Error detection circuit 400 Channel device 500 Input / output device

Claims (1)

[Claims] 1. A plurality of channel devices each having an input / output device connected thereto, and a channel for transferring memory reply data read from a storage device to a transfer destination input / output device designated by an input / output instruction instructing data transfer. In the data transfer system having a control device, the channel control device has a prefetch data buffer in which a data holding area is divided into a plurality of unit areas, and a spare unit area for occurrence of a failure is provided; Corresponding to each unit area, in-use information indicating whether or not the memory reply data is stored in the unit area, and input / output indicating a transfer destination input / output device of the memory reply data stored in the unit area Information and failure information indicating prohibition of use of the unit area when a failure occurs in the unit area are recorded. A data buffer management flag group consisting of the data buffer management flags, a transfer performance table in which the data transfer performance of each of the input / output devices is stored in advance, and the transfer destination input / output device corresponding to the input / output command when issued. Extracting the data transfer performance from the transfer performance table, and setting the in-use bit and the input / output device information in the data buffer management flag corresponding to the data holding area of the prefetch data buffer according to the data transfer performance, When a failure occurs in the prefetch data buffer unit area in use, a channel control circuit for setting a used bit and input / output device information in the data buffer management flag of the spare unit area, and the data buffer management flag group As a result, the in-use bit of the I / O device to which the memory reply data is transferred is set. An address of a unit area of Sekiru the prefetch data buffer in the data buffer management flag being,
A prefetch data buffer control circuit for designating a write address of the memory reply data to the prefetch data buffer and also designating a read address for reading the memory reply data already held by the prefetch data buffer; By referring to the memory reply data read from the buffer, it is checked whether or not the memory reply data is normal, and if an error occurs, the memory reply data is stored in the unit area corresponding to the read address read from. A data transfer system comprising: an error detection circuit for recording the failure information in a related data buffer management flag.