JPS58200323A - Input and output processor - Google Patents

Abstract

PURPOSE:To connect and control plural high-speed input and output devices which have nearly equal data transfer capability, by providing a data transfer controlling part with an FF for detecting the priority of data transfer. CONSTITUTION:An input and output processor is provided with a microprocessor 1, storage part 2, plural input and output connection parts 4 and 5, plural input and output device parts 6 and 7, and data transfer controlling part 3. The storage part 2 consists of memory elements in and out which data is written and read. The input and output device parts 6 and 7 operate at high speeds respectively and has nearly equal data transfer capability. The data transfer controlling part 3 has a priority deciding circuit provided with the FF10 for determining the priority of data transfer to control the data transfer between the storage part 2 and input and output device parts 6 and 7 through the input and output device connecting parts 4 and 5.

Description

Detailed Description of the Invention (Description of Technical Field) The present invention relates to an input/output processing device for use in an information processing device, and particularly to an input/output processing device characterized by a priority determination method for data transfer requests in the input/output processing device. Regarding equipment.

(Description of Prior Art) Conventionally, when data is transferred between a plurality of input/output device units and one storage unit in this type of input/output processing device, the data transfer priority is determined in advance. There is.

When two or more input/output devices that are high-speed and have the same data transfer capacity are connected in parallel, the probability of overrun or underrun occurring is low for input/output devices that are set to a low priority. must be maintained. Due to this necessity, a data buffer is required in the input/output device section.
There was a drawback that the amount of hardware for configuring the input/output processing device was increased by the data buffer.

(Detailed Description of the Invention) An object of the present invention is to provide a priority determination circuit using flip-flops to a data transfer control unit in order to determine the priority order of data transfer between a plurality of input/output device units and a storage unit. The object of the present invention is to solve the above-mentioned drawbacks by providing an input/output processing device configured so that two or more input/output device sections having high speed and the same level of data transfer ability can be connected in parallel and controlled. .

(Description of structure and operation of the invention) The input/output processing device according to the invention includes a microprocessor,
It includes a storage section, a plurality of input/output device connection sections, a plurality of input/output device sections, and a data transfer control section. A microprocessor is used to process information.

The storage section is made up of memory elements in which data can be written and read. The plurality of input/output device connection sections have a direct memory access function. The plurality of input/output device sections are provided individually corresponding to the plurality of input/output device connection sections, and are for performing input/output operations. The data transfer control section controls data transfer between the storage section and the input/output device section via the input/output device connection section. It includes a ranking determination circuit.

(Explanation of Examples) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. First, each component of the present invention will be explained.

In FIG. 1, 1 is a program storage type microprocessor. 2 is a writable and readable storage section. 3 is a priority determination circuit 11 which constitutes the main part of the present invention.
FIG. 3 shows an example of a detailed partial configuration. 4 and 5 are first and second input/output device connection sections, and 6 and 7 are first and second input/output device sections that operate at high speed and have comparable data transfer capabilities. To make the explanation easier to understand, the first and second input/output device connection sections 4.5 and the first and second
Although the input/output device section 6.7 of the
Of course, a combination of the input/output device connection section and the input/output device section can also be connected. 101 t'i This is an address bus for accessing the storage unit 2. 102c is a data bus for writing data to or reading data from the storage unit 2. 2
01 Ifi A first device interface bus for connecting the first input/output device connection section 4 and the first input/output device section 6. Reference numeral 202 is used to write or read data to a second device interfter for connecting the second input/output device connection section 5 and the second input/output device section 7. a write request sent from the microprocessor 1 via the first data transfer request signal line 505;
Alternatively, the read request is accepted by the data transfer control unit 3. Furthermore, a second and a third
The write request 1. sent via the data transfer request signal lines 501 and 503. Alternatively, the continuation request is accepted by the data transfer control unit 3 and ends. Therefore, the priority order determination circuit 11 determines the priority order, and at the same time, one reception transmits a permission signal to the first to third data transfer request signal lines 502,
504 and 506, and outputs an access start signal to the storage unit 2 via the access start signal line 601.

FIG. 3 shows a priority determination circuit 11 and 1. First to third AND gates 1 related to this
2 to 14 and a flip-flop 10 are connected. In the priority order determination circuit 11, a data transfer request signal from the first input device connection section 4 is connected to the first input terminal 1 indicating priority 1 through the second data transfer request signal line 501.
A data transfer request signal from the input/output device connection section 5 of gJ2 is assigned via the third data transfer request signal line 503 to the second input terminal 2 which is assigned via '&- and indicates priority 2. There is. from the first input/output device connection section 4 to the second
A data transfer request signal MREQ1 is sent out via the data transfer request signal line 501, and a data transfer request signal MREQ2 is sent out from the second input/output device connection section 5 via the third data transfer request signal line 503. When M is sent out according to the timing chart shown in FIG.
Flip-flop 10 for inhibiting I'tHQ 1
As a result, MRBQI and MRBQ2 are alternately suppressed, and data transfer requests can be accepted alternately. That is, in FIG. 2, for example, when the second MREQI■ and the first MREQ2■ are being sent, the first data transfer acceptance is the signal ACK sent on the permission signal line 502.
Assume that shift flip-flop 10 is set to I. Therefore, the second MREQ1■ is suppressed by the negative output signal of the flip-flop 10 via the AND gate 14, and the first MREQ2■ has the highest priority. As a result, the priority determination circuit 11 sends a signal ACK2 on the permission signal line 504 to accept the second data transfer.

In the following sequence, it becomes possible to accept the 11th and 12th MREQ1■, but because of this, the flip flow is:.

Tube 10 is reset by the AND of FiMRBQ2 and ACK2. As already explained, when the output state of the flip-flop 10 is 1, if MRBQ1 and MRBQ2 are both sent out, priority is given to accepting M1'tEQ2. When the output state of the flip-flop 10 is O, if both MRBQl and MREQ2 are sent out, MREQl is accepted in accordance with the priority order. At initial setting □, the state of the output of the flip-flop 10 is set to 0. MRBQl and MREQ2 are connected to the second and third data transfer request signal lines 501, respectively.
,,503, ACKl and ACK2
are the first and second input/output device connections 4 and 5, respectively.
Sent from In this case, the next data transfer request signal can be sent before the usage time of the storage unit 2 ends due to the preceding data transfer request signal, so high-speed data transfer is possible.

(Detailed Description of the Invention) As explained above, the present invention is equipped with a flip-flop that determines the priority order of data transfer requests, thereby enabling high-speed input/output devices with the same level of data transfer capacity. This has the advantage that the device sections can be connected, and the probability of overrun and underrun occurrence can be suppressed to a low level with simple hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an input/output processing device according to the present invention. FIG. 2 is a timing chart showing data transfer between the storage section and the input/output device connection section in the input/output processing device shown in FIG. FIG. 3 is a diagram showing the connection of a priority determination circuit of a data transfer control section used in the input/output processing device shown in FIG. 1. 1...Microprocessor 2 storage section 3...Data transfer control section 4.5...I/O device connection section 6.7...I/O device section 10...Flip-flop 11...Priority (1 apex determination circuit 12, 13, 14...AND gates 101, 102, 201, 202...bus 30
1~304.401~404.501~506,601
...Signal line patent applicant NEC Co., Ltd. agent Patent attorney Hisashi I) Ro

Claims (1)

[Claims] a microprocessor for processing information, a storage section capable of writing and reading, a plurality of input/output device connection sections having a direct left memory access function, and a plurality of input/output device connection sections individually connected to the plurality of input/output device connection sections. Controls data transfer between the storage unit and the input/output device unit via a plurality of corresponding input/output device units and the input/output device connection unit, and determines the priority order of the data transfer. 1. An input/output processing device, comprising: a data transfer control unit including a priority order determination circuit equipped with a flip-flop for data transfer.