JPS5943456A - Information processor - Google Patents

Abstract

PURPOSE:To allow the data transfer of the 1st controlling method even during access to a solid-state memory, by connecting the 1st - the 3rd controlling means which have semiconductor memories respectively in series and connecting the solid-state memory to the 3rd controlling means. CONSTITUTION:A main processor CPU1 having an RAM1, an intermediate controller CPU2 having an RAM2, and a microcomputer 3 having an RAM3 are connected together by signal line INTRs 1-2 and INTAs 1-2. The CPU3 constitutes a disk control unit together with a disk interface FDC and a floppy disk FDD. Consequently, the disk control unit allows data transfer between the CPUs 1 and 2 even during access from the CPU3 to the FDD through the FDC to eliminate the need to interrupt processing with high importance in the middle of it, improving the operation rate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device including a memory device having a mechanical drive unit, such as a flexible disk memory device, a hard disk memory device, or an optical disk memory device.

Flexible disk memory devices, hard disk memory devices, optical disk memory devices, and the like are capable of storing large amounts of data and are also capable of random access, and are therefore used as external memory devices in information processing devices, that is, computers.

Although this type of memory device can store a large amount of memory, the access speed is slow because it involves mechanical operation.

For example, in a flexible disk device, the access time is the 1-rack movement time required to position the magnetic head position and the circumferential position of the disk, that is, the track position, and the time required to move the rack from a given position (sector) on the disk to the head position. It is determined by the rotational waiting time required for the magnetic head to reach its final position, the settling time required for the magnetic head to stabilize its position, and the head load time required for the magnetic head to fully contact the disk surface, and is at least several tens of millimeters long. Seconds are necessary. In the case of a write operation, since a read check is required after writing, it takes an additional time of about -50 m5.

Data loading and reading operations must be performed in synchronization with the rotation of the disk, so if the processing unit itself and the disk memory device are directly connected via an interface, the disk IE in which the disk device is positioned at a predetermined position, giving priority to the mechanical movement of the device, the processing device must immediately stop other processing and perform disk read/write operations. This data transfer for reading and writing data is generally I)
This is performed using the MΔ (die reflex 1-memory access) method. That is, the processing device hands over the right to use the bus to the DMA controller, and the IT controller controls the exchange of data from the memory of the processing device and the disk without going through the processing device. Therefore, during this DMA period, the processing device cannot perform the E process even if there is a request for other high-priority processing.

・So, in order to reduce the burden on the processing device and increase processing efficiency, the disk device is equipped with a control device that is independent from the processing device, and the control device is also equipped with a semiconductor memory.
of the disk device) I! It has been proposed to transfer data between a conductive memory and a semiconductor memory device of a processing device, and between a semiconductor memory and a disk of a disk device. According to this, for example, in reading, the processing device sets a command lj to the disk control device, and when a predetermined job is finished (between jobs), it checks whether there is data in the control device. If there is one, it is transferred to the processing unit's own memory. In other words, since the processing device is always the main entity, data transfer between the processing device and the disk can be performed when there is no prefecture tree for high-priority processing, depending on the convenience of the processing device. If, during data transfer, there is a request for a process with a higher priority than that process, the data transfer can be interrupted and other processes can be performed.

However, even if the above method is adopted, for example, when a disk control device is transferring data between disks, the processing device may not be able to transfer data between that control device. Can not. In other words, when the processing device executes a job that requires frequent disk access, if the access interval becomes shorter than the disk access time, it must wait until the data transfer between the control device and the disk is completed.

The first object of the present invention is to provide an information processing apparatus in which the main processing unit can perform highly efficient processing without being affected by the operation of the non-solid-state memory means, and the data transfer speed of each part can be arbitrarily adjusted. The second goal is to provide an information processing device that can
The purpose of

In order to achieve the above object, the present invention includes a main processing unit having a main memory, that is, a first control means;
A second control means having a semiconductor memory and a third control means having a semiconductor memory and performing data transfer with a non-solid state memory means such as a disk.
Data transfer is performed between the first control means and the non-solid-state memory device via the control means. According to this, even when the third control means is accessing the non-solid-state memory means, the first control means can exchange data with the second control means. Processing can be performed efficiently without having to wait until the data transfer of the control means of No. 3 is completed.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic block configuration of the entire apparatus of the embodiment. This will be explained with reference to FIG. The first control means is the main processing unit CPUI. The main processing unit CPUI has a first semiconductor memory, namely 1:.

It is equipped with a storage device RAM1. The second control means (intermediate control unit CPU2, CI) U2 is equipped with a second semiconductor memory RAM2. Intermediate control device CPU2
and the main processing unit CI) U1 are connected by a number of signal lines, and an interrupt request signal IN'R1 from the CPUI is applied to the interrupt input terminal of the CPU2.CP
U2 outputs INTAl in response to I N T Rl. The third control means is a microcomputer CPU3, and the CPU3 has a DMA controller DM inside.
Δ1. It includes a semiconductor memory device RAM3 and the like. Microcomputer CPU3 and intermediate control unit CPU2
are connected with many signal lines, and the interrupt request input terminal of the microcomputer (PLJ3) is
A signal from P tJ 2 + 1'', ITR2 is applied. CPU 3 generates TNTA2 in response to IN'FT<, 21.
The PU 3 is included in a disk control unit I-, which is also equipped with a disk, an interface I"DC, and a flexible disk device FDD.

FIG. 2 shows a schematic block configuration of the main processing unit CPU 1 shown in FIG. This will be explained with reference to FIG.

A central processing unit, a main memory device, a timer, a ROM, a communication control device, and a communication control device are connected to the system 11 bus of the CP T, J+.

One line of the I10 interface includes a CRT display unit, keyboard 22, and printer unit 1.
-, etc. are connected. The other line of the I10 interface is connected to the intermediate control unit, and the processing unit CPU 1 is connected via this line to the R, A M
] and the memory r (ΔM2) of the intermediate control device CPU2.

Third diagram 2. :, intermediate control device CP L, J in Fig. 1
The drawn shell of 2 is not shown. This will be explained with reference to FIG. In this embodiment, the intermediate control device is an Intel Mike O Broselli unit h8085A, RAM・■10・
Timer/Counter Knit 8], 56, RO
M・■10 Uniso I”8355.RAM Units h 81
It is composed of 85 mag. Microprocessor, ″′J-
Interrupt control line of Nitsu 1-8085 and 815
6 input/output ports to the main processing unit CP T, J 1
．． &: Connected. The input/output ports 1 to 8355 are connected to the disk controller.

FIGS. 4a and 4b show the configuration of the disk control device. First, the microcomputer CPU 3 will be explained with reference to FIG. 4a. CPU 3, Microprocessor unit 1-8085, manufactured by Intel Corporation, DM
Acon I-Rolako, Nitsu 1-8257 (DMA3),
To RAM memory 1 2114 (RAM3), R, O
M Memorunino I-2708.

It is composed of a bidirectional bus driver 8226 and the like.

The input/output lines of the bidirectional bus driver 8226 of one system and the interrupt signal line of 8085 are connected to the intermediate control device CPU2, and the input/output lines of the bidirectional bus driver 8226 of the other system.

The DMA control lines etc. from the 8257 are connected to the flexible RIKE interface F i)C.

41) Disk interface FI- with reference to figure 41)
)<=, The flexible disk device FDD, etc. will be explained. In this embodiment, ¥D274 manufactured by YE Data Co., Ltd. is used for FDD. YD274 is
It is a 5.25-inch double-sided flexible disk drive. This has a magnetic storage medium (distor) inside.
300.1-<F' M
), the magnetic head is positioned at a predetermined 1-rack of the disk by a 1-to-rack positioning mechanism consisting of a stepping motor, a reed screener, etc., the magnetic head is pressed against the disk, and the magnetic head is rotated at a predetermined position according to the rotation of the disk. Data is written and read based on timing. The disk interface FI)C generates control signals for the flexible disk device FDD and writes and reads data. In this example, the FDC is FDC manufactured by Western Digital.
D1791 is used. F L) ('', is, Cl
) U interface, controller 1-roller/format section.

It consists of an FDD interface, etc. Controller 1 roller/format section is disk 2 data file 1
)--control the mat. The write data from Fl2C is directly applied to the flexible disk device, and I"D
Read data from D is applied to FDC via the V'FO data separator. These write data and read data are serial data, and are subjected to parallel-to-serial conversion inside the FDC.

This will be explained with reference to FIGS. 4a and 4b. When writing and reading data to and from the flexible disk device FDD, it is necessary to transfer the data sequentially between the FDC and the micro combi coater CPU3 in synchronization with the rotation of the disk. Since this data transfer rate is relatively high, the software i-ware of the microprocessor 8085 cannot process the data transfer. Therefore, micro combi coater CPU3 (RAM3) and F
When transferring data between DCs, DMA
The controller and 3257 perform control.

If the microprocessor 8085 processes the DMA controller (roller 8257) in advance, such as initializing, mode setting 1-, address setting, etc., then, for example, when reading data, the magnetic spatula of the FDD When 1- reaches a predetermined position on the disk, the FDC outputs a signal from 1 to 1 and returns the data to ``0''.

DALO~DAT-7(-
If the output is 1;, send a DMA request to 8257. II) M△Con(-Roller 8257 receives this request and issues a 7j, -Role 1- request to the Hall I-Request. The operation is stopped and the right to use the system bus is not handed over to l-) MA controller 1 to roller 8257.

After that, until the predetermined number of data transfers are completed, the address signal and readout from the DM7N controller 1-roller 8257,
Write control signals are issued, and in response to these signals, F
The 8 hit 1 data from DC are sequentially written to predetermined addresses in the RAM memory 21j4. When this process is completed, the microprocessor 8085 takes control of the system bus and starts working.

FIG. 5 shows an outline of the operation of the microphone 8085 of the microcomputer CI tJ3.It will be explained with reference to FIG.

First, perform the initial settings. That is, the output capo-1 is set to the initial state, the disk control unit yh FDC and the DMA control unit h 8257 are initialized, and the buffer memory (R11M3) is cleared.

Read the contents of the instruction register. If the contents are not cleared, wait until an instruction is written to the instruction register by interrupt processing.

DMA control unit 8257 (DMA:□3)
The predetermined data is sent to 1-. That is, write the start address of the memory hasher in register 71, write the number of data to be transferred in terminal register 1,
Write the specified data in the register to Mo 1 Hese, No 1 1
．． Now l) MΔ control unit l-8257 to D1114
When A11'/varnish l-(+) RQ2) is present, 8257 starts the predetermined operation.

℃, read command or 1. depending on the contents of the instruction register. l
- Rai 1-21 cloak control Unisol I”
1. ) and then load it into the register. Due to this ■? D C becomes T3 US Y, and data storage 1~ is performed at predetermined timing according to the rotation of the disk
(DRQ) is output to 8257.

Due to this, 8257 (DMA3) starts operating and outputs bold state T to master processor unit 8085 and l-I R, Q to S1. 8085 becomes bold state due to this, and the system bus and outputs Hall 1 Hair Tanorithod I1.i2) A to 8257. Now, the multi-rotor controller CPU 3 enters the IDMA mode, and the 8257 sends predetermined address data and control signals (IOR, IOW, MEMR, M
EMW, etc.) is output, thereby performing data transfer between the FI'lC and the buffer memory RAM3.

When the transfer is completed, the BUSY state is released.11.
Check the status register to see if there is an error.

Sets the processing end flag in the instruction register to 1.

When transferring data between CF' U 2 and CI U 3, the microprocessor 8085 of CPU 3 executes interrupt processing. That is, CP T, J 2 to I N
When TR2 comes, the next process is executed.

CI) Reads the instruction output by the TJ 2 and, depending on the type of instruction, loads the instruction or the instruction data stored in the register of the CP TJ 3 in advance.

If it is an instruction from CI) U 2 or a data write command, the next data output from CI) U 2 will be sequentially output from CI) U 2.
F-' Transfer to memory RA of tJ3, M3.

If the instruction is to read data (, this means that it is checked whether the specified read data is in the RAMB by checking whether the processing end flag is set in the instruction register. If there is no specified data in RAM3, B, CI)
Outputs "no data" to U2. When a read command is issued for the first time, the C1) IJ 3 outputs "no data" and returns to the main process to perform disk data readout processing since no data has been read for the command. When data reading for the king's instruction is completed and data corresponding to the RAM 3 exists, the data is transferred to the CPU 2. Then, the instruction is stored (: p Clear the contents of the register of IJ 3.

FIG. 6 shows the general operation of the microb "1 Cenoza Uniso (・8085) of the intermediate control device CI-'U2.
This will be explained with reference to the figure.

Perform the initial settings. That is, the output board is set to the initial state, and the output board is set to the initial state.
185).

Read the contents of the instruction register. If the contents are cleared, the CPU waits until an instruction is written to the instruction register by interrupt processing.

It outputs an interrupt request signal IN'I to the CPU3. Microcomputer c I-) u 3 is DM
If it is not A mode, Ic immediately after receiving I NTR2.
Since T N'r A 2 is output, CP LJ 2 waits for I N 'T'' A 2 to be output.

When writing data, first output instruction code 1-, then write memory R at the address indicated by that instruction code.
The data in ΔM2 is transferred to the CPU3. When reading data, the command code is output to (: P U 3, and the corresponding data is stored in the memory R of CP TJ 3.
A: Check to see if it is on 3.

If there is data, the data output from the CPU 3 is sequentially stored in a predetermined address of 8M2. .

Then, the processing end flag in the instruction register is set to 1.

CI) When transferring data to and from CT' U2, the microprocessor unit of Cp u :2 =
8085 executes interrupt processing. In other words, CF>U
1 to ■NTR], the CPU 2 reads the CPU 2 to execute the next process or the command to be output, and depending on the type of the command, reads the command or the command set in advance in the 1 register of the CPU 2. Loads the current instruction list.

CPt, J + or +7. The command is a data write command, and the next data output from the CPU 1 is sequentially stored at a predetermined address in the memory RAM 2 of the CI-12. If the instruction is to read data, the predetermined read data is 1zA by checking whether the processing end flag is set in the instruction register.
Check whether it is within M2. If there is no predetermined data in RAM2, it outputs "no data" to CI) LJI. When a read command is issued for the first time, the CPU 2 has not transferred any data to the CPU 3 for that command, so it outputs "No data ()".
C- Return to the carrier main process and perform data transfer with 0r) TJ3. In this data transfer, c p u 2
instructs the CPU 3 to read the disk data. When the disk data read and data transfer for that instruction is completed and the corresponding data exists in RAM2, the data is transferred to C)) U1. Then, the contents of the register of CI) U2 in which the instruction was stored are cleared.

The microcomputer cpu:3 of the intermediate control device CPU2, the disk control-1, and the chive 1- are as follows!
-The main processing unit (: P tJ
] can output disk access commands at any time according to the convenience of its own processing operation, and after outputting those commands, other jobs are executed until the data from the disk is needed. Can be executed. Furthermore, even if the disk device is being accessed, the main processing unit can output the next data entry command or data read command to the intermediate control unit ('tJ2) without waiting for the access to complete.

FIG. 7 shows an example of the timing of data transfer between each control device. An example of the overall operation of the mink will be explained with reference to FIG. For example, main processing unit CPU
has completed the specified job ('I' at '7', issues a disk data write command at 1, and writes the specified data to CF)
Transfer from U1 to CPU2. , when the processing is completed ('T'2), the CPU executes the next job, and the CPU
2 sends T N T RI to CPU 3 and CP
The disk write instruction of the write data obtained from U i and the predetermined data are transferred c P U 3 r=. At T23, CPU 3 performs a disk write operation of the transferred data. At this time, since the CPU 2 is in a state where it can accept interrupts, the CPU 2 can immediately instruct the CPU 2 to read data from the disk without being affected by the execution of other processes.

In other words, in this case, data transfer between disk and CPU3,
CI) [J 1. - Parallel processing with data transfer by CPU 2 will be performed. Then, CPU2
3-Wait for the DMA transfer between FDC to finish,
Outputs the following command to CPU3. Even during this waiting time of CPU2, the CPU 2 again issues the next command.
It can be sent to 2.

In the embodiment described above, the main processing unit CPtJl-intermediate control unit rv control PU2. and intermediate controller CPTJ
2-Microcomputer CPU3 data transfer is performed by software control, but CPU3-
DMA transfer may be performed as between FDCs. In that case, CP01 years old? and CP t-12 respectively.
A control unit is provided and configured to send data via the l/'(') port, and one DMA control unit is set to I10 line 1-, memory read mode 2,
The other D IV? All you have to do is set the unit 1 to 10 read and memory write mode to the eight systems.

As described above, according to the present invention, even when a disk is being accessed, the computer
I) can transfer data for disk commands and data reading, so there is no need to interrupt highly important processing in the middle, and parallel processing can be performed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall schematic configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the main processing unit CPUI in FIG. 1, and FIG. 3 is the intermediate control device in FIG. 1. CPU
Figure 4a is a block diagram showing the connection between the microcombi two CPU U3 and FIC in Figure 1, and Figure 4b is a block diagram showing the connection between the FIC in Figure 1 and the flexible disk device. A block diagram showing the connection with the FD "], Figure 5 is the microprocessor unit in Figure 4a"
FIG. 6 is a flowchart showing the general operation of the 8085, FIG. 3 is a flowchart showing the general operation of the 8085, and FIG. be. CI'tJI:j:, processing device (first control means) CP
U2: Intermediate control device W (second control means) CI-ゝ(J
3: Microcomputer (third control means) 1” D
(: :Disk interface r” IJ D
:Flexible disk memory device (non-solid memory means)

Claims (1)

[Claims] (1) a first control means comprising a first semiconductor memory means; a second control means connected to the first control means and comprising a second semiconductor memory means; a second control means connected to the second control means; , a third control means comprising a third semiconductor memory means; and a non-solid state memory means connected to the third control means; An information processing device characterized in that the contents of the memory means are stored in the non-solid-state memory means, and the contents of the non-solid-state memory means are stored in the first memory means in response to a second instruction from the first control means. .