JPS5969844A - Loading method of microprogram - Google Patents

Abstract

PURPOSE:To reduce the loads of a computer and a main storage in an SVP by writing into CS directly through an interface between the SVP and a CPU without passing through a main storage of SVP when loading a microprogram in a control storage (CS). CONSTITUTION:An interface on the CPU side is provided with a decoder 7, a command register 8, a data register 9, an address register 10, and a control circuit 11. When data are to be written from an interface 5 of the SVP to the CS 12 of the CPU, a write instruction to the CS 12, a write address of the CS 12 and a write data are set up in a command register 8, an address register 10 and a data register 9 respectively, and then a start signal for executing the contents of the command register 8 is applied to the control circuit 11 to execute the command. At the loading of the microprogram to the CS, the microporgram can be written in the CS directly through the interface between the SVP and CPU and the loads to the computer 2 and main storage 3 of the SVP are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a central processing unit and a service processor (SVP).
The present invention relates to an information processing system having a central processing unit (abbreviated as ), and particularly relates to a microprogram loading method in which a microprogram of a central processing unit is loaded by SVP.

(b) Prior art and problems The central processing unit has a control storage (CONTROLS) where a microprogram to control the central processing unit is stored.
TORAGE (hereinafter abbreviated as C8), and in large-scale computers, the C8 is usually configured with RAM, so that various function changes can be handled by rewriting the microprogram. However, C8 is RA
If the C8 is configured with M, it is safe to initialize it by loading the microprogram into the C8 from an external storage device when the power is turned on. This initialization is performed by the initial microprogram load (INITIAL MICROP).
ROGRAMLOAD (hereinafter abbreviated as IMPL). In the above computer, an external storage device such as a floppy disk device is prepared for each device for the IMPL.

Particularly in recent years, a C8 is provided for each unit in the central processing unit, which is called a distributed microprogram, and therefore external storage devices as many as the number of C8O are generally required. Furthermore, if the central processing units constituting the system are multiprocessor type, external storage devices corresponding to the number of central processing units are required.

However, in an information processing system equipped with SVP, in order to avoid the waste of having duplicate external storage devices as described above, SVP
The auxiliary storage device connected to the computer has come to be used instead. In other words, all microprograms for the central processing unit are prepared in the auxiliary storage device under the SVP, and when the information processing system is powered on, the SVP executes the central processing unit's C.
8 to load the microprogram. Since SvP is an independent computer system, it is not possible to display or change the contents of microprograms in auxiliary storage9.
Managing the version number, comparing the contents of C8 with the contents of the auxiliary storage device, selectively loading microprograms (for example, loading a diagnostic microprogram and loading a system operation microprogram), etc. I became K so that I could do it.

However, it is necessary to read the data onto the micro main memory prepared in the auxiliary storage of the SvP, and then load the data on the main memory into the C8 via the interface between the SvP and the central processing unit. At this time, if the capacity of the main memory is not sufficient for the amount of data in the microprogram, it is necessary to perform the data transfer by dividing the above operation into several times. Auxiliary storage devices usually have a direct memory access (DIREETMORY ACCESS) mechanism, but the interface between the SVP and the central processing unit is generally a program transfer method in consideration of versatility. be. Therefore, as the amount of data in a microprogram increases, its transfer rate becomes a problem. In order to solve this problem, if a direct memory access mechanism is also provided in the interface circuit between the SVP and the central processing unit, the interface circuit will become complicated and the versatility will be lost.Moreover, it will still go through the 5vPO main memory, so in any case, The method of loading a microprogram from an auxiliary storage device under SVP has the drawback of requiring a large amount of time due to IMPL.

(c) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks, and when a microprogram is loaded from the auxiliary storage connected to the SVP to the CS of the central processing unit, it is possible to load the microprogram without going through the 5vPO main memory. By directly transferring data from the auxiliary storage to the central processing unit C8, IMPL time can be reduced and
The object of the present invention is to provide a microprogram loading method for the purpose of reducing the load on the SVP computer associated with PL.

(d) Configuration of the Invention The configuration of the present invention includes an increment prohibition mode for a circuit that increments a memory address when data is transferred to the memory by a direct memory access mechanism to the SVP common bus,
In an information processing system that connects an auxiliary storage device that has the function of sequentially writing data to the same address, stores the microprogram of the central processing unit in the auxiliary storage device, and executes IMPL, SvP is common. svP via path
Depending on the address information and write timing when data is written to the data buffer in the interface between , said C8
The interface between the SVP and the central processing unit is configured to set the next CS address by incrementing an address register that determines the address of the data buffer, and data is transferred from the auxiliary storage device to the data buffer in an address increment prohibition mode. By doing this, the microprogram of the central processing unit stored in the auxiliary storage device can be directly downloaded via the interface 8-1 between the svP and the central processing unit without going through the main memory of the SvP. It was designed to be transferred to

(e) Embodiment of the invention FIGS. 1 and 2 are block diagrams showing an embodiment of the invention.

FIG. 1 is a diagram showing an example of a connection between SvP and a central processing unit. The SVP has a common bus 1, a computer 2, a main memory 3. Auxiliary storage device 4. Interface 5゜Display device 6
is connected. The address of interface 5 is main memory 3
A portion of the address has been assigned. Therefore, calculator 2
is load (LOAD) and store (sroaE) for interface 5.

Control is possible by accessing a control register in the interface 5 using a main memory access command such as MOVE. The interface on the central processing unit side includes a data reader 7. Command register 8. Data register 9. Address register 10. Control circuit 11
When writing data to the C812 of the central processing unit from the interface 5 of the SVP, send a write command to the C812 to the command register 8, write the write address of the C812 to the address register 10, and write the write address of the C812 to the data register. Write data is set in the command register 9, and then a start signal is given to the control circuit 11 to cause the contents of the command register 8 to be executed. IMPL
Continuous write operations to the C812 such as the above are also executed by repeating the above operations multiple times.

The circuit of FIG. 2 is a detailed diagram of the interface 5 of FIG. The C on the central processing unit side is sent to the unit address register 9 via the receiver 13 connected to the SvP common bus 1.
The address of each device with 8 is stored. The address entered in the unit address register 9 is sent out via the driver 24, and the target device for writing data to C8 is selected. The select address register 20 receives an address for selecting the command register 8, data register 9, address register 0, etc. shown in FIG. command register 8 or data register 9. Address register 0, etc. is selected. Data to the register is provided from output data register 21 through driver 26. When data is set in the output data register 21 via the common bus 1, the address register 15 is set by the timing generator 16 through the driver 29.
The contents of the output data register 21 are transferred to the command register 8. of the central processing unit according to the contents of the select address register 2o. Data register 9. address register 1
A timing signal is sent to input the contents of the output data register 21 into the output data register 21, etc.

Each device equipped with C8 on the central processing unit side is selected by a unit address register 19. Next, select address register 20. Using the output data register 21, set a write command to the C812 in the command register 8. Similarly, select address register 20. C81 to the output data register 21 and address register 10
Write address 2 sets write data to C812 in data register 9. Conventionally, the control register 23 causes the control circuit 11 to execute the contents of the command register 8 immediately after this, but in the present invention, the control circuit 11 executes the contents of the command register 8.
detects that the content is a write command to C812 and that data has been written to data register 9,
Data is written to the C812, and after the writing is completed, an instruction is given to the address register 10 to increment the address.

Command register 8 holds a write command to C812, and address register 10 holds the next CS address. Therefore, from now on, every time new data is set in data register 9, the contents of data register 9 are written to C812, and at the same time address register 1
Since 0 indicates the next CS address, data to be written to the C812 is successively set in the data register 9.

In order for SvP to set data in data register 9, it is only necessary to hold the address of data register 9 in select address register 20 and set data in output data register 21, so data to C812 is Sequentially setting the output data register 21 to 0 The above steps are performed by the SVP computer 2, but since the interface 5 is assigned a part of the address of the memory 3 as described above, the data is sent from the auxiliary storage device 4. Even if the data is transferred to the output data register 21, the data is sequentially written to the C812 in the same way. Therefore, after initializing the command register 8 and address register 10 as described above, the SvP computer 2 prohibits the auxiliary storage device 4 from incrementing the memory address of the auxiliary storage device 4! , causes the data to be transferred to the output data register 21. Since the data read from the t10 auxiliary storage device 4 is prohibited from advancing the memory address, it is sent to the output data register 21 at the same address, and the strobe signal generated by the timing generator 16 and the select address register 20 are used as data registers. 9 is selected and the contents of command register 8 are C.
812), the control circuit 11
The data is sequentially written into the C812 at the address indicated by the address register 10.

Receiver 2F1 selection circuit 17, 18. Driver 14
is a circuit that inputs data from the central processing unit,
Since it is not directly related to the present invention, the explanation will be omitted. (f) As described in detail of the invention, when loading a microprogram to C8, the present invention uses 1-negative SVP without going through the main memory of SvP.
Since it is possible to write to the C8 via the interface between the CPU and the central processing unit, the load on the SVP computer and main memory is reduced, and 11j can be shortened at IMPL, so the effect is incredible. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the connection between the SVP and the central processing unit, and FIG. 7A2 is a detailed diagram of the interface 5 in FIG. 1. 1 is a common path, 2 is a computer, 3 is a main memory, 4 is an auxiliary storage device, 5 is an interface, 7 is a screen reader, 8 is a command register, and 9 is a data register. 10 is an address register, 11 is a control circuit, 12 is a control storage, and 13.27 is a resin. 14, 24.25.2 G, 28.29 is the driver,
19 is a unit address register, 20 is a select address register, 21 is an output data register, 22 is an input data register, and 23 is a control register.

Claims (1)

[Claims] An information processing device equipped with a service processor, in which the computer, memory, various interface circuits, etc. are connected by a common bus method, and the address of the interface circuit is assigned a part of the memory address, and an access method equivalent to that of memory is used. When data is transferred to the memory using a direct memory access mechanism, the common bus of the service processor configured to allow access is provided with an increment prohibition mode for the circuit that increments the memory address. An information processing system in which an auxiliary storage device having a function of sequentially writing data is connected to the auxiliary storage device, a microprogram of a central processing unit is stored in the auxiliary storage device, and an initial microprogram load to the central processing unit is executed by a service processor. According to the address information and write timing signal when data is written to the data buffer in the interface between the service processor and the central processing unit via the common bus of the service processor,
At the same time as writing the data written in the data buffer to the control storage in the central processing unit,
The interface between the service processor and the central processing unit is configured to increment an address register that determines the address of the control storage to set the next control storage address, and increment the address register from the auxiliary storage device q to the data buffer. By performing data transfer in advance-prohibited mode, the microprogram of the central processing unit stored in the auxiliary storage device can be transferred via the interface between the service processor and the central processing unit without passing through the main memory of the service processor. A microprogram loading method characterized in that the microprogram is directly transferred to the control storage.