JPS61217827A - Data transfer controller - Google Patents

Abstract

PURPOSE:To increase the data transfer speed by using a RAM having the memory capacity larger than the data equal to a sector in place of a data FIFO as a data buffer within a disk controller. CONSTITUTION:Buffer memories BM1 and BM2 having the 256-byte capacity respectively are connected to a host bus H-BUS and a kernel bus K-BUS. The data equal to a sector (256 bytes) are read out and transferred between a hard disk controller and a disk device while the transfer of data is stopped at the side of a system bus. These transferred data are stored temporarily in the memories BM1 and BM2 and then transferred to the host side via the system bus.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to data transfer control technology, and is effective when used in a data transfer control device in a system equipped with a device that requires data transfer, such as a hard disk drive. related to technology.

[Background Art] In a system equipped with a floppy disk device or a hard disk device, it is necessary to read serial data stored on a magnetic disk and convert it into parallel data.
It is necessary to convert parallel data sent from the system's host CPU (central processing unit) to the disk device side into serial data.

A disk controller LSI is used as a device to control data transfer between such a host CPU and a disk device.
There is. A conventional disk controller has an internal buffer memory called a data FIFO (first-in first-out), and data transfer between a host CPU and a disk device is performed via the data FIFO.

However, the data FIFO is composed of a shift register, and the data that can be stored in the data FIFO is about 8 bytes.

However, in a disk device, each sector, which is a storage unit, can normally store about 256 bytes of data. Therefore, when reading or writing one sector worth of data, if data is transferred between the host and the disk device using FFO transfer, the data is transferred between the host and the FIFO in parallel with reading or writing data from the disk. F if data is not exchanged with
IFO will overflow.

Therefore, in a data transfer method using a conventional disk controller having a data FIFO, the data transfer speed between the host and the disk controller is limited to the speed at which data is written to and read from the disk. As a result, there is a problem in that the system bus exclusive time on the host side becomes longer and the system throughput decreases.

In addition, because the FIFO capacity of conventional disk controllers is small, it is difficult to transfer data between multiple disk devices under the control of the controller.
Data has to be transferred to the main memory device consisting of semiconductor memory via the system bus.

Regarding hard disk controllers that transfer data using the FIFO method, please refer to Nikkei Electronics J 1982, published by Nikkei McGraw-Hill.
August 30 issue (No. 298), pages 187-216
It is written on the page.

[Objective of the Invention] The object of the invention is to reduce the system bus exclusive time during data transfer between a disk device and the host side, reduce the burden on the host side during data transfer, and improve system throughput. The object of the present invention is to provide data transfer control technology that enables

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, there is a data FIF in the disk controller.
Buffer R, which has a storage capacity larger than one sector of data, serves as a storage unit in a disk device instead of O.
By providing AM (Random Access Memory) and allowing data for one sector to be stored in a buffer RAM before being transferred, data can be transferred between the disk device and the disk controller at the same time, and the data can be transferred between the disk controller and the host. This eliminates the need to transfer data between the two, allowing data to be transferred all at once, thereby reducing the time occupied by the system bus, and
Using this buffer RAM, data can be transferred between devices under the control of the disk controller without going through the system bus, reducing the burden on the host side and improving system throughput. This aims to achieve the above objectives.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a hard disk controller, in which each circuit block is formed on one semiconductor chip such as a single crystal silicon substrate, It has been made into an LSI.

This hard disk controller is connected to a CPU (microprocessor) via a bus to form a microcomputer system.

In FIG. 1, a host CPU that controls the entire system is disposed on the left side of the eight-speed disk controller, and a disk device (disk drive) is disposed on the right side.

Inside the hard disk controller, there is a command memory that holds commands supplied from the host CPU.
It decodes the register CR and the commands stored in this command register CR to form various internal control signals,
A kernel processor section 1 for output is provided.

This kernel processor unit 1 has a microprogram RO in which a group of microinstructions corresponding to each command is stored.
It has M11 and forms various control signals to sequentially execute tasks according to commands supplied from the host CPU.

In addition to the microprogram ROMII, the kernel processor section 1 includes an ALU (arithmetic logic unit) 12 that performs various arithmetic operations necessary for command execution, and a 64-byte storage unit that stores parameters and status necessary for command execution. A working RAM 13 is provided.

Further, within the kernel processor section 1, a disk interface control circuit 14 is provided which controls the input/output of various interface signals necessary for exchanging data with a disk device.

The microprogram ROMII and ALU 12 in the kernel processor section 1. Working RAM13. The disk interface control circuit 14, command register CR, etc. are connected to the kernel bus via -BUS.

In addition, the above-mentioned kernel bus -BUS contains the status information that maintains the internal state of the hard disk controller.
A register SR is connected so that it can be read from the host CPU side at any time.

The above status register SR and command register C
Reading and writing data to and from R is performed via data buses DO to [)ts on the host side.

Also in the hard disk controller.

When transferring data between the host CPU and the hard disk controller, the read/write signal R/W
A host interface control circuit 3 is provided for exchanging signals such as a data transfer control signal such as a bus control signal DTACK, a chip selection signal σ, a reset signal RS, and the like.

The host side data bus no't)ts is connected to the internal 8-bit host bus H-ts via the data register DR.
A buffer memory BM1.8M2 each having a capacity of 256 bytes is connected to the host bus H-BUS and the kernel bus -BUS. This buffer memory BMI f 8M2 is RAM
The storage capacity is determined based on one sector worth of data (256 bytes) that is read and written to the magnetic disk at a time.

Buffer memory BM1. BM2 is a buffer pointer BP, each having an address counter function.

Continuous access is enabled by BF2. External host CPU or DMA (direct
Memory access) By setting the contents of buffer pointers BP, BP2 from the controller, data can be read from or written to a desired location. Also, due to the lack of 256-byte buffer memory.

It is also possible to cope with a case where one sector has a data portion of 512 bytes.

Further, the hard disk controller of this embodiment is provided with a satellite processor section 2 for controlling data transfer with the disk device.

The satellite processor section 2 includes a serial-to-parallel/parallel-to-serial conversion circuit 21, an error detection/correction/encoding control circuit 22, and a control section 23. The straight-parallel/parallel-direct conversion circuit 21 is
It converts serial data read from the disk device into 8-bit parallel data, and converts write data sent from the host side into serial data.

The error detection and correction/encoding control circuit 22 uses a cyclic redundancy check method to check whether there are any errors in the data read from the disk device, and if there is an error, it corrects it and outputs it, and also performs data writing. Sometimes, an error correction code is formed based on the write data and supplied to the disk device. The error correction code is stored together with the sector management information indicating the position of the sector in the ID section before the data section in which original information is stored in FIG. 2 showing the sector configuration. The data part is configured as 256 bytes,
A sync byte SB indicating the start of data is provided at the beginning of each of the data section and ID section.

The error detection/correction/encoding control circuit 22 receives a read clock R-(;LK and a write clock W-CLK, which serve as synchronizing signals at the time of reading and writing) from the disk device.

The control unit 23 controls the operation of the above-mentioned serial-parallel/parallel-serial conversion circuit 21 and error detection/correction/encoding control circuit 22, for example, a PLA (programmable logic array).
The control circuit is constructed using a random logic method.

In this embodiment, the above-mentioned straight-to-parallel/parallel-to-direct converter circuit 2
1 and the buffer memories BM1 and 8M2 are connected by a satellite bus 5-BUS, and data transfer between the host side and the disk device is performed using the buffer memories BM1 and 8M2.
This is done via 2.

Therefore, according to the hard disk controller of this embodiment, when reading and transferring l sector worth of data (256 bytes), data transfer on the system bus side is suspended and the hard disk controller and disk device are connected. Data is transferred between the two, temporarily stored in a buffer memory, and then transferred all at once to the host side via the system bus.

However, while the data transfer between the host side and the hard disk controller is parallel transfer, the data transfer between the hard disk controller and disk device is serial transfer, so the data transfer speed on the disk device side is It's better.

Currently, the data transfer speed is considerably slower than that of the host.

However, according to the above embodiment, data transfer on the disk device side and data transfer on the host side are performed separately.

Therefore, data transfer on the host side can be performed at the highest transfer speed without being constrained by the data transfer speed on the disk device side. As a result, the system bus exclusive time during data transfer between the host side and the disk device is shortened, and the system throughput is improved.

When the data portion of one sector is 256 bytes, by alternately using buffer memories BM1 and BM2,
Data transfer between the host and controller and between the controller and disk can be performed in parallel. This reduces the transfer time when transferring a large amount of data.

Moreover, in this embodiment, the hard disk controller having the configuration shown in FIG. 1 is provided with a new command processing function for data transfer without using the system bus, as will be described below.

That is, this new command temporarily holds one or two sectors worth of data read from the disk device in the buffer memories BM, BM2.

This means that the data is output to the disk device again without being output to the system bus.

As a result, when two or more disk devices are connected under the control of the same hard disk controller, when you want to transfer data in one disk device to the other disk device, conventionally 311 CB), it was necessary to transfer the data to the main memory (main memory) on the host side before performing the process. In contrast, according to the above embodiment, data can be transferred directly from drive to drive without passing the data to the main memory as shown in FIG. 3(B). Therefore, it is possible to copy data in the drive without using the system bus, which reduces the burden on the DMA controller on the host side, and reduces the exclusive time of the system bus, so the system Throughput is improved. Moreover, since data copying and the like can be performed without using a DMA controller, a simple and inexpensive system without a DMA controller can be constructed.

Note that hard disk drives usually have multiple magnetic heads and multiple disks, so...
When such a disk device is used, data can be copied not only between drives as described above but also within or between disks without going through the system bus.

Furthermore, in addition to copying data, the host CPU externally transfers data to the buffer memories BM1 and 8M2 while holding one or two sectors worth of data in the buffer memories BM1 and 8M2.
By rewriting the data in BM2, it is possible to partially modify the data without going through the system bus.

In the above embodiment, two 256-byte buffer memories are provided, but the present invention is not limited to this, and the buffer memory may have a capacity of only one or 512 bytes.

[Effect (1) A buffer RAM with a storage capacity larger than one sector of data, which is a storage unit in a disk device, is installed in the disk controller instead of a data FIFO.
(Random Access Memory) was installed so that one sector's worth of data could be partially stored in the buffer RAM before being transferred.

There is no need to transfer data between the disk device and the disk controller and between the disk controller and the host at the same time, and data can be transferred all at once, reducing system bus exclusive time.
This has the effect of improving system throughput.

(2) A buffer RAM in the disk controller that has a storage capacity larger than one sector of data and serves as a storage unit in the disk device instead of the data FIFO.
(random access memory), and data for one sector can be partially stored in the buffer RAM before being transferred, so the buffer memory can be used to transfer data between devices under the control of the disk controller. The ability to perform transfer without going through the system bus has the effect of reducing the burden on the host side and improving system throughput.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the buffer memory is formed of RAM, but it can also be formed of a large FIFO such as 256 bytes.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, which is an A-drive disk controller, but this invention is not limited thereto. Instead, it can be used generally for controller LSIs having a storage device under their control, such as a floppy disk controller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a hard disk controller, and FIG. 2 is an explanatory diagram showing an example of a pattern of serial data stored on sectors of a magnetic disk. FIGS. 3(A) and 3(CB) are explanatory diagrams showing a data transfer control system using the present invention and a conventional hard disk controller, respectively. l...Kernel processor unit, 2...Satellite processor unit, 3...Host interface control circuit, 11...Microprogram ROM,
12...ALU, 13...Working RAM,
14...Disk interface control circuit, 21
. . . Straight-parallel/parallel-to-direct conversion circuit, 22 . . . Error detection/correction/encoding control circuit, 23 . . . Control unit, K-B
US: Kernel bus, 5-BUS: Satellite bus, H-BUS: Host bus.

Claims (1)

[Claims] 1. A data transfer control device that controls data transfer between an external storage device and another storage device or control device based on a supplied command, the device controlling data transfer between an external storage device and another storage device or a control device, It has a built-in buffer memory that has a storage capacity larger than the amount of data for a group of data that is continuously read and written, and it is possible to directly control data transfer between multiple devices under its control via this buffer memory. A data transfer control device characterized in that: 2. The data transfer control device according to claim 1, wherein the buffer memory is a random access memory that can be read and written at any time. 3. Claim 1, wherein the storage device is a disk device using a magnetic disk as a storage medium.
3. The data transfer control device according to item 1 or 2.