JPS62154153A - Control system for external storage - Google Patents

Abstract

PURPOSE:To attain the continuous transfer of remaining records within the same track after the transfer of the record designated by a CPU, by providing two microprograms to an external storage device and running both programs in parallel with each other. CONSTITUTION:When a head is positioned at a record R0 of a track of a magnetic disk 4, a muP 1 executes a command read R0 and transfers the record R0 to a CPU 1. In the same way, the records R1 and R2 are read out and transferred to the CPU 1 when the head is positioned at these records. While a muP 2 reads the records when the head is positioned at records R3, R4-Rn respectively and transfers and stores these records in a cache memory 3 via buses 25 and 26. Here the muP 1 is also working during the transfer and storage of the records R3-Rn and processes continuously the commands produced successively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an external storage control system, and particularly to a control system for an external control device equipped with a cache memory.

[Background of the invention]

Magnetic disk devices, magnetic tape devices, magnetic drum devices, and the like are often used as external storage devices for computer systems. However, the access time for these is on the order of tens of milliseconds at most, and the central processing
There is a difference of about 10 5 to 10 6 compared to the access time of the main memory in U), which is several hundred nanoseconds, and this is an impediment to improving the performance of electronic computer systems.

An external storage control device with a cache memory is used to compensate for the slow speed of this external storage device. In other words, data that is frequently used by the CPU is stored in the cache memory, and when there is a transfer request from the CPU, the data is read from the cache memory without being read from an external storage device and transferred to the CPU. Because it has a transfer function, the access time can follow the hundreds of nanoseconds of semiconductor memory, thus enabling high-speed data access. The cache memory is generally managed in units of tracks of an external storage device. Furthermore, if the record (track) specified by the CPU does not exist in the cache memory, it is directly read from the external storage device and transferred to the CPU, and at the same time, transferred to the cache memory and stored therein. When the transfer of this record is completed, it is necessary to transfer the remaining codes of the track in which the record exists to the cache memory and store them as well. In other words, the cache memory contains blocks (here,
Since copies are transferred and stored track by track, the remaining records of one track must be transferred to the cache memory along with the currently used record.

Traditional system? In the device, reading of the record to be transferred to the CPU is discontinuous, while reading of the remaining records in the same track is discontinuous. That is, when the reading of records to be transferred to the CPU is completed, the control device and the external storage device are once disconnected, and after the medium of the external storage device rotates several times, the remaining records are read out. This operation will be explained using a magnetic disk control device as an example with reference to FIGS. 5 and 6. 5 is a block diagram of the magnetic disk subsystem, and FIG. 6 is a diagram showing an example of a command group (commands) issued from the CPU. In FIG.
, 2 is a magnetic disk controller (DKC).

3 is a cache memory, 4 is a magnetic disk device (DK
U), 5 indicates one track in the magnetic disk drive (DKU). Assume that a command group as shown in FIG. 6 is issued from the CPUI. That is, record R
This is a command to read O, RL, R2 and sector number. By this directive.

As shown in FIG. 5, the record RO* R1r R2 of track 5 is read from the magnetic disk device 4, and as shown by the arrow, the magnetic disk controller i! CPUI via 2
At the same time, it is also transferred to the cache memo IJ3 and stored there. When the Read 5ector No command is issued after the ReadR2:17 command, the magnetic disk controller i! 2, it is necessary to transfer the head position of the magnetic disk HR4 to the CPUI. The processing time required to transfer the head position is
Since it is longer than the gap time between records -R3r
It is not possible to transfer R4 to Rn to the cache memory 3 continuously, and after waiting for one revolution, for example, they are transferred to the cache memory 3 and stored. Therefore, it takes a long time to transfer and store the remaining records from the magnetic disk controller 4 to the cache memory 3, resulting in a decrease in the performance of the computer system.

Note that, as a known example related to this type of device, there is, for example, a technique described in Japanese Patent Application Laid-Open No. 60-73758.

[Object of the Invention J The object of the present invention is to solve such conventional problems and to
External storage control that allows the remaining records in the same track to be continuously transferred and stored in cache memory after transferring the specified record from U, eliminating rotational waiting time and improving performance. The goal is to provide a method.

[Summary of the invention]

In order to achieve the above object, the external storage control method of the present invention reads the record from the external storage device and transfers it to the host device at the same time when the record specified to be read from the host device does not exist in the cache memory. An external storage control device that transfers and stores the remaining records of the track to the cache memory after also transferring and storing them to the cache memory has a processor that runs two or more programs in parallel, and has a processor that runs two or more programs in parallel. The first program controls the process until the transferred records are transferred, and after the transfer, multiple programs are started, and the second program transfers and stores the remaining records other than the specified records in the cache memory. During this period, the response operation to the activation from the host device is controlled by the first program.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a magnetic disk control device showing one embodiment of the present invention. In Figure 1, 21 is for CP
A U interface section, 22 is a data transfer control section, 23 is a DKU interface section, 24 is a microprocessor section, and other symbols represent the same devices as the same symbols in FIG. 5. The CPU interface section 21 is a CPU interface section.
The data transfer control unit 22 performs processing such as data transfer and control information exchange between the magnetic disk controller 2 and the magnetic disk controller 2.
Controls data transfer between the PU, magnetic disk device, and cache memory. The DKU interface section 23 is
The path 25 is a data bus between the magnetic disk device 4 and the magnetic disk control device 2, and the path 25 is a data bus that transfers data and sends and receives control information to and from the magnetic disk device 4.
is a data bus between the magnetic disk control table [2 and the cache memory 3, and path 27 is a data bus between the magnetic disk control device 2 and the CPU 1. microprocessor 2
4 has a function that can run two microprograms (μPI, μP2) at the same time, and in that case, the
The μP1 controls the UI processing, and the magnetic disk device 4
and μP1 and μ for processing for cache memory 3.
The circumference of P2 is controllable. Further, the overall control of the magnetic disk control device 2 is performed by the μP 1, and when the CPU 1 requests a record that does not exist in the cache memory 3, the record is read from the magnetic disk device 4 and data transfer is controlled via the path 25. After being transferred to the data transfer control unit 22, the data is transferred to the CPUI via a path 27, and at the same time, it is also transferred from the data transfer control unit 22 to the cache memory 3 via a path 26. Control at this time is performed only by μP1.

Next, let us consider the processing of the command group shown in FIG. As shown in Figure 6, first, Read RotRea
d When R1 and Read R2 commands are issued.

The processing up to this point is performed only by μP1, and μP1
, controls processing of cache memory.

Next, when the command Read 5ector No.
2 and R3, the magnetic disk drive [
When CPUI determines that it does not need the data from 4, it activates the other μP2 and shifts to parallel running mode. As a result, the microprograms μP1 and μP2 run in parallel, and μP1 communicates with the CPU
While continuing to process the dSeehiorN o command, μP2 processes records R3 and R4-Rn.

20 is a timing chart showing the processing procedure of μP1 and μP2 in FIG. 1;

In the external storage control method of this embodiment, the configuration is such that two microprograms can be run simultaneously on the magnetic disk control table 2, and the CPU
One microprogram performs the processing with I, and the other microprogram performs the processing of transferring and storing records from the magnetic disk device 4 to the cache memory 3. With NIO, it is possible to transfer five records in a row without losing time due to waiting for rotation. In FIG. 2, in the magnetic disk device 4,
When the head is located at record RO of track 5, μP1 executes the Read RO command and reads C.
Transfer this record R to PU1 and do the same,
When the head is located at records R1+R2, these are read and transferred to CPU1. On the other hand, μP2 reads each record when the head is positioned at record Rav R4t...Rn, and passes through pass 25 and pass 2.
Transfer these records to cache memory 3 via 6 and store them (Load R3, R4="・Rn)
.

Also, during this transfer/storage operation, μpt is also operating, and in this embodiment, processing of the Read 5ector No. command issued following the Read R2 command is continued, and when the processing is completed, the CPU 1
It enters a scanning state that monitors startup from.

In this way, the magnetic disk controller i! 2 is equipped with two microprograms μPI and μP2, and by running them in parallel, records after the record specified by the CPU can be continuously transferred and stored in the cache memory 3, improving system performance. can be improved.

FIG. 3 is a block diagram of an external storage control device showing one embodiment of the present invention, showing a configuration that allows two microprograms to run simultaneously. In Figure 3, 30, 31, and 32 are flip-props, and 33
34 is a selection circuit, 35.36 is a microprogram address register, 37.38 is an AND circuit, and 39.40 is a register.

411 is a selection circuit, 42 is a decoder, and 43 is an arithmetic circuit. RS Blip Prop 30.31 each 5TAR
It is set by the TμP1 instruction and 5TARTμP2 instruction, and reset by the MULTIRUN instruction. Here, the instruction is a microprogram instruction. The RS flip-flop 32 is set by the 0 output of the flip-flop 30 and reset by the 0 output of the flip-flop 31.

Therefore, when the O outputs of the flip-flops 30 and 31 are both at high level, the state of the cellar 1 of the flip-flop 32 is inverted by the clock signal (CL○CK). Here, the clock signal (C: LOCK) is a signal that becomes LL I 11 for each microprogram cycle. Control memory 33 for storing microprograms
addresses are stored in the address registers 35 and 36, and one of these is selected by the selection circuit 34 and sent to the control memory 33 to access the microinstruction storage area. Address register 35 is μP
1 address register, and address register 36
is an address register for μP2, and when one output of the blip-prop 32 is at a high level, the address register 35 is selected, and when it is at a low level, the address register 36 is selected.

The microinstruction read from the control memory 33 is decoded by the decoder circuit 42, and part of the decoding result becomes the input to the address registers 35 and 36, and the other part becomes the A bus input to the arithmetic circuit 43. At the same time, the type of calculation of the calculation circuit 43 is specified (OP). On the other hand, the data stored in the registers 39 and 40 are selected by the selection circuit 4!1, and one of the data is input to the B bus of the arithmetic circuit 43. The result of the operation is output to the D bus and stored in either register 39 or register 40, one of which is designated by AND circuits 37 and 38. That is, the flip-flop 32
``If the condition is bad, the AND circuit 37 is opened and the result is stored in the register 39, and the flip-flop 32 is
If it is in the OH state, the AND circuit 38 flashes and the result is stored in the register 40.

Figure 4 shows the address register (IARl, 2) in Figure 3.
FIG. 4 is a diagram showing the selection state of the register (REGI, 2). In the initial state, only μP1 is running,
The 5TART μP2 command causes only μP2 to run.
Next, μP1 and μP2 run alternately by the MULTI RUN command.

That is, as shown in Figure 4, IARI for specifying μP1 is first selected as the address register, and REGI for storing the data of μP1 is selected as the register. The 5TARTμP2 instruction selects IAR2 as the address register and selects REG2 as the register. Further, by the MULTI RUN instruction, the address registers IARI and IAR2 are alternately selected, and the registers REGI and REG2 are alternately selected. In this way, it is possible to run two microprograms in parallel, and after transferring the specified record from CPU 1, the remaining records of that track are continuously transferred to the cache memory and stored. be able to.

〔Effect of the invention〕

As explained above, according to the present invention, two microprograms can be run simultaneously in the external storage control device. records can be transferred and stored in the cache memory, and as a result, the time for waiting for one revolution can be eliminated, making it possible to improve the performance of the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a magnetic disk control unit showing one embodiment of the present invention, and FIG. 2 is a block diagram of the microprogram μP1. A time chart showing the processing procedure of μP2,
3 is a block diagram of the microprocessor shown in FIG. 1, FIG. 4 is a diagram showing the selected state of the address register and data register in FIG. 3, and FIG. 5 is a block diagram of the magnetic disk subsystem programmer. 6th @ is a diagram showing an example of a command group issued from the CPU of FIG. 5. 1: CPTJ, 2: Magnetic disk control device, 3: Cache memory, 4: Magnetic disk device, 22: Data transfer control section, 21.21 Interface control section, 24: Microprocessor, 30, 31° 32: Flip-prop, 33: Control memory. 34.41: fi selection circuit, 43: arithmetic circuit, 42: decoder, 35.36: address register. Figure 1 4% Figure 2

Claims (1)

[Claims] (1) If a cache memory is provided and the record specified to be read by the host device does not exist in the cache memory, the record is read from the external storage device and transferred to the host device, and at the same time, it is also transferred to the cache memory. After storing, the external storage control device transfers and stores the remaining records of the track to the cache memory, and has a processor that runs two or more programs in parallel until the specified record is transferred to the host device. The first program controls the process, and after the transfer, multiple programs are started, and the second program controls the process of transferring and storing the remaining records other than the specified record in the cache memory. An external storage control system characterized in that a response operation to a startup from is controlled by the first program.