KR20030054985A - Apparatus for reduplication over warm standby system - Google Patents

Abstract

PURPOSE: A warm standby duplexer is provided to enable a CPU of an active board to store data at an interconnector, which records data at a memory of a standby board, at the same time as the CPU records the data at a memory so that it can duplex a system irrespective of an operating system. CONSTITUTION: The system comprises an active board(100) and a standby board(200). The active board(100) includes a CPU(110), a memory(120), an interconnection matcher(130), and an interconnector(140). The interconnection matcher(130) includes a direction controller(131), a latch(132), a decoder(133), and an approaching time matcher(134). The direction controller(131) controls a data flow according as the CPU or the interconnector(140) has a bus control right. The latch(132) temporarily stores data when the CPU(110) records the data at the memory(120). The decoder(133) decodes the address and the control signal output by the CPU(110) for making the address and the control signal approachable to a register of the interconnector(140) and the memory(120). The approaching time matcher(134) matches the time, when the CPU(110) approaches the memory(120), with the time, when the CPU(110) approaches the interconnector(140). The standby board(200) has the same structure as the active board(100), and the components of the standby board(200) also have the same functions as those of the active board(100).

Description

Warm standby redundancy unit {APPARATUS FOR REDUPLICATION OVER WARM STANDBY SYSTEM}

The present invention relates to a warm standby redundancy device, and more particularly, to a warm standby redundancy device suitable for implementing a duplication system independent of the operating system and minimizing the load of CPI in a real time system such as a mobile communication system.

In general, there are two methods of redundancy: cold standby, warm standby, and hot standby.

First, in the standby standby method, when a problem occurs in an active board in which a program operates and is replaced with a standby board, the standby board restarts the boot and executes the program.

In addition, the hot standby method is a method in which a program on a standby board operates without stopping at the same time when a problem occurs in an active board while a program is simultaneously operated on an active board and a standby board.

In addition, the warm standby method is a method in which a program is stopped for a replacement time, but a standby board is changed to an active board, so that the program of the currently active board corresponding to the stopped portion of the program of the previous active board is executed.

In this case, the warm standby method includes data written in the memory of the active board and the standby board by two processes: dual copy (hereinafter referred to as dual write) and parallel write (hereinafter referred to as parallel write). Match the data recorded in the memory.

The dual write is a process of writing data written in the memory of the active board to the memory of the standby board.

In addition, parallel writing is a process of writing the changed data in the memory of the standby board when the data of the memory is changed while the program of the active board is executed.

The two processes will be described in detail with reference to FIG. 1 as follows.

First, when the system boots, one of the redundant boards becomes the active board 10 and the other becomes the standby board 20. In this case, the active board 10 performs an operating system and an application program.

The active board 10 then writes the operating system to the standby board 20, which is referred to as operating system dual recording.

The standby board 20 reboots into the copied operating system and requests an application program from the active board 10. Accordingly, the active board 10 writes the application program to the standby board 20, which is referred to as application program double recording.

Thereafter, when the data recorded in the memory 12 of the active board 10 is changed, the changed data is simultaneously written to the memory 22 of the standby board 20. This process is called a parallel record.

Here, when a hardware problem occurs in the active board 10, the data stored in the register of the active board 10 is written to the register of the standby board 20, and the active board 10 reboots.

At this time, the standby board 20 performs a command corresponding to the address stored in the program counter.

Therefore, when a problem occurs in the active board 10 and is replaced by the standby board 20, the data of the memory 12 of the active board 10 and the data of the memory 22 of the standby board 20 are the same, and the standby board 20 is identical. If the data stored in the register of 20 is the same as the data stored in the register of the active board 10, the standby board may continuously execute the program of the active board without interruption.

However, in the prior art, the base address used when the system is not operated with redundancy and the base address used when the system is operated with redundancy (when dual recording and parallel recording are performed) are used differently. .

In addition, since there is a close relationship with the operating system, there is a problem that the conventional duplication method cannot be used when changing to another operating system.

In addition, since the CPI of the active board (CPU: denoted CPI) performs a double recording, there is a problem that the CPI load increases.

Accordingly, the present invention has been made in view of the above problems, in which the data is written to the interconnector, which serves to store the time when the CPI accesses the memory in the active board and the data in the memory of the active board in the memory of the standby board. The purpose is to provide a warm standby redundancy device independent of the operating system by minimizing the linkage with the operating system by controlling the flow of data between the active board and the standby board by matching the set time.

1 is a block diagram showing the configuration of a conventional redundancy apparatus.

Figure 2 is a block diagram showing the configuration of the present invention warm standby redundant device.

FIG. 3 is an exemplary diagram illustrating a condition under which each component of FIG. 2 operates. FIG.

4 is an exemplary diagram illustrating types of input / output signals of the decoder of FIG. 2.

5 is an exemplary view illustrating types of input / output signals of the direction controller of FIG. 2.

FIG. 6 is an exemplary view illustrating types of input / output signals of the latch of FIG. 2. FIG.

** Explanation of symbols for main parts of drawings **

100: active board 110, 210: CPI oil

120, 220: memory 130, 230: interconnection combiner

131, 231: direction controller 132, 232: latch

133, 233: decoder 134, 234: access time matcher

200: standby board

The present invention for achieving the above object is a direction controller for controlling the flow of data according to the CFI or interconnector having a bus control right; A latch for temporarily storing the data when the CPU writes the data into a memory; A decoder for decoding the address and the control signal output from the CPI so that they are accessible to a register of the interconnector or the memory area; And the access time matcher for matching the time when the CPU accesses the memory with the time when the interconnector is accessed.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

The type of interconnector depends on the type of CPI. For example, if the PC is a Power PC, the interconnect uses a PCI bridge (PCI Bridge).

Here, the interconnector shall have the following functions.

First, registers on the interconnector and memory on the standby board must be accessible to different addresses. That is, it should have two or more images.

In addition, one of the bus interface functions should be the bus master function.

And, regardless of CPI, the memory must be directly accessible. Therefore, the load of the seed oil is reduced when the double recording is performed.

The present invention implements a warm standby redundancy device using a Tunsund PowerSpan chip having the above functions.

Figure 2 is a block diagram showing a warm standby redundant device of the present invention, the direction controller 131 for controlling the flow of data in accordance with the CFI 110 or the interconnector 140 has a bus control rights, When the CPI 110 writes data to the memory 120, the latch 132 temporarily stores the data, and the address and the control signal output from the CPI 110 are stored in the register of the interconnector 140 or the Decoder 133 for decoding the memory 120 region accessible, and access time matcher 134 for matching the time that the CPI 110 accesses the memory 120 and the time to access the interconnector 140. An active board (100) composed of; The direction controller 231 controls the flow of data according to the CPI 210 or the interconnector 240 having the bus control right, and the time when the CPI 210 approaches the memory 220 and the interconnector 240. An embodiment of the present invention will be described as being composed of a standby board 200 composed of an access time matcher 234 for matching a time to approach.

When power is applied to the system, assume that the booting side is the active board 100 first, and the booting side is the standby board 200.

First, the active board 100 writes data stored in the memory 120 to the memory 220 of the standby board 200 through the interconnector 130 and the interconnectors 140 and 240. Through this, the active board 100 performs a double write.

At this time, in performing the double recording, using a DM (Direct Memory Access, hereinafter referred to as a DM) controller it is possible to perform the double recording regardless of the CAPI.

Here, the case where the dual recording is performed in the case of using the DM and the case of not using the DM will be described in detail with two examples.

First, when using a DM, the interconnector 140 (powerspan) outputs a signal (BR: Bus Request) requesting the use of the bus to the bus arbiter.

The bus arbiter outputs a signal to the interconnector 140 (powerspan) to permit use of the bus (BG).

After the execution of these two processes, the interconnector 140 (powerspan) of the active board 100 reads data from the memory 120 to read the data from the standby board 200 through the PCI Bus (Pipheral Component Interconnect Bus). Output to interconnector 240 (powerspan).

Thereafter, the interconnector 240 (powerspan) of the standby board 200 requests the bus arbiter (Bus Arbiter, hereinafter referred to as bus arbiter) to use the bus and obtains a bus grant. Record the data in).

In another case, when the DM is not used, the duplex recording is performed in the following order.

First, the CPI 110 of the active board 100 reads data from the memory 120 and outputs the data to the interconnector 140 (powerspan). Then, the interconnector 140 (powerspan) reads data from the memory 120 when receiving a bus permission signal from the bus arbiter through the PCI bus interconnector 240 (powerspan) of the standby board 200 )

Thereafter, the interconnector 240 (powerspan) of the standby board 200 requests the bus arbiter to use the bus and writes data to the memory 220 when the bus permit is obtained.

In the above, the order in which the dual recording is performed has been described, and in the following, the order of performing parallel writing will be described.

The interconnector 130 of the active board 100 equally matches the time that CPI 110 approaches the memory 120 and the interconnector 140 (powerspan).

The interconnection combiner 130 prevents data from being output from the interconnector 140 (powerspan) when the CPI 110 reads the memory 120.

In addition, the interconnector 130 outputs an acknowledgment signal (TA in PowerPC) output from the interconnector 140 (powerspan) when the register of the interconnector 140 (powerspan) is accessed. This recognition signal is not output when parallel recording is performed.

Conversely, the interconnector 230 of the standby board 200 does not perform any operation but merely transfers data.

Subsequently, when a problem occurs in the active board 100, the DM controller of the interconnector 140 reads the data stored in the register of the CPI 110 from the CPI 210 of the standby board 200. In the register).

Therefore, the standby board 200 can operate as the active board 100.

Hereinafter, the interconnection combiners 130 and 230 having different operations in the active board 100 and the standby board 200 will be described in detail with reference to FIGS. 3 to 6.

First, the decoders 133 and 233 may output an address (CAS: CPU_Address_Signal decoded into PSAS: PowerSpan_Address_Signal), data (CDB: CPU_Date_Bus), and a control signal as shown in FIG. 4. (CCS: CPU_Control_Signal decoded to PSCS: PowerSpan_Control_Signal, CBR: CPU_Bus_Request decoded to PowerSpan_Bus_Request, CBG: CPU_Bus_Grant decoded to PSBG: PowerSpan_Bus_Grant). It maps to the area of memory (synchronous DRAM).

Here, the direction controllers 131 and 231 may be used when the system is not redundant as shown in FIG. 3, the system is redundant and the standby board, the interconnector has a bus right, or the interconnector (powerspan). 5 is operated when reading the register of CPI, the signal output from the CPI (110) 210 when using the bus (CCS: CPU_Control_Signal, CAB: CPU_Address_Bus, CDB :) CPU_Data_Bus) is output to interconnectors 140, 240 (powerspan) and outputs from interconnectors 140, 240 (powerspan) when interconnectors 140, 240 (powerspan) uses a bus. The output signals PSCS: PowerSpan_Control_Signal, PSAB: PowerSpan_Address_Bus, and PSDB: PowerSpan_Data_Bus are outputted to the CAPI 110 and 210.

At this time, the above process is performed according to the OC (Output_Enable_Control) signal is active and the on / off of the DC (Direction_Control) signal.

In other cases, when reading data from a memory (synchronous DRAM: synchronous DRAM), the interconnector 130 and 230 make the input signal high impedance without performing any operation.

In another case, the latches 132 and 232 are shown in FIG. 3, when the CPI 110 and 210 of the active board become the master and write to the memory (synchronous DRAM) 120 and 220. 6 and temporarily store the address (CAB: CPU_Address_Bus), the data (CPU_Data_Bus), and the control signal (CPU_Control_Signal) output from CPI 110 and 210, as shown in FIG. Outputs data and control signals (PSCS: PoweSpan_Control_Signal, PSAB: PowerSpan_Address_Bus, CDB: CPU_Data_Bus) to the span).

In this case, at least four data may be stored in the latches 132 and 232 in consideration of the operation of the burst mode of the memory.

In addition, the operation of outputting the information stored in the latches 132 and 232 to the interconnectors 140 and 240 (powerspan) may be performed by the interconnectors 240 and 140 (powerspan) accessing the registers. The process continues until an end signal is outputted.

In another embodiment, the same redundancy system can be implemented using a PC-X or other bus scheme without using a PC-I bridge in the interconnect.

As described in detail above, the present invention matches the time of accessing the memory and the time of the interconnector to the warm-up duplication system even in a system using a commercial operating system with minimal correlation with the operating system used in the system. There is an effect that makes it easy to implement.

In addition, when data is repeatedly recorded on the active board and the standby board, the interconnector can directly write data to the memory of the standby board without passing through the active board's CPU, thereby reducing the load on the CPU of the active board.

In addition, the use of PCI buses in the interconnector can increase the reliability of the bus. For example, parity check is possible when an error occurs in the redundant bus, so it is easy to determine the cause of the error.

Claims (4)

A direction controller that controls the flow of data as the CAPI or interconnector has bus control; A latch for temporarily storing the data when the CPU writes the data into a memory; A decoder for decoding the address and the control signal output from the CPI so that they are accessible to a register of the interconnector or the memory area; Warm standby redundancy device, characterized in that configured to duplicate the board configured to include the access time matcher for matching the time when the CPI accesses the memory and the time to access the interconnector. The latch of claim 1, wherein the latch is operated when the system writes data to the memory when the system is redundant and the board operates as an active board, and temporarily stores the address, data and control signals of the CPU and output them to the interconnector. A warm standby redundancy apparatus, characterized in that configured to be capable of storing a predetermined number or more of data when the data recording mode is a burst mode. 3. The warm standby redundancy apparatus of claim 2, wherein the operation of writing data stored in the latch to the interconnector is configured to continue until access of the register of the interconnector is terminated. The warm standby redundancy apparatus of claim 1, wherein the access time matcher is configured to facilitate the use of a memory having a different waiting time for data recording by matching the time that CPI writes to the memory with the time that is written to the interconnector. .