JPH0235542A - Transfer control system for disk cache data - Google Patents

Abstract

PURPOSE:To shorten an access time by providing load end flags by blocks and setting a flag every time the block is loaded completely. CONSTITUTION:A target block of data is transferred between a channel device 3 and a disk device 7 and the block is saved even on a cache memory 5. When the data transfer is completed, the load completion flag 62 of the block is set to 1 and the command end is reported to the channel device 3. Then the load completion flag 62 is set to 1 every time a block is loaded until the whole track is loaded. Then a hit result is obtained when a read, write or search command is issued, the load completion flag 62 of a target block is read in and checked. When loading is completed, data transfer is performed between the channel device 3 and cache memory 5 and the command end is reported to the channel device 3, thus finishing the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer control method for a disk cache, and particularly to a data transfer control method for a disk cache that handles cache memory on a trunk-by-trunk basis.

[Prior Art] A disk cache is one of the things that improves the effective performance of a disk device. A disk cache is placed between a disk device and a main storage device. A copy of data from the disk device is placed in the cache memory, and the central processing unit receives a read command or command to transfer data from the disk device to the main storage device. When a write command is issued to transfer data from the main memory to the disk device, a read command or By terminating the RIE 1 to command, the track positioning (seek) time for positioning to the target block on the disk device and the disk rotation waiting time are eliminated, thereby speeding up the input/output processing.

Conventionally, two types of copying of data to a cache memory are often used: track by track and block by block. Here, ``Block J is usually a unit of logical records from the CPU side.

The number of blocks included in one track of the disk device is 9.
It is about 5. If the target data is not in the cache memory when a read or write command is issued as an opportunity to move data from the disk device to the cache memory,
At the same time that the target data is transferred from the disk device to the main memory, the data is also transferred to the cache memory, and the data is continuously transferred in units of tracks (all of one track) or units of several blocks (from the load start record to the last record of the track). In this case, data is often moved to a cache memory.The amount of data required by one instruction varies, sometimes being less than one track, sometimes several tracks worth.

Hereinafter, the operation of moving (writing, copying) data from the disk device to the cache memory will be referred to as loading.

The reason for moving adjacent data that has been read/written in units of tracks or in units of several blocks to the cache memory is that the probability of it being accessed next is considered to be high.

Loading in blocks allows for fine-grained data management because the unit of read/write commands from the central processing unit is a block, but on the other hand, when variable-length blocks are targeted, managing the empty area of blocks in the cache memory becomes complicated. Become. Therefore, block-by-block loading is suitable for fixed-length blocks. A known example of loading such fixed-length blocks is disclosed in Japanese Patent Application Laid-Open No. 55-1570.
There is something like the one described in Publication No. 56.

In addition, track units are easy to handle when loading variable-length blocks, and are used in many disk caches. One of the known examples is shown in Japanese Unexamined Patent Publication No. 16257/1983.

[Problems to be Solved by the Invention] An example of loading in units of tracks will be described below with reference to FIG. 3. Note that in this specification, "record ROJ, etc." refers to a physical record on a disk, and is treated as having the same meaning as the above-mentioned "block."

Figure 3 shows one track spread out in a row, and the track has the home address (HA), record O (RO)
Below are record 1 (R1), record 2 (R2)
, record 3 (R3) are recorded sequentially, and formatting is performed up to the final record L (R, , ). If the trunk containing the record does not exist in the cache memory when a read command for record 2 is issued from the central processing unit, record R2 is read from the disk device and simultaneously sent to the main storage and cache memory, and After returning the completion report, continue from R3 to RL and HA, R.
The entire track up to O and R1 is loaded from the disk device to the cache memory. Depending on the cache memory management method, it may be possible to only load from R3 to the last track record R. Conventionally, when the next read/write command is issued for the record currently being loaded, the loading of the entire track is completed. It was necessary to make the read/write command wait until the read/write command was executed. In particular, since read/write commands for sequential access files are accessed sequentially in the order of records R2 and R3, there is a high probability that an error will occur when the loading is completed.

If the block length is short, the time to load the entire track is the time required for one rotation of the disk, and this is one factor that hinders the improvement of disk cache access performance when the load is completed.

The purpose of the present invention is to enable high-speed access by making it possible to execute the next read/write command for a block to be loaded that was issued during a load operation for a previous read/write command without having to wait until the entire track has been loaded. Disk cache transfer! Our goal is to provide an IJ control method.

[Means for Solving the Problems] In order to achieve the above object, the cache memory data transfer control method of the present invention provides a flag indicating that the loading is completed for each block, means for storing load completion flags corresponding to at least the number of blocks possessed by each trunk for each track to be loaded; A first means of resetting all the Makki load completion flags corresponding to a block (indicating an unloaded state), and setting the load completion flag corresponding to the block each time the loading of each block is completed (of the block and a second means (indicating loading completion).

Also, when the central processing unit issues the next read/write command to the block in the track that is being loaded,
A third means is provided to immediately execute the read/write command when the load completion flag is set to a load completion state, and to make the read/write command wait when the load completion flag is reset.

Furthermore, when the read and write commands are made to wait by the third means, the fourth means requests the host device to issue the command again by detecting the point in time when the loading of the target block is completed. Equipped with means for

The means for storing the load completion flag may be provided in a cache memory, a directory memory, or other memory.

[Effect] The effect based on the above configuration will be explained.

Read/write from central processing unit
When the command is issued and the target data does not exist in the cache memory, the first means resets all the load completion flags of the track. Then, data is transferred between the disk device and the main storage device, and the data is also transferred (loaded) to the cache memory. After the transfer of the target data is completed, the load completion flag for the block is set, and data continues to be loaded from the disk device to the cache memory. During loading, each time the loading of each block is completed, the second means sets the loading completion flag of the block. When the loading of the entire track is completed, the loading completion flag of the entire block in the track is set.

The next read/write command is issued during loading.

If the target block has been loaded, the third means immediately executes the processing between the cache memory and the main memory, and if the load has not been completed, the third means makes the read/write command wait. .

(If cache control is performed at a level below the disk controller, you can wait by retrying the command.) Wait for the load to complete, and when the block is finished loading,
The fourth means requests reissue of the read/write command again to perform transfer between the main storage device and the cache memory. By performing such control, a read/write instruction aimed at a block within a track that is being loaded can be executed on the cache memory with minimal waiting time.

[Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is an example of a system configuration to which the present invention is applied. This system configuration example includes a central processing unit 1 that instructs a channel device 3 to read/write a read/write command as a channel command word (CCW), a main storage device 2, and a CCW received from the central processing unit 1.

a channel device 3 that issues commands to the disk control device 4; a cache memory 5; a directory memory 6 that stores track unit information stored in the memory 5;
A disk control device 4 that controls these cache memories 5 and direct memories 6 and also takes charge of transfer control between the channel 3 and the disk devices 7, and a disk device 7 that has a much larger capacity than the cache memory 6.
It consists of In this embodiment, the effects of the present invention are not lost even if the cache memory 5 and directory memory 6 are placed at the level of the disk control device 4 or anywhere between the main storage device 2 and the disk device 7. In addition, the directory memory 6 may be included in the cache memory 5. In order to maximize the effects of the present invention, the directory memory 6 may be included in the data transfer between the main storage device 2 and the cache memory 5, and the data transfer between the cache memory S and the disk device 7. Data transfer can be performed simultaneously and independently.

FIG. 1 shows a disk controller 4 and a directory memory 6.
FIG. The disk control device 4 includes a channel transfer control section 41 that controls data transfer between the channel device 3 and the cache memory 5, and a device transfer control section 42 that controls data transfer between the disk device 7 and the cache memory 5. and have microprograms 411 and 421, respectively. Any number of microprocessors may be used to execute these microprograms. The directory memory 6 is a memory that stores track-by-track control information of the cache memory 5, and is accessed by the channel transfer control unit 41 and device transfer control unit 42 via controls 3601 and 602, respectively. The bit/miss determination table 61 shows that when the command sent from the channel device 3 is a read or write command, the target track exists in the cache (bit: the target track area is secured in the cache but the loading is not completed). This is a table for determining whether a case is included (includes a case) or does not exist (miss). Load completion flag 6
2 is a flag that indicates completion/incomplete of loading for all blocks from home address HA 7) 1 to maximum record Rmax for each track stored in the cache memory 5; here, it is reset to O when loading is not completed;
It is set to 1 when loading is completed.

FIG. 4 shows a schematic execution flow of read/write/search commands.

The operation will be explained below with reference to FIGS. 4(a) and 4(b).

The channel transfer control unit 41 uses a hit/miss determination table 61
(step 1002), and checks whether a track containing the target block exists in the cache (step 1003).

In the case of a miss, the relevant track area is secured in the cache memory, and at the same time, the load completion flag 62 is reset for all broncs (step 1004) (the first
means).

Next, the data of the target block is transferred between the channel device 3 and the disk device @7, and at that time, the block is also stored in the cache memory 5 (step 1005). When the data transfer is completed, the load completion flag for the block is set to 1.
is set, and a command completion report is sent to the channel device 3 (step 1006). Thereafter, the load completion flag is set to 1 each time a block is loaded until the entire track is loaded (step 1007゜1).
008) (the second means), when the loading of the entire track is completed (step 1009), the bit/miss determination table 61 and other tables (cache memory start address, data size, cylinder number, etc.) are A load completion status is set for the slot management table (for example, a slot management table that manages the data) (step 1010).

On the other hand, if it is a hit when the read/write search command is issued (step 1003), the load completion flag 62 of the target block is read and checked. If the loading has been completed (step 1021), data is transferred between the channel and the cache memory (step 1022), a command completion report is returned to the channel device 3, and the process ends (step 1023).

Further, if the loading of the target block is not completed (step 1021), the channel data transfer control unit 41 reports the command retry to the channel device 3.
031), make the command wait (the third means)
. During this time, the channel control unit 41 monitors whether or not the load completion flag of the target block is set.
O32), upon being set, requests the channel device 3 to reissue the command (step 1033) (the fourth means).

The channel data transfer control unit 41 monitors the setting of the target block load completion flag 62 (step 1032).
The setting of the load completion flag 62 (step 1008) is performed by the device data transfer control unit 42, and by allowing each control unit to execute processing independently and simultaneously, the waiting time for load completion can be minimized. be able to.

According to this embodiment, by setting a load completion flag for each block, a block that has been loaded can be accessed immediately, and there is no need to wait for the entire track to be loaded, thereby shortening the access time. Note that cache memory and directory memory can have a large capacity, so if these memories are used, the storage area for the load completion flag can be easily secured.

[Effects of the Invention] As described above in detail, according to the disk cache data transfer control method of the present invention, a load completion flag is provided for each block, and when starting loading into the cache memory in units of tracks, The load completion flag corresponding to all blocks is reset, and the flag is set each time the loading of successive blocks is completed.
While data is being loaded from the disk device to the cache memory, the next read/write is performed on the block in the trunk.
When a write instruction is issued, the wait time for the instruction to complete loading can be significantly shortened, resulting in a reduction in the access time to the subsystem and an improvement in the throughput of the entire system. be effective.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing details of an embodiment of the present invention, Fig. 2 is a system configuration diagram of an embodiment of the present invention, and Fig. 3 is an explanation of loading in units of tracks. Figure 4(a)(b)
) is a flowchart showing the operation of an embodiment of the present invention. 1-...Central processing unit, 2...Main storage device,
31. . ... Channel device, 4 ... Disk control device, 5 ... Cache memory, 6 ... Directory memory. 7...Disk device, 41...Channel transfer control unit, 42...Device transfer control unit, 4
11...Channel side microprogram, 421
...Device side microprogram, 61...
...Hit/miss judgment table, 62...Load completion flag. Figure 3 Loading completed

Claims (1)

[Claims] 1. A main storage device, a disk device having a large number of tracks and each track consisting of a plurality of blocks, and a cache memory that holds a copy of the disk device in units of tracks, and a central processing In response to a read/write command for the block from the device, if a track containing the target block exists in the cache memory, data is transferred between the cache memory and the main storage device, and the track containing the target block is transferred. does not exist in the cache memory, in a disk cache data transfer control method in which data is transferred between the disk device and the main storage device and data is loaded from the disk device to the cache memory, each means for storing, for each track to be loaded into the cache memory, at least as many load completion flags as the number of blocks possessed by each track, the flag indicating that the loading is completed for each block; and a first means for resetting all the load completion flags corresponding to the blocks in the track to be loaded when starting loading from the device to the cache memory in track units; and second means for setting the load completion flag. 2. When the next read/write command is issued from the central processing unit to the block in the track being loaded,
and third means for immediately executing the read/write command when the load completion flag is set to a load completion state, and causing the read/write command to wait when the load completion flag is reset. 2. The disk cache data transfer control method according to claim 1. 3. After making the read/write command wait by the third means, a fourth method requests the host device to issue the command again by detecting the point in time when the loading of the block is completed. 3. The disk cache data transfer control system according to claim 2, further comprising means.