JPH0876940A - Method for controlling disk array - Google Patents

Abstract

PURPOSE: To reduce the overhead of hardware, to shorten the occupation time of a system bus and to improve the performance of the system bus by shortening writing penalty time generated at the time of updating disk data. CONSTITUTION: After acquiring occupation right for the system bus 4 from a central processing unit(CPU) 2, a system bus control part la starts DMA transfer. Simultaneously with the start of DMA transfer, the seak/rotation waiting of four data disks 5a to 5d and a parity disk 5e is started. Then data from a main storage device 3 are DMA-transferred to a data buffer 1b through a system bus 4 and the control part 1a. After the DMA transfer, the system bus 4 is released. The data transferred to the data buffer 1b are transferred to an array control part 1c and striped to four sectors and the striped data are transferred to the data disks 5a to 5d. A parity generating/checking part 1d generates a parity and tranfers the parity to the parity disk 5e.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array control method, and in particular, by reducing the write penalty time that occurs when updating disk data, hardware overhead is reduced, and the main memory and disk array are further reduced. The present invention relates to a disk array method suitable for shortening an occupied time of a system bus with a control device to improve the performance of the system bus and realizing high-speed data transfer.

[0002]

2. Description of the Related Art As a conventional technique, “Nikkei Electronics” No. 26, April 26, 1993. 579 77th
"Disk array device: Improving performance and key to distributed system" from page 103 to page 103 is known. According to the above conventional technique, in the disk array control device, parity is generated by a plurality of data disks,
Writing to one parity disk. For this reason,
When updating the data written on the data disk,
At the same time, the parity disk must be updated.

For example, in a disk array control device composed of four data disks and one parity disk, the parity disk is updated even when only the data stored in one data disk is updated. It is necessary to read the data stored in the remaining three data disks. The time generated for this is called a write penalty time, and is a hardware overhead time peculiar to the disk array device generated at the time of data writing.
This time is a fatal defect of the disk array device, and shortening this time has been one of the methods for improving the performance of the disk array device.

Conventionally, after reading data from four data disks, update data is read from the main storage device,
Was generating parity. After that, the data was transferred to the data disk and the parity was transferred to the parity disk.

However, in such a method, data read, update data read, parity generation, and data disk write are sequentially executed, so that the write penalty time becomes the hardware overhead time as it is. It was In particular, in the RAID 3 level disk array control device, when all the disks are accessed at the same time, when updating small-capacity data of a data disk, the ratio of the write penalty time becomes larger than the transfer time of the update data. There was a problem.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and particularly to shorten the write penalty time that occurs when updating disk data in a disk array controller. The hardware overhead is reduced, the system bus occupied time between the main memory and the disk array controller is shortened, the performance of the system bus is improved, and high-speed data transfer is realized.

[0007]

The disk array control method of the present invention is applied to a computer system including a central processing unit, a main storage device, a disk array control device, and a magnetic disk array. In particular, when updating data is recorded on the data disk in the magnetic disk array, the exclusive right of the system bus used for data transfer is secured between the main memory and the disk array controller, and the disk array controller is activated. Then, the first step of setting the seek / rotation wait state is performed, and the update data read from the main storage device is transferred to the data buffer in the disk array control device via the system bus,
Then, a second step of releasing the exclusive right to the system bus, and a third step of reading a plurality of data for generating parity together with update data from a corresponding data disk in the magnetic disk array and transferring the data to the data buffer. , Store at least the updated data in the corresponding data disk in the magnetic disk array, generate parity data based on the updated data and non-updated data stored in the data buffer, and store the parity data in the parity disk in the magnetic disk array. It is characterized by comprising a fourth step.

[0008]

According to the present invention, the update data can be transferred from the main memory to the data buffer during the seek / rotation wait time of the non-updated data, and the write penalty time which is the time for parity generation can be shortened. Is possible,
As a result, hardware overhead can be reduced and the system bus occupancy time between the main memory and the disk array controller can be shortened, system bus performance is improved, and high-speed data transfer is realized. can do.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a computer system using a magnetic disk array controller to which the present invention is applied. In FIG. 1, the disk array control device 1 is
It is connected to the central processing unit 2 and the main memory 3 via a system bus 4. The magnetic disk array 5 is composed of magnetic disk devices 5a to 5e. The magnetic disk devices 5a to 5d are data disks that store file data, and the magnetic disk device 5e is a parity disk that stores parity. These magnetic disk devices 5a to 5e are connected to the disk array control device 1 via a magnetic disk bus 6. The access unit of each of the magnetic disk devices 5a to 5e is one sector, and the parity of one sector is generated from the data of four sectors. With these, a magnetic disk array 5 of 4 data disks and 1 parity disk is configured. Here, one sector is 512 bytes.

In the disk array controller 1, the system bus controller 1a controls DMA transfer between the system bus 4 and the data buffer 1b. Data buffer 1
b is a portion that absorbs the difference between the data transfer rate of the system bus 4 and the data transfer rate of the magnetic disk array 5.
At the time of data transfer (data write) from the main storage device 3 to the magnetic disk array 5, data is transferred to the system bus control unit 1.
The data is once written in the data buffer 1b from a and then transferred to the array control unit 1c. Data transfer from the magnetic disk array 5 to the main memory 3 (data read)
At this time, the data is once written from the array controller 1c to the data buffer 1b and then transferred to the system bus controller 1a.

The array controller 1c includes a data buffer 1b.
And data transfer between the data disks 5a-5d. At the time of data writing, striping of 2048 bytes of data into 4 sectors is performed to each of the data disks 5a to 5d.
Transfer to Further, at the time of data reading, four sectors are read from four data disks 5a to 5d at one time, and 20 sectors are read.
The data of 48 bytes is converted and transferred to the data buffer 1b.

The parity generation / check unit 1d generates parity and transfers it to the parity disk 5e when the data of 4 sectors striped in the array control unit 1c passes. In addition, the data disks 5a-5
A parity check is performed on the data from d using the data on the parity disk 5e.

The mask control unit 1e masks unnecessary data among the data from the array control unit 1c to the data buffer 1b so as not to be written in the data buffer 1b.

The hardware of these control devices is controlled by a micro program.

The operation of each unit will be described below with reference to the time charts shown in FIGS.

First, the operation during 4-sector write will be described with reference to FIG. The system bus control unit 1a acquires the exclusive right of the system bus 4 from the central processing unit 2 and then
A Transfer is activated. At the same time when this DMA transfer is activated, 4
Data disks 5a to 5d and parity disk 5
e seek and rotation waiting starts. Next, the main storage device 3
The 2048 bytes of data A, B, C, D from are transferred to the data buffer 1b by DMA via the system bus 4 and the system bus controller 1a. At this point, the system bus 4 is released.

The data transferred to the data buffer 1b is transferred to the array controller 1c and striped into four sectors. After this, seek and rotation were waiting 4
Data disks 5a to 5d and parity disk 5
Access to e is activated. Then, the striped 4-sector data A, B, C, and D are simultaneously transferred to the data disks 5a to 5d, respectively. When these data A, B, C and D pass through the parity generation / check unit 1d, parity is generated and transferred to the parity disk 5e.

In the prior art, as shown in FIG. 4, the seek / rotation wait of the four data disks 5a-5d and the parity disk 5e is performed after the data A, B, C and D are stored in the data buffer 1b. Since it was started, the hardware overhead time was long. Further, although not shown, in the prior art, before starting the system bus 4, the seek / rotation wait of the four data disks 5a to 5d and the parity disk 5e and the data A, B, C, and
Since the D was stored in the data buffer 1b, the hardware overhead time was long.

Next, the operation during one sector write will be described with reference to FIG. The system bus control unit 1a is the system bus 4
After acquiring the exclusive right of the CPU from the central processing unit 2, the 512-byte (1 sector) update data B ′ from the main memory 3 is DMA-transferred to the data buffer 1b via the system bus 4 and the system bus control unit 1a. . At this point, the system bus 4 is released.

Simultaneously with the start of the DMA transfer, the data A, B, of 4 sectors including the data before the update of 1 sector described above.
Reading from the C and D data disks 5a to 5d is activated, and the data disks 5a to 5d are in a seek / rotation waiting state. During the seek / rotation wait time when accessing the data A, B, C, D of the four sectors, the DMA transfer is completed and the update data B'is stored in the data buffer 1b first. After that, when the data A, B, C, and D of four sectors are transferred to the data buffer, the mask control unit 1e masks the update data B ′ of one sector that was previously DMA-transferred so as not to be overwritten. 2 in data buffer 1b
When 048 bytes (4 sectors) of data A, B ', C, D have been collected, the data A, B', C, D are transferred to the array controller 1c. The data A, B ', C, D transferred to the array controller 1c is divided into 4 sectors and transferred to the data disks 5a-5d via the magnetic disk bus 6. At this time, the parity is simultaneously generated and transferred to the parity disk 5e via the magnetic disk bus 6.

According to the above embodiment, when the system bus is activated, the seek and
Since the rotation wait is started and only the update data is transferred to the data buffer first from the main memory, the write penalty time and the hardware overhead can be shortened, and the main memory and the disk array can be further reduced. Since the occupied time of the system bus with the control device can be shortened, the performance of the system bus can be improved. The present embodiment is particularly useful for shortening the write penalty time that occurs when the small capacity data of the data disk is updated by the disk array control device.

[0023]

According to the present invention, in the disk array controller, the hardware overhead is reduced by shortening the write penalty time generated when updating the disk data, and the main memory device and the disk array controller are controlled. It is possible to shorten the occupation time of the system bus with the device, improve the performance of the system bus, and realize high-speed data transfer.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system using a magnetic disk array control device to which the present invention is applied.

FIG. 2 is a time chart showing the operation of the computer system shown in FIG.

FIG. 3 is a time chart showing the operation of the computer system shown in FIG.

FIG. 4 is a time chart showing the operation of a computer system according to the related art.

[Explanation of symbols]

1 ... Disk array controller, 1a ... System bus controller, 1b ... Data buffer, 1c ... Array controller, 2 ...
Central processing unit, 3 ... Main memory unit, 4 ... System bus, 5
... magnetic disk array, 5a-5d ... data disk,
5e ... Parity disk, 6 ... Bus for magnetic disk.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nekatsu Fukaya 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Stock Company Hitachi Office Systems Division

Claims (1)

[Claims] 1. A disk array control method for a computer system comprising a central processing unit, a main memory, a disk array controller and a magnetic disk array, wherein update data is recorded on a data disk in the magnetic disk array. In this case, the first step is to secure the exclusive right to the system bus used for data transfer between the main memory device and the disk array control device, and activate the disk array control device to put it in a seek / rotation wait state. , The second step of transferring the update data read from the main memory device to the data buffer in the disk array controller via the system bus, and then releasing the exclusive right to the system bus, and generating the parity together with the update data Read multiple data from the corresponding data disk in the magnetic disk array Then, the third step of transferring to the data buffer, at least the update data is stored in the corresponding data disk in the magnetic disk array, and the parity data is stored based on the update data and the non-update data stored in the data buffer. And a fourth step of generating and storing in a parity disk in the magnetic disk array.