JPH05151094A - Backup control system of file high-speed writing mechanism - Google Patents

Abstract

PURPOSE:To minimize the loss of data by holding data before process interruption even if a process is interrupted owing to a power failure, etc., during a writing process by the DASD high-speed writing mechanism. CONSTITUTION:A DASD controller 2 is provided with a cache memory 4, a nonvolatile cache memory 5, a memory controller 6, and a nonvolatile memory 7 and when data are written, the write data are inputted to the nonvolatile memory 7 temporarily and written back to the cache memory 4 and nonvolatile cache memory 5. In this case, an address plus the number of transfer bytes are written in a control part C, and the write data are stored in a data area D; and the transfer completion flag of a flag part F is set and the data are written back to the cache memories 4 and 5 successively. Then a transfer completion flag is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup control system in a file high-speed writing mechanism used for DASD (Direct Access Storage Device) such as a magnetic disk subsystem.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional DASD control device, and FIG. 6 is an explanatory view of a conventional data write process.

In the figure, 1 is a channel, 2 is a DASD control device, 3 is a DASD (for example, a magnetic disk device), 4 is a cache memory, 5 is a non-volatile cache memory, and 6 is a memory controller.

CA is a channel control unit, D
A is a device control unit, SSP is a memory port,
CIL is a channel interface unit, BIL is a bus interface unit, CS is a control memory, AIL is an adapter interface unit, and MACI is a memory controller interface unit.

Conventionally, a DASD high-speed writing mechanism has been known which writes data from a host at high speed to a DASD (for example, a magnetic disk device) connected to the host.
One example thereof will be described below with reference to FIGS.

As shown in FIG. 5, a DASD controller 2 is connected to the channel 1 on the host side, and a DASD 3 is connected to the DASD controller 2. in this case,
For example, the DASD controller 2 is a magnetic disk controller,
DASD 3 is a magnetic disk device.

The DASD control device 2 is provided with a channel control unit CA, a device control unit DA, a cache memory 4, a non-volatile cache memory 5, a memory controller 6, and a memory port SSP.

Further, the channel control unit CA includes
Microprocessor MPU, control memory CS, channel interface unit CIL, bus interface unit B
IL is provided, and the device control unit DA is provided with a microprocessor MPU, a control memory CS, a bus interface unit BIL, and an adapter interface unit AIL.

Further, the memory port SSP is provided with a bus interface unit BIL and a memory controller interface unit MACI. With the high-speed write function having the above-mentioned configuration, the data from the channel 1 on the host side is stored in the cache memory 4 and the non-volatile cache memory 5.
To the host, and at the end of writing, the connection with the host is terminated.

By performing such processing, the I / O response time in the write processing can be shortened. Also, the write processing for DASD3 is performed by DASD.
Since write-back processing is automatically performed inside the control device 2, no host intervention is required.

Specifically, it is as follows. Data is written to the cache memory 4 and the volatile cache memory 5 when the target record exists in the cache memory (when the data is already read from DASD), and this case is the write hit operation. ..

If there is no data in the cache memory, the write hit operation is not performed and the data is directly written to DASD (in this case, high speed writing is not performed).

At the time of the write hit operation, the write data sent from the channel 1 on the host side is received by the channel control unit CA in the DASD control device 2,
The received write data is transferred to the memory controller 6 via the memory port SSP.

Thereafter, the memory controller 6 simultaneously writes the received data in the cache memory 4 and the non-volatile cache memory 5. When the writing of the data to the cache memories 4 and 5 ends normally, the connection with the host ends.

That is, by writing the data in the cache memory 4 and the non-volatile memory 5, it is treated as if the data were written in the DASD 3, and the data write processing on the host side is speeded up.

In this case, even if a power failure occurs after the data write to the cache memory is completed, the write data from the host is stored in the non-volatile cache memory 5 and is not lost. Therefore, the write data is guaranteed as in the case of writing to DASD3.

The data written in the cache memory is then written back in the DASD controller 2 and written back to the DASD 3. The write hit operation is usually repeated for the same record, and the data is overwritten in the same memory each time. This is shown in FIG.

For example, at the end of the first write hit operation, as shown in (A) of FIG. 6, the cache memory 4 and the non-volatile cache memory 5 have predetermined addresses (areas of the same address shown by hatching). Data is written.

Next, when the second write hit operation is completed with respect to the same address as the first write hit operation, as shown in FIG. 5B, data is written in the first write hit operation. The data is overwritten and the data is rewritten.

Next, when the third write hit operation is performed on the same address as above, new data is overwritten on the data written in the second write hit operation. If a power failure occurs during the third write hit operation, the state of FIG. 6C is obtained.

That is, if a power failure occurs during the write hit operation, the write data can be sent only halfway. Therefore, the write data of the second time and the write data of the third time are mixed, and the data written in the second time is lost. In this case, the contents of the cache memory 4 are all lost.

[0022]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. (1) Due to the DASD high-speed writing mechanism, if the process is interrupted due to a power failure or the like while the write process is being performed, the data before the process is interrupted cannot be retained. Therefore, data loss occurs.

(2) Since data is lost due to a power failure or the like, the reliability of the DASD high-speed writing mechanism deteriorates. The present invention solves such a conventional problem, and makes it possible to retain the data before the processing interruption even if the processing is interrupted due to a power failure or the like during the write processing by the DASD high-speed writing mechanism. The goal is to minimize losses.

[0024]

FIG. 1 is a principle view of the present invention, in which the same reference numerals as those in FIG. 4 indicate the same elements. Also,
7 is a nonvolatile track buffer, F is a flag, C is control data, and D is data.

In order to solve the above problems, the present invention has the following configuration. (1) D that performs various controls for DASD (file) 3
The ASD control device 2 is provided with a cache memory 4, a non-volatile cache memory 5, and a memory controller 6 for controlling these memories, and write data from a host is stored in the cache memory 4 and the non-volatile cache memory 5. In the backup control method in the file high-speed writing mechanism, in which writing is performed at the same time and connection with the host is terminated at the end of writing,
The ASD control device 2 is provided with a non-volatile memory 7, and when writing the write data from the host to the cache memory 4 and the non-volatile cache memory 5, the write data is temporarily controlled by the non-volatile memory 7 under the control of the memory controller 6. The data in the nonvolatile memory 7 is written back to the cache memory 4 and the nonvolatile cache memory 5 after the writing data is normally captured.

(2) In the configuration (1), the nonvolatile memory 7
And a flag portion F for setting / resetting the transfer completion flag.
After the write data is fetched into the non-volatile memory 7, the transfer completion flag is set, the data in the non-volatile memory 7 is written back to the cache memory 4 and the non-volatile cache memory 5, and then the transfer is performed. Changed to reset the flag.

(3) In the configuration (2), when the apparatus is started up after the processing is interrupted due to a power failure or the like, the transfer flag is checked, and if the transfer completion flag is set, the data in the non-volatile memory 7 is saved. The data is written back to the cache memory 4 and the non-volatile cache memory 5.

[0028]

The operation of the present invention based on the above configuration will be described with reference to FIG. 1. In the channel control unit CA of the DASD control device 2, the write command is received from the channel 1 (host side) and the DASD high speed write mechanism is used. When writing data to the cache memory,
First, the address (write address of the cache memory) and the number of transfer bytes are transferred to the memory controller 6, and then the write data is transferred.

In the memory controller 6, the address and the number of transfer bytes are stored in the control section C of the non-volatile memory 7, the next write data is stored in the data area D, and when this processing is completed, the flag section F Set the transfer completion flag of.

Thereafter, the memory controller 6 transfers the data in the data area D to the cache memory 4 and the non-volatile cache memory 5 and writes back the data. When a power failure occurs and the processing is interrupted, the memory controller 6 checks the flag portion F at the time of device startup processing performed after recovery from a power failure or the like. As a result, if the transfer completion flag is set, the address of the control section C and the number of transfer bytes are read, and the data of the data section D is written back to the cache memory 4 and the nonvolatile cache memory 5.

By doing so, even in the DASD high-speed writing, the data before the interruption can be guaranteed when the write processing is interrupted. The data in the nonvolatile cache memory 5 is written back to the DASD 3 by the DASD control device 2 regardless of the host.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 4 are views showing an embodiment of the present invention, FIG. 2 is a configuration diagram of a DASD control device, FIG. 3 is a partial detailed view of FIG. 2, and FIG. 4 is a processing flowchart of a memory controller. is there.

In the figure, the same symbols as those in FIGS. 1 and 5 indicate the same components. 7A is a non-volatile track buffer, SSI
Indicates a cache memory control unit, TKBI indicates a track buffer control unit, and NVSI indicates a non-volatile cache memory control unit.

The structure of the DASD control device in the embodiment is shown in FIGS. In this embodiment, a nonvolatile track buffer 7A is added to the conventional DASD control device shown in FIG.
In addition, in order to control the nonvolatile track buffer 7A, the structure of the memory controller 6 is as shown in FIG. Specifically, it is as follows.
As shown, the DASD controller 2 is connected to the channel 1 on the host side, and the DASD controller 2 is connected to the DASD controller 2.
3 is connected.

The DASD controller 2 includes a channel controller CA, a device controller DA,
A cache memory 4, a non-volatile cache memory 5, a memory controller 6, and a memory port SSP are provided.

The channel control unit CA is provided with a channel interface unit CIL, a microprocessor MPU, a control memory CS and a bus interface unit BIL, and the device control unit DA is provided with a bus interface unit BIL and a microprocessor MP.
U, adapter interface AIL, control memory CS
To provide.

Further, the memory port SSP is provided with a bus interface unit BIL and a memory controller interface MACI, and the memory controller 6 is provided with
Cache memory control unit SSI, track buffer control unit TKBI, non-volatile cache memory control unit NVSI
To provide.

As shown in FIG. 3B, the non-volatile track buffer 7A comprises a flag section F, a control section C, and a data area D, and the track buffer control section in the memory controller 6 is provided. Controlled by TKBI.

In this case, the nonvolatile track buffer 7A
Is a non-volatile buffer having a capacity enough to write data for one track of DASD3. The cache memory 4 is controlled by the cache memory control unit SSI in the memory controller 6, and the nonvolatile cache memory 5 is controlled by the nonvolatile cache memory control unit NV.
Controlled by SI.

Backup control in the DASD high-speed writing mechanism of the embodiment will be described below. DASD
In the write hit operation by the high-speed writing mechanism, the data received from the channel 1 is transferred to the channel control unit CA.
Via the memory port SSP and the memory controller 6 through the cache memory 4 and the non-volatile cache memory 5
It is performed by simultaneously transferring to.

In this case, when data writing (writing of data) to the cache memory 4 and the non-volatile cache memory 5 is performed, the channel control unit CA beforehand
Data transfer is performed after notifying the "data storage address (address of the cache memory 4 and the nonvolatile cache memory 5) and the number of transfer bytes" to the track buffer control unit TKBI in the memory controller 6 through the memory port SSP. The track buffer control unit TKB
When I receives the "data storage address and the number of transfer bytes", I stores it in the control unit C in the nonvolatile track buffer 7A (creating the control unit).

After that, the track buffer control unit TKBI
Then, when the data to be written is received, the data is stored in the data area D of the nonvolatile track buffer 7A. Further, the track buffer control unit TKBI sets the transfer completion flag in the flag unit F in the nonvolatile track buffer 7A at the time when the data for the above “transfer byte number” is received.

Subsequently, the memory controller 6 reads the data stored in the data area D of the nonvolatile track buffer 7A, and the cache memory controller SS
It is transferred to the cache memory 4 via I and to the nonvolatile cache memory 5 via the nonvolatile cache memory control unit NVSI.

When this data transfer is completed and the write data from the channel is written in the cache memory 4 and the non-volatile cache memory 5, the track buffer control unit TKBI sets the transfer completion flag of the flag unit F. To do.

While repeating such operations, the write hit operations are sequentially performed, but when the processing is interrupted due to a power failure or the like, the processing is performed as follows. For example, during a power outage,
When the device is started up after recovery, the track buffer control unit T
KBI is the flag part F of the nonvolatile track buffer 7A.
Check, and if the transfer completion flag is set,
The "data storage address and number of transfer bytes" stored in the control unit C is read.

Then, the data stored in the data area D is read out and transferred to the cache memory 4 via the cache memory control unit SSI, and at the same time, the nonvolatile cache memory 5 is transferred via the nonvolatile cache memory control unit NVSI. Transfer to and store.

After the data transfer is completed, the track buffer control section TKBI resets the transfer completion flag set in the flag section F. Further, when the device is started up, the data transfer is not performed unless the transfer completion flag is set.

The data in the nonvolatile cache memory 5 is written back (written back) to the DASD 3 by the DASD control device 2 regardless of the host side. When this write-back is completed, the data area of the non-volatile cache memory 5 is released (the write-back process is the same as that of the conventional example, so detailed description is omitted).

The processing of the memory controller will be described below with reference to the processing flowchart of FIG. The process numbers in FIG. 4 are shown in parentheses. First, in the track buffer control unit TKBI, the nonvolatile track buffer 7
The flag portion F in A is checked (S1), and if the transfer completion flag is set, the "data storage address and number of transfer bytes" stored in the control portion C is read (S2).

Next, the data stored in the data section D is transferred to the cache memory 4 and the non-volatile cache memory 5 (S3), and the transfer completion flag of the flag section F is reset (S4). If the transfer completion flag is not set (S1), nothing is done.

After that, the next command is awaited (S
5). When the write command is issued from the channel 1 and the "data storage address and the number of transfer bytes" sent from the channel control unit CA is received by the track buffer control unit TKBI in the next write hit operation, the nonvolatile track buffer It is stored in the control section C in 7A (S7).

Next, when the track buffer control unit TKBI receives the write data from the channel control unit CA, it stores it in the data unit D in the nonvolatile track buffer 7A (S8).

After that, the transfer completion flag of the flag portion F is set (S9). If the command issued on channel 1 is a read command, read processing (S10) is performed.

During the write hit operation as described above, even if the writing process to the cache memory is interrupted due to a power failure, for example, the data before the process is interrupted is guaranteed.

[0055]

As described above, the present invention has the following effects. (1) With the DASD high-speed write mechanism, even if a power failure occurs during the process of writing data to the cache memory and the process is interrupted, no error occurs and the data before the process is interrupted Can hold.

(2) Since the loss of data due to a power failure or the like can be minimized, the reliability of the DASD high speed writing mechanism can be improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a DASD control device according to an embodiment of the present invention.

3 is a partial detailed view of FIG. 2, in which FIG. A is a block diagram of a memory controller, and FIG. B is a block diagram of a nonvolatile track buffer.

FIG. 4 is a processing flowchart of a memory controller.

FIG. 5 is a configuration diagram of a conventional DASD control device.

FIG. 6 is an explanatory diagram of a conventional data write process.

[Explanation of symbols]

 1 channel 2 DASD control device 3 DASD 4 cache memory 5 non-volatile cache memory 6 memory controller 7 non-volatile memory CA channel control unit DA device control unit F flag unit C control unit D data area

Claims (3)

[Claims] 1. A file controller (2) for performing various controls on a file (3), a cache memory (4), a non-volatile cache memory (5), and a memory controller () for controlling these memories. 6) is provided, and write data from the host is simultaneously written to the cache memory (4) and the non-volatile cache memory (5), and at the end of writing, the connection with the host is terminated at high speed. In the backup control method in, the file control device (2) includes a nonvolatile memory (7).
When the write data from the host is written in the cache memory (4) and the non-volatile cache memory (5), the write data from the host is temporarily stored in the non-volatile memory (7) under the control of the memory controller (6). ), And after the write data is normally captured, the data in the non-volatile memory (7) is written back to the cache memory (4) and the non-volatile cache memory (5). Backup control method in. 2. The non-volatile memory (7) is provided with a flag section (F) for setting / resetting a transfer completion flag, and after the write data is taken into the non-volatile memory (7), the transfer completion flag is set. The transfer completion flag is reset after the data in the non-volatile memory (7) is written back to the cache memory (4) and the non-volatile cache memory (5). Backup control method for high-speed file writing mechanism. 3. When the device is started up after interruption of processing due to a power failure or the like, the transfer completion flag is checked, and if the transfer completion flag is set, the data in the non-volatile memory (7) is transferred to the cache memory ( 4. The backup control method in the high speed file writing mechanism according to claim 2, wherein the data is written back to the non-volatile cache memory (4) and the non-volatile cache memory (5).