JPS6354631A - Controller - Google Patents

Controller

Info

Publication number
JPS6354631A
JPS6354631A JP19874086A JP19874086A JPS6354631A JP S6354631 A JPS6354631 A JP S6354631A JP 19874086 A JP19874086 A JP 19874086A JP 19874086 A JP19874086 A JP 19874086A JP S6354631 A JPS6354631 A JP S6354631A
Authority
JP
Japan
Prior art keywords
address
high speed
rom
low speed
data signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19874086A
Other languages
Japanese (ja)
Inventor
Jun Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP19874086A priority Critical patent/JPS6354631A/en
Publication of JPS6354631A publication Critical patent/JPS6354631A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To execute a processing at high speed by using a low speed ROM, by discontinuing the use of a high speed PROM and using the low speed ROM, and also, providing a high speed RAM for writing the program of the low speed ROM before starting a processing operation.
CONSTITUTION: From a CPU (not shown in the figure), the read-out address 13 of a low speed ROM 12 is designated, and the contents of a control bit area 12b corresponding to the address of an address bit area 12a are read out as a read-out data signal 14. This data signal 14 is written as a write data signal 10 in the address of an address bit area 8a of a high speed RAM 8 designated through a multiplexer 11 by the write address 9 of the CPU. As a result, an address register 2 designates the address of the high speed RAM 8 by an output 5. Accordingly, a high speed RAM 8 control signal 6 and the next address signal 4 are outputted.
COPYRIGHT: (C)1988,JPO&Japio
JP19874086A 1986-08-25 1986-08-25 Controller Pending JPS6354631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19874086A JPS6354631A (en) 1986-08-25 1986-08-25 Controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19874086A JPS6354631A (en) 1986-08-25 1986-08-25 Controller

Publications (1)

Publication Number Publication Date
JPS6354631A true JPS6354631A (en) 1988-03-09

Family

ID=16396190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19874086A Pending JPS6354631A (en) 1986-08-25 1986-08-25 Controller

Country Status (1)

Country Link
JP (1) JPS6354631A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01261759A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system
JPH01261760A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system
JPH01261758A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01261759A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system
JPH01261760A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system
JPH01261758A (en) * 1988-04-13 1989-10-18 Canon Inc Computer system

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