JPS6354631A - Controller - Google Patents

Abstract

PURPOSE:To execute a processing at high speed by using a low speed ROM, by discontinuing the use of a high speed PROM and using the low speed ROM, and also, providing a high speed RAM for writing the program of the low speed ROM before starting a processing operation. CONSTITUTION:From a CPU (not shown in the figure), the read-out address 13 of a low speed ROM 12 is designated, and the contents of a control bit area 12b corresponding to the address of an address bit area 12a are read out as a read-out data signal 14. This data signal 14 is written as a write data signal 10 in the address of an address bit area 8a of a high speed RAM 8 designated through a multiplexer 11 by the write address 9 of the CPU. As a result, an address register 2 designates the address of the high speed RAM 8 by an output 5. Accordingly, a high speed RAM 8 control signal 6 and the next address signal 4 are outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is capable of increasing speed while using a low-speed ROM, and also enables revision of content by using a low-speed ROM, making version management easy. The present invention relates to a control device.

[Conventional technology]

As a conventional control device, for example, there is one shown in FIG. 2 (Advanced Micro Device Bit Slice Design Method, published January 31, 1980). This control device is related to a controller based on a microprogram, and consists of an n-bit address bit area 1a and a C-bit control bit area 1b.
) bit high-speed PROM (for example, access time is 20 to 40 ns) 1 and an address register 2 that outputs an address 5 for the high-speed FROMI.

In the above configuration, when address register 2 outputs address 5 based on clock signal 3, high-speed FROM
I provides a control signal 6 to the system, for example a printer (not shown) connected via an interface to a host computer (not shown), and a next address signal 4 to be loaded into the address register 2. Output. This control signal 6 is sent to the CPU (not shown)
The signal is output to the printer based on signal processing, and a predetermined drive unit is activated. As a result, a desired print can be obtained based on data obtained from the host computer at a speed corresponding to the access time of high-speed RPOMI.

[Problem that the invention seeks to solve]

However, according to the conventional control device, for example, in correspondence with the program of the host computer, high-speed PROMI
Even if it becomes necessary to change the contents of the program, the contents cannot be changed, so expensive high-speed F ROM 1
Waste occurs because the parts have to be replaced.

To avoid this, store an external floppy disk or
A control device that is equipped with a ROM and downloads the program from there to the internal RAM has also been proposed;
Since the n device and the floppy disk or FROM are separate, version management becomes difficult, and
When trying to correct analog elements with different characteristics provided on each board using ROM, each board and FR
Since it becomes difficult to deal with the OM, there is an inconvenience that its management becomes difficult.

[Means for solving problems]

The present invention has been made in view of the above, and eliminates the waste caused by replacing expensive high-speed FROMs (and also eliminates the waste of replacing expensive high-speed FROMs). In order to facilitate the management of correspondence with the above, the present invention provides a control device equipped with a high-speed RAM that stops the use of the high-speed FROM and uses a low-speed ROM, and writes the program in the low-speed ROM before starting a processing operation.

Here, low-speed ROM means, for example, an access time of 1
It is 50 to 300 nS, and at present, the price per chip for 256 bits is only about 50% higher than that of a small-capacity high-speed FROM of 4 bits. Therefore, if you compare prices for the same capacity, the cost will be significantly reduced, and there will be less waste even if you replace one low-speed ROM with another low-speed ROM to change the program content.On the other hand, erasable FR as a low-speed ROM
By using OM, programs can be changed freely and waste caused by replacement can be eliminated.

Hereinafter, the control device of the present invention will be explained in detail.

〔Example〕

FIG. 1 shows an embodiment of the present invention in which the load is enabled based on the clock signal 3 and the n-bit address 5 is loaded.
, a multiplexer 11 that selects and outputs either the n-bit write address 9 or the address 5 of the address register 2, an n-bit address bit area 8a, and a C-bit write signal area 8b. It is composed of a high-speed RAM 8 and a low-speed ROM 12 having an n-bit address bit area 12a and a C-bit control bit area 12b.

In the above configuration, before a predetermined processing operation is started, the read address 13 of the low-speed ROM 12 is designated by the CPU (not shown), and the address bit area 1
Control bit 9M area 1 corresponding to address 2a
The contents of 2b are read out as a read data signal 14. This data signal 14 is written as a write data signal 10 to an address in the address bit area 8a of the high speed RAM 8 designated via the multiplexer 11 by the write address 9 of the CPU. In this way, the predetermined microprogram is transferred from the low-speed ROM 12 to the high-speed R
When written to A M 8, address register 2 is transferred to fast RAM 8 by output 5 via multiplexer 11.
Specify the address of. This allows the high speed RAM 8 to provide a control signal 6 to the system, for example a printer (not shown) connected to a host computer (not shown) via an interface, and a next address signal to be loaded into the address register 2. Outputs 4.

The CPU controls the printer based on the control signal 6, causes it to perform a predetermined printing operation, and outputs a record based on the data transferred from the host computer.

As is clear from the above embodiments, since the processing operation is started after reading the contents of the low-speed ROM, it is possible to store multiple sets of data in the low-speed ROM and use only one set of data. , the contents of the control operation can be changed by adding processing to the read data.

In addition, since the low-speed ROM is provided, for example, in the control device of the printed board unit, version number management is easy, and if an erasable FROM is used as the low-speed ROM, the program can be changed and there is no need to replace it. It disappears. Although the high-speed RAM is used to store microprograms, it may also be used to store control system parameters, for example.

〔Effect of the invention〕

As explained above, according to the control device of the present invention, the high speed
By stopping the use of ROM and using a low-speed ROM, we also installed a high-speed RAM that writes the program in the low-speed ROM before starting the processing operation. This allows for faster processing while still using the low-speed ROM, and eliminates waste when changing programs. In addition, version number management and correction management of analog elements with different characteristics on each board are facilitated.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention. FIG. 2 is an explanatory diagram showing a conventional control device. Explanation of symbols 2・-・−・−・Address register 8−・−High speed R
A M12----Low speed ROM

Claims (1)

[Claims] A control device that controls the operation of a related system based on stored control data, comprising: a read-only memory (ROM) that stores the control data; and a read-only memory (ROM) that stores the control data. a random access memory (RAM) having an access time shorter than that of the ROM, and reading predetermined control data from the read-only memory (ROM) prior to controlling the operation; A control device comprising control means for causing data to be written into the random access memory (RAM).