JPS595481A - Flag controlling system of stack memory control - Google Patents

Abstract

PURPOSE:To reset effective flag of the block of a high speed buffer using simple configuration, by performing interruption basing on the shrinkage flag that responds to exceeding of block boundary of a high speed buffer memory in the direction of shrinking of a stack. CONSTITUTION:Set operation code is interpreted by an operation code decoder 2, and in case of direction of shrinking of a stack, output l1 of the decoder 2 becomes high level. When the address necessary for selection of a multiplexer 3 exceeds blocks B0, B1- of a high speed buffer memory B, output l2 of a comparator 4 is inverted to high level through a pointer HST, and shrinkage flag S from an AND gate 6 becomes high level and a processer 15 is interrupted. The flag of the bit that forms tag of corresponding blocks B0, B1- is reset by simple configuration using a shrinkage flag.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a stack computer equipped with a hardware stack, and includes a flag for managing all usage states of its high-speed buffer memory. The present invention relates to a device that allows the existence of free blocks in a high-speed buffer memory to be indicated by a simple configuration.

[Technology background]

In a stack computer, as shown in Fig. 1, a memory called a stack S'I'-0...
T −n ft Provided for each process and provided for multiple processes (
tasks) are being processed in parallel. In such multi-process processing, the environment of each process (intermediate results and status of processing)
The stack is prepared to hold the data, and the data set at the top of the stack is used to perform data processing for each process. By doing this, the central processing unit only has to access all the data set in the upper position of the stack and execute all data processing, making control easier.As shown above, each stack is controlled by the central processing unit Since it is frequently accessed during the data processing process, it is desirable to configure it with high-speed memory, but realizing the entire stack capacity with high-speed memory is expensive and poses a cost problem. Therefore, in terms of cost performance, it is better to use a high-speed buffer to hold only the tip of the stack (the part where recently created data has been set) and use low-speed memory to store the rest, or to use low-speed memory to store the entire stack. ing.

On the other hand, in the multi-process processing described above, a plurality of stacks exist. The method of providing a high-speed buffer memory for each stack is simple in terms of control, but it is costly, and having a dedicated high-speed buffer even for processes that are infrequently started is an effective way of conserving resources. This is a problem from a usage point of view.

Therefore, as shown in Figure 2, each stack (process)
T-0...S T-n f consists of a low-speed memory and has a plurality of blocks Bo-Bsf in common.
A method of providing two high-speed buffers Bi, such as a so-called cache memory, in which the high-speed buffers are allotted to processes that have recently been activated frequently, is used because it is superior in terms of cost performance.

In order to realize this method, the high-speed buffer memory Bi is divided into a plurality of blocks BO to B3, and as shown in FIG. (i-0 to n), stack position information (block number or address) b A tag memory (directory) TO or tag register is provided to hold all, and hardware stack NO...Nn
No. 1 that provides an address for the access-t-role.
A hardware stack pointer H8T=i is provided, and this is filled with the block number J (i=0 to m) in the stack, the address bad in the block, and the block number Bi (
i = 0 to 3), and fill in the hardware stack pointer HAT with the stack pointer of the currently running process, bi, , bad.
Write down all numbers such as +Bi. Each stack is also provided with a stack top pointer 8TP, in which a recently used in-flock address (or block number and address) is written.

In this FIG. 3, the stack top pointer S
TP stores the address in the stack that was recently used, that is, when a process pauses, the address in the stack at the time of the pause is stored, so when a process is started, the stack pointer of the stack is transferred to the hardware stack pointer H8T. loaded into. Then, the tag TG is searched, and if a block Bi including the address bad f exists in the high-speed buffer B, processing starts on that block Bi (i=o to 3). If it does not exist, check all appropriate blocks in the sofa (for example, blocks specified by LRU circuits, etc.) at high speed, and if the valid flag of that block is V-0, read the corresponding block from the stack.
If the valid flag of a block in the high-speed buffer designated by the RU circuit or the like is V-1, the block is transferred to the stack of the low-speed memory, and then all the corresponding blocks are read. Processing of that block then begins.

Consider a case where, for example, the process crosses a block boundary in the course of execution after starting this process.

In this case, it is assumed that processing is performed on block b1-0 of stack S'l''-Q in block B1.

As the process of stack 5T=Q progresses and the stack advances in the direction of elongation, the tooth block b1-
When processing progresses from block 0 to block b2-o,
If it is -1 in the next buffer block, replace it, register all tags, and proceed with processing.

However, when the stack is in the shrinking direction, the block b1-0 is used. When the process progresses in the direction of -0, the block b. −〇 is block Bl of high-speed buffer
Before transferring to block Bt, first reset the valid flag Vi of block Bt to V-0, then transfer to the necessary block b. −
〇All data must be transferred. [Prior art and problems] In order to reset the valid flag when the stack is in the shrinking direction, conventionally the entire circuit as shown in FIG. 4 was required. In FIG. 4, 11 to 14 are valid flags V in the tags of the high-speed buffer B.

~ ■ 3, and AND circuit 7 is used to reset all of this.
Reset signal k from ~10. - It is necessary to output kak. As mentioned above, in block B1 of high-speed buffer B,
When block I)□1-0 of stack 5T-0 in FIG.
/ Yon code register 1 is set. The operation code set in the operation code register 1 is decoded by the operation code decoder 2, and if the stack is in the shrinking direction, the signal 11 becomes "1". Further, the multiplexer 3 is selectively controlled by this decoding, thereby selecting an address signal necessary for processing. When this address crosses the block boundary, comparator 4
Logical block number P at stack pointer H8T
Compare l (corresponding to bi in H8T in FIG. 3) with the logical block number of the address transmitted from multiplexer 3,
When this block boundary is crossed, the comparator 4 outputs its boundary change detection signal j2. As a result, the AND circuit 6 outputs a signal l indicating that a block boundary has been crossed by a process that is proceeding in the direction of shrinking the stack. -Output rlJ. At this time, the encoder 5 decodes the buffer block number Pa (corresponding to Bi of H8T in FIG. 3) of the hardware stack pointer H8T, fully recognizes that it is B+, and inputs the [ lJf: output,
"0" is output to the AND circuit 7.9.10. Therefore, the signal l is output from the AND circuit 6. - When "1" is output, the AND circuit 8 fully outputs the Vl reset signal ki to drop the valid flag ■1, thereby
-0, and the valid flag Vl is reset.

In this way, when a block boundary was crossed in the direction of shrinking the stack, the valid flag of the tag of the old block was reset by hardware as shown in Figure 4.
There is a problem in that as the number of blocks in the high-speed buffer (four in FIG. 4) increases, the hardware required to reset the valid flag of the tag corresponding to each block increases proportionally.

[Purpose of the invention]

An object of the present invention is to provide a stack memory control flag control method that does not require an increase in the amount of hardware required to reset the valid flag for each block even when the number of blocks in a high-speed buffer increases. Configuration] In order to accomplish all of this purpose, the stack memory control flag control method of the present invention includes a low-speed memory stack provided for each of a plurality of processes, a high-speed buffer memory divided into a plurality of block parts, and the high-speed buffer. In a stack memory having a tag section provided for each block portion of the memory and having a valid flag, a first signal generating means indicating that a process is progressing in a direction in which the stack is shrinking, and a block for detecting that a block boundary has been crossed. It is equipped with a boundary over detection means and a shrink display means 't- which indicates that a block boundary has been crossed in the direction in which the stack shrinks, and when a display signal is set in the shrink display means, the block portion is read and the block portion is Disable all the valid flags in the tag%
be a sign.

[Embodiments of the invention]

An embodiment of the present invention will be explained based on FIG. 5.

In the present invention, one shrink flag S is provided.

This shrink flag S is not provided corresponding to each block Bo-H3 of the high-speed buffer B, but
Only one is provided. This shrink flag S is set when a block boundary is crossed in the direction in which the stack is shrinking.

In FIG. 5, operation code register 1
When the operation code is set to , this is decoded by the operation code decoder 2, and when the stack is in the shrinking direction, l, = "IJ". - Also, the output of this decoder 2 selectively controls the shim multipunker 3, This selects the address store name required for processing.And when this add exceeds the block boundary,
Comparator 4 receives boundary change detection signal 1 as in the case of FIG.
Output 2 times. As a result, the p' AND circuit 6 outputs a signal l indicating that a block boundary has been crossed due to the progress in progress in the direction of shrinking the stack. -1-1'' is fully output, thereby setting the shrink lag S, and r lj is fully output.

As a result, an interrupt signal will be output to the processor 15.The processor 151 will then:
Check this shrink flag S in the interrupt processing routine caused by accessing the stack with an invalid stack pointer.

When the shrink flag S is set, the buffer block number P3 (Tsumushi Bi) of the hardware stack pointer H8T is checked, and the valid pit V of the tag of that old block is reset.

In this way, with a very simple configuration, even if the block boundary changes when the synutac is in the shrinking direction, the valid flag can be easily dropped.

Furthermore, even if the number of blocks in the high-speed buffer increases, only one shrink flag S is required, so an increase in the amount of hardware can be prevented.

This shrink flag S may be provided in the hardware stack pointer HST' portion as shown in FIG.

〔Effect of the invention〕

According to the present invention, control when the stack crosses a block boundary in the direction of shrinkage can be handled by providing only one shrink flag 'ft, so that the hardware configuration can be simplified. Furthermore, even if the number of blocks in the high-speed buffer is increased, there is no need to increase the amount of hardware.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of a stack calculator, Figure 2 is an explanatory diagram of a high-speed buffer and stack, and Figure 3 is an explanatory diagram of a high-speed buffer and a tag.
An explanatory diagram of the hardware stack pointer, etc., Figure 4 shows the conventional stack memory control flag control method,
FIG. 5 is a configuration diagram of an embodiment of the present invention, and FIG. 6 shows an example of a shrink flag installation section. In the figure, 2 indicates a lid operation code V register, 2 an operation code decoder f, 3/ri multiplexer, 4 a comparison circuit, and 15 a processor. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani Eisai 1fil

Claims (1)

[Claims] (1) A low-speed memory stack provided for each of the plural e processes, a high-speed buffer memory divided into a plurality of block parts, and a tag part provided for each block part of the high-speed buffer memory and having a valid flag. in the stack memory, a first signal generating means for indicating that the process progresses in a direction in which the stack shrinks;
It is equipped with a block boundary over detecting means for detecting that the block boundary has been crossed, and a shrink display means for indicating that the block boundary has been crossed in the direction of shrinking the stack, and when a display signal is set in the shrink display means. A stack memory control flag control method 0 characterized in that C reads a block portion and further invalidates all the valid flags in the tag of the block portion.