JP3128060B2 - Multi-function parallel processing electronic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-function parallel processing type electronic device for processing a plurality of sets of control programs in parallel in a time-division manner, and in particular, a subroutine called in processing a control program accesses a dynamic RAM. In this case, the time-division switching is inhibited to ensure the refresh operation and prevent the stored data from disappearing.

[0002]

2. Description of the Related Art Conventionally, in electronic devices such as various types of information processing devices having a built-in computer, a plurality of functions such as arithmetic processing control and information input / output processing control are performed in order to speed up processing of a plurality of functions. A multi-function parallel processing method for simultaneously realizing a plurality of functions by processing control programs in parallel is employed. In this multifunctional parallel processing system, a plurality of central processing units (CPUs) are interconnected and connected, and a plurality of sets of control programs are respectively controlled by a plurality of central processing units by a parallel processing management system based on an OS (operating system). A multi-processing system (multi-processing system) that is executed as a separate process has been put to practical use. Also, a time-sharing processing method (time-division processing method) in which a plurality of sets of control programs are executed in a predetermined order for each predetermined processing time time-divided by one central processing unit in a short time is also practical. Has been

Recently, instead of a static memory (a so-called SRAM), an inexpensive large-capacity memory can be mounted as an IC memory mounted on various electronic devices such as a computer and storing various data. Dynamic RAM (so-called DRAM) has become mainstream.
However, in this dynamic RAM, a refresh operation is required every minute time (for example, 2 to 5 msec) in order to hold stored data. Therefore, a peripheral circuit having a clock oscillator, a refresh controller, and the like is included in the dynamic RAM. The refresh operation is performed by a regular refresh pulse output from the peripheral circuit connected thereto.

On the other hand, recently, a peripheral circuit such as a refresh controller and a clock oscillator is built in as this kind of dynamic RAM, and the peripheral circuit always performs an internal refresh operation. A combination refresh operation type one-chip dynamic RAM in which the internal refresh operation is stopped and a series of refresh operations are included in the read processing or the write processing instead has been put to practical use.

[0005]

As described above, when a plurality of functions are realized in parallel by a multi-processing system using a plurality of central processing units, a plurality of central processing units are required, and Since the size of the control board of the control device is increased, the cost of the electronic device is increased. Therefore, in order to reduce costs, a single central processing unit processes a plurality of functions in parallel in a time-sharing manner.
When a plurality of functions are simultaneously realized, a combination refresh operation type dynamic RAM described above may be used as an inexpensive dynamic RAM for data storage.

In this case, when time-division switching occurs during data read processing or data write processing for the dynamic RAM and the processing is switched to processing of the other party's function, the data read processing or write processing is performed. The refresh operation is also interrupted along with the interruption. Here, when the time-division processing time is longer than the refresh cycle time set to perform the refresh operation, the refresh operation can be performed in the standby period until the access to the dynamic RAM is resumed at the next time-division switching timing. Gone
There is a problem that all or a part of the data stored in the dynamic RAM disappears.

An object of the present invention is to execute a subroutine included in a control program so that a refresh operation for reading or writing data from or to a dynamic RAM is not interrupted by time division switching so that stored data can be erased. An object of the present invention is to provide a multi-function parallel processing type electronic device that can be prevented.

[0008]

According to a first aspect of the present invention, there is provided a multi-function parallel processing electronic apparatus comprising a computer comprising at least one CPU, a ROM, and a RAM, wherein the ROM has a plurality of sets of control programs corresponding to a plurality of functions. Embed,
In an electronic device capable of simultaneously realizing a plurality of functions by executing two or more sets of control programs in parallel in a time-sharing manner, a dynamic RAM having an internal refresh function and performing a refresh operation for each data reading or writing process And among the plurality of subroutines included in the control program, the dynamic R
A subroutine for accessing the AM incorporates a switching prohibition step of prohibiting time division switching at least until the subroutine is completed.

[0009] When a plurality of sets of activated control programs are processed in parallel by a computer in a time-division manner, if a plurality of subroutines are included in the control program to be processed, the subroutine is called each time. Be executed. By the way, dynamic RAM
In the above, when the data read process or the write process is not performed, the internal refresh operation by the internal refresh function is performed. However, the dynamic RAM is accessed for the data read or write by the called subroutine. Sometimes, the switching inhibition step incorporated in the subroutine inhibits the time division switching until the subroutine is completed. Therefore, instead of the internal refresh operation, the refresh operation performed for each read process or write process is not performed. Without being interrupted by split switching
It is possible to reliably prevent the stored data from disappearing.

The multi-function parallel processing type electronic device according to claim 2 is
2. The switching device according to claim 1, further comprising switching means for sequentially switching a plurality of sets of control programs to be processed in parallel among the plurality of sets of control programs at a predetermined switching timing by time division, wherein the switching means inhibits the switching. When time-division switching is prohibited by a step, switching is not performed at a predetermined switching timing. In this case, when a plurality of sets of control programs are processed in parallel, the switching means allows the plurality of sets of control programs to be processed in parallel to be sequentially switched at a predetermined switching timing by time division. Therefore, when the time division switching is prohibited, the switching at the switching timing by the switching means can be reliably prohibited. In addition, Claim 1
It has the same function as.

The multi-function parallel processing type electronic device according to claim 3 is
In the invention of claim 2, the switching means is configured to perform switching at the predetermined switching timing after the switching prohibition in the switching prohibiting step is released. In this case, when the switching prohibition in the switching prohibition step is released, the switching is performed at a predetermined switching timing by the switching means thereafter, so that the parallel processing of a plurality of sets of control programs by time division switching is continued. be able to. Others
The same operation as the second aspect is achieved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. This embodiment has a laser printer or an image scanner device, and records received facsimile data, and in addition to a normal facsimile function such as transmitting image information of a document, is connected via a connection cable. This is a case where the present invention is applied to a multi-function parallel processing type electronic device (hereinafter, referred to as a multi-function information processing device) capable of realizing a data communication function for a personal computer. As shown in FIG. 1, the multifunction information processing apparatus 1 basically includes a control unit 20 having one computer 10, an operation panel 2, a laser printer 3, and an image scanner 4 connected to the control unit 20. It is composed of

The computer 10 basically has a CP
U11, a ROM 12 connected to the CPU 11 by a common bus 16 including a data bus, and an EEPROM.
(Electrically erasable and rewritable ROM) 13 and RA
M14 and a DMA controller 15 and the like. The common bus 16 includes a CODEC 21 having an encoding unit for encoding for shortening image information and a decoding unit for decoding shortened communication data, and an input / output ASIC (hardware logic circuit). An application-specific integrated circuit) 22, a modem 23 for facsimile communication,
The buffer 25 and a communication interface (communication I / F) 26 connected to the external personal computer 6 via the connection cable 7 are connected to each other.

An NCU (Network Control Unit) 24 connected to the telephone line 5 and the receiver 8 is connected to the modem 23. Further, the input / output ASIC 22 includes a display 2 a and a keyboard 2.
b and a laser printer 3 are connected, and a dynamic RAM (hereinafter, DRAM)
The image scanner device 4 is connected to the image scanner device 27 via an external device 27. In the DRAM 27, dot data for two to three dot lines read by the image scanner device 4 are temporarily stored as image information,
The image information is read by the input / output ASIC 22.

The DRAM 27 has a peripheral circuit 27 including a clock oscillator and a refresh controller.
1-chip LSI (Large Scale I
C), as shown in FIG. 2, a memory capacity of 3072 bytes, in which addresses of 64 bytes are provided in the row direction and addresses of 28 bytes are provided in the column direction. That is, in the DRAM 27, by always setting the access mode to OFF, the refresh pulse RP1, RP2, RP3,... RP64 is sequentially supplied to the row address of “64 rows” by the peripheral circuit 27a. As a result, a refresh operation is performed on a row-by-row basis. However, the refresh cycle of the refresh operation is set within about 5 msec.

On the other hand, the access mode of the DRAM 27 is set to O
When set to N, the line address 6 within about 5 msec
A refresh operation can be performed simultaneously by accessing four bytes and performing read processing or write processing of data of all bytes. That is, for example, at the time of the read process, the refresh operation is performed simultaneously while reading data corresponding to the specified read address by executing the read process one byte at a time from the start address to the end address of the DRAM 27. .

The ROM 12 stores an external facsimile device (not shown) via the telephone line 5 by operating the laser printer 3 or the image scanner device 4.
A control program for realizing a facsimile function for controlling transmission and reception of facsimile data, a control program for realizing a copy function for recording image information of an original read by the image scanner device 4, and a control program received from the personal computer 6. A control program for realizing a print function for recording print data, a control program for realizing a scanner function for transmitting image information of a document read by the image scanner device 4 to the personal computer 6, and the like are stored.

As a control program for realizing the function of the facsimile, an idling control program for constantly detecting a change in the state of the multifunction information processing apparatus 1 and facsimile data received via the telephone line 5 are recorded by the laser printer 3. An image receiving / recording control program, and image information of a document is sent to an image scanner 4
And a memory transmission control program for reading and transmitting the image information stored in the RAM 14 in advance by reading with the image scanner device 4 and transmitting it as facsimile data via the telephone line 5. I have.

This multifunction information processing apparatus 1
In the above, the CPU 11 is capable of accepting a timer interrupt by a built-in timer that counts a clock signal from a clock connected thereto in a hardware manner. Then, for example, the memory transmission control program of the facsimile function and the control program of the scanner function are processed in parallel, or the image reading and transmission control program of the facsimile function and the control program of the print function are processed in parallel. When the CPU 11 receives a timer interrupt of, for example, about 1/60 second (about 16 msec), a plurality of sets of control programs corresponding to the plurality of functions are assigned to the assigned program for about 1/60 second (about 16 msec). A plurality of functions can be realized at the same time by performing parallel processing while sequentially switching in a time division manner every / 60 seconds.

The EEPROM 13 stores various setting modes for realizing the facsimile function, various setting data for the printing position and printing density for realizing the printer function, and a plurality of destination data. Is stored. RAM 14
Has a plurality of functions such as a facsimile function and a copy function in addition to a reception data memory for storing received data, a recording data memory for storing dot image data obtained by developing the received data so that the laser printer 3 can record the data. Various memories and buffers necessary for executing the control program to be realized are provided.

As described above, each of the control program for the facsimile function, the control program for the print function, and the control program for the scanner function includes a plurality of subroutines for realizing the functions. include. For example, the image reading and transmitting control program includes a subroutine for operating the image scanner device 4 to read the image data of the document, a writing subroutine for writing and processing a predetermined amount of the image information of the read document to the DRAM 27, and a transmission destination telephone. The subroutine includes a reading subroutine for reading a number from the EEPROM 13 and a subroutine for transmitting image data to the transmission destination.

The control program for the print function includes a subroutine for receiving print data from the personal computer 6, and a print position and print density, which are EEPR.
A data read subroutine for reading from the OM 13 is included. Further, the control program for the scanner function includes a plurality of subroutines for reading the image information of the document by a predetermined amount while operating the image scanner device 4, and a subroutine for transmitting the image information to the personal computer 6. include.

Next, the personal computer 6 will be described. As shown in FIG.
0, a hard disk drive (HDD) 40 connected thereto, a floppy disk drive (FDD) 41, and a CRT display (CRTD) 4
2, a keyboard 43, and a coordinate input device (mouse) 44
It is composed of The control device 30 includes a CPU 31
And a common bus 36 including a data bus
ROM 32, RAM 33, input / output interface 34, and communication interface (communication I /
F) 35.

The input / output interface 34 includes:
A hard disk drive controller (HDC) 37 for driving and controlling the hard disk drive 40 and a floppy disk drive controller (FDC) 38 for driving and controlling the floppy disk drive 41
And a CRT controller (CRTC) 39 for driving and controlling the CRT display 42 are connected to each other. The multifunction information processing apparatus 1 is connected to the communication interface 35 via a connection cable 7. Thereby, the created print data can be transmitted to the multi-function information processing apparatus 1 and recorded by the laser printer 3 of the information processing apparatus 1, while
It is possible to receive image information read by the image scanner device 4, and the like.

Next, a data read (write) subroutine of the DRAM 27 included in the image read / transmission control program will be described with reference to the flowchart of FIG. In the figure, reference symbol Si (i = 10, 1
1) are each step. When the data reading (writing) subroutine is called during the execution of the image reading / transmitting control program, first, the switching prohibition flag NCF is set to "1" as flag data. Are stored in an appropriate working area of the RAM 14 (S10).

Next, the access mode for the DRAM 27 is switched ON (S11), and a process of reading (writing) data from the DRAM 27 is executed (S12). At this time, as described above, the refresh operation is performed simultaneously by accessing 64 bytes corresponding to the row address within about 5 msec and executing the process of reading (writing) data of all bytes. When the access to the DRAM 27 is completed, the access mode to the DRAM 27 is switched to OFF, and the peripheral circuit 27 is turned off.
The internal refresh operation according to a is executed (S13), the flag data of the switching prohibition flag NCF is reset to "0" (S14), and the subroutine ends and returns. Here, S10 and S14 correspond to a switching prohibition step.

Next, the routine of the time division switching process control (corresponding to the switching means) for switching the process control based on the time division switching timing will be described with reference to the flowchart of FIG. When this control is started, first, the flag data of the switching prohibition flag NCF is read, and when the flag data is set to "1" (S20: Ye
s) The control is terminated and return is made without switching at the predetermined switching timing.

When the switching prohibition flag NCF is reset to "0" (S20:
No), a time-division switching process for switching the processing control to the other party and performing the processing is executed (S21), and this control is terminated and the routine returns. Here, the switching of the processing control based on the time-division switching timing will be described in the same manner as in the case of performing a subroutine call by a normal interrupt. While stacking data and the like of (status register) in a predetermined area of the RAM 14, PC data and SR data and the like related to the other processing control to be switched and executed are read out from the stack area of the RAM 14, Switching is performed by storing them in the SR or the like.

For example, when the image reading / transmission control program of the facsimile function and the control program for the printing function are processed in parallel in a time-division manner, the above-described read (write) subroutine for the DRAM 27 is executed. The operation at that time will be described with reference to FIG. However, the peripheral circuit 27a connected to the DRAM 27 always sets the access mode to O.
FF, and the DRAM 27 is connected to the peripheral circuit 27a.
, An internal refresh operation is performed by a regular refresh pulse RP for each refresh cycle, and all the stored data is stored and held.

At time T1, the image reading and transmitting control program is started, and from time T1, the image reading and transmitting process TA1 is executed. On the other hand, when the control program for the print function for recording the print data received from the personal computer 6 by the laser printer 3 is started at the time T2 during the execution of the image reading and transmitting process TA1, the image is started from the time T2. The reading transmission processing TA and the printing processing TB are processed in parallel by time division.

Then, after time T2, 1/60
Time division switching timings t1, t2, t3,.
Each time, the print processing TB1, TB2,... And the image reading and transmitting processing TA2, TA3,. At the time T3 during the execution of the image reading and transmitting process TA2, the DRAM 27
When the data read (write) subroutine is started, the switching prohibition flag NCF is set and the data read (write)
In the time-division switching prohibition period until time T4 when the processing is completed, the switching processing by time division is prohibited.

That is, during the time division switching prohibited period from time T3 to time T4, the time division switching timing t happens to occur.
3, the time-division switching is not performed at the same timing t3, so that the DRAM 27 is not interrupted until the data reading (writing) processing for all bytes is completed, and the refresh operation is not performed. Is performed reliably, and all of the stored data is stored and held. After the time T4 when the time division prohibition is released, the time division switching is performed at every predetermined time division switching timing t5, t6,..., And the parallel processing is continued.

As described above, at least one C
A computer 10 including a PU 11 is provided, and a plurality of sets of control programs corresponding to a plurality of functions such as a facsimile function, a print function, and a scanner function are incorporated in a ROM 12 of the computer 10, and the plurality of sets of control programs are concurrently executed in a time-division manner. In the multi-function information processing apparatus 1 capable of simultaneously realizing a plurality of functions by performing the processing, DR among the plurality of subroutines included in the image reading and transmitting control program of the facsimile function
Since a subroutine for reading (writing) data to the AM 27 incorporates a switching prohibition step of prohibiting time division switching until the subroutine is completed, a plurality of sets of control programs are processed in parallel in a time division manner. When the dynamic RAM 27 is accessed by a called subroutine, time-division switching is prohibited until the subroutine is completed by a switching prohibition step incorporated in the subroutine. The refresh operation performed for each read process or write process is not interrupted by time-division switching, so that the disappearance of stored data can be reliably prevented.

After the time division prohibition is released, the time division switching is performed at every predetermined time division switching timing t, so that the parallel processing of a plurality of sets of control programs by the time division switching is continued. . Here, as a modification of the above-described embodiment, the DRAM 27 has a 4K
It may have various memory capacities, such as 16 bits or 16K bits, or may be provided instead of the RAM 14. Furthermore, the present invention may be applied to various electronic devices that include at least a computer and employ a multi-function parallel processing method that simultaneously realizes a plurality of functions such as arithmetic processing and information input / output processing.

[0035]

According to the multi-function parallel processing electronic apparatus of the first aspect, the computer includes at least one CPU, ROM, and RAM, and a plurality of sets of control programs corresponding to a plurality of functions are incorporated in the ROM. In an electronic device capable of simultaneously realizing a plurality of functions by executing two or more sets of control programs in parallel in a time-division manner, a dynamic device having an internal refresh function and performing a refresh operation for each data read process or write process is provided. Since a RAM is provided and a subroutine for accessing the dynamic RAM among a plurality of subroutines included in the control program incorporates a switching prohibition step of prohibiting time division switching at least until the subroutine is completed. Control program is time division When the dynamic RAM is accessed by the called subroutine during the parallel processing, time-division switching is prohibited until the subroutine is completed by the switching prohibition step incorporated in the subroutine. Instead, the refresh operation performed for each of the read processing or the write processing is not interrupted by the time-division switching, so that the disappearance of the stored data can be reliably prevented.

According to the multi-function parallel processing electronic device of the second aspect, the same effect as that of the first aspect is obtained, but a plurality of sets of control programs to be processed in parallel among the plurality of sets of control programs are time-divided. Switching means for sequentially switching at a predetermined switching timing is provided, and the switching means is configured not to perform the switching at the predetermined switching timing when the time division switching is prohibited by the switching prohibiting step. When the control programs are processed in parallel, the plurality of sets of control programs to be processed in parallel are sequentially switched at a predetermined switching timing by time division by the switching means, but time division switching is prohibited by the switching prohibition step. When it is
Switching at the switching timing by the switching means can be reliably prohibited.

According to the multi-function parallel processing electronic device of the third aspect, the same effect as in the second aspect can be obtained, but the switching means performs a predetermined switching after the switching prohibition in the switching prohibiting step is released. Since the switching is performed at the timing, when the switching prohibition by the switching prohibiting step is released, the switching is performed at a predetermined switching timing by the switching means thereafter, and a plurality of sets by the time division switching are set. The parallel processing of the control program can be continued.

[Brief description of the drawings]

FIG. 1 is a block diagram of a control system of a multifunction information processing apparatus according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating address management of a DRAM.

FIG. 3 is a block diagram of a control system of the personal computer.

FIG. 4 is a schematic flowchart of a data read (write) subroutine of a DRAM.

FIG. 5 is a schematic flowchart of a time division switching process control routine;

FIG. 6 is a time chart illustrating an operation when a facsimile function and a print function are simultaneously processed in a time-division manner.

[Explanation of symbols]

 Reference Signs List 1 multi-function information processing apparatus 10 computer 11 CPU 12 ROM 14 RAM 20 control unit 27 DRAM 27a peripheral circuit

Claims (3)

(57) [Claims] 1. At least one CPU, ROM, and R
A computer comprising an AM is provided, and a plurality of sets of control programs corresponding to a plurality of functions are incorporated in the ROM, and two or more sets of control programs are processed in parallel in a time-sharing manner, so that a plurality of functions can be simultaneously realized. In the electronic device, a dynamic RAM having an internal refresh function and performing a refresh operation for each data read or write process is provided, and among a plurality of subroutines included in the control program, a subroutine for accessing the dynamic RAM includes: A multi-function parallel processing type electronic device incorporating a switching inhibition step for inhibiting time division switching at least until the subroutine is completed. 2. A switching means for sequentially switching a plurality of sets of control programs which are processed in parallel among the plurality of sets of control programs at a predetermined switching timing by time division, wherein the switching means performs the switching by the switching prohibiting step. 2. The multi-function parallel processing type electronic device according to claim 1, wherein when time division switching is prohibited, switching is not performed at a predetermined switching timing. 3. The multi-function according to claim 2, wherein said switching means switches at said predetermined switching timing after said switching prohibition in said switching prohibition step is released. Parallel processing electronic device.