JPH024916B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to data processing, and more particularly, the present invention includes a first storage device for storing character font data for displaying a plurality of characters, each character being stored in a bit map of a predetermined size according to the font data. , the plurality of characters are stored according to a specified storage sequence, and an image comprising a preselected one of the characters is displayed in a predetermined background area. an image display device for displaying a bitmap representation of the image; a second storage device for storing a bitmap representation of the image; and a second storage device for controlling the image display device to display the bitmap representation of the image in the second storage device. The present invention relates to a general data processing device including a visualization control device for visually displaying the image in accordance with stored character font data. One data processing display device of the general type described above is disclosed in U.S. Pat. No. 4,103,331.
This device works well for word processing using a limited set of character fonts, such as the alphabetic alphabet and various mathematical symbols. In the case of such a limited set of characters, character font data representing the entire set of characters can be stored in the main memory of the device. US Patent No. 4103331
The main memory disclosed in the publication is a solid-state random access memory that has a considerably faster access time than conventional low-speed memories such as disk memory and tape memory. US patent application Ser. No. 781,266, filed March 25, 1977, discloses a data processing apparatus specifically designed to process Japanese writing style. Japanese is,
It is a writing style that combines four different sets of characters: Romaji, Hiragana, Katakana, and Kanji. There is no problem in handling the hiragana and katakana character sets in terms of the number of pieces. That is, there are 46 hiragana characters and 46 katakana characters, so all character font data can be stored in a solid-state main memory with relatively high speed access. However, this is not the case with a much larger set of Kanji characters. In other words, there are approximately 10,000 kanji characters.
Of these 10,000 characters, there are, for example, 3,000 characters that are frequently used, and because of the limited bit capacity of current solid-state memory, external storage devices such as disks are required. It is necessary to use Thus, one drawback of the apparatus disclosed in U.S. Patent Application No. 781,266 and U.S. Pat. Accessing character font data from storage or similar devices is rather slow. This access time problem is
It becomes even larger when the character font data stored in the disk memory is in a specified storage sequence that is completely different from the desired specified display sequence. When dealing with sets of characters in the thousands, if the character font data is accessed from disk memory according to this specified display sequence, Japanese characters can be formatted and displayed. The speed at which this can be done will be severely limited. There is a need, therefore, to improve the access time for character font data from an external, fairly slow access storage memory over that currently available in word processing devices such as the prior art devices described above. In order to meet this demand, the general type data processing device according to the present invention is equipped with a character sorting device. More specifically, the data processing device of the present invention includes a third storage device for storing a list of identification label data for at least some of the preselected characters to be visually displayed; The identification label data identifies the type and style of each character and the desired location of the character in the background area, and further comprises a data control device for controlling the processing and handling of the character font data; The control device includes a sorting device for sorting the identification label data in the third storage device into the specified storage sequence, and further includes a sorting device for sorting the identification label data in the third storage device, and further includes a sorting device for sorting the identification label data in the third storage device, and further includes a sorting device for sorting the identification label data in the third storage device. an access device for accessing character font data for each character identified in the list in the specified storage sequence from a storage device; and a second storage device for storing character font data for each accessed character. The present invention is characterized in that the bitmap display is further provided with a loading device for loading the bitmap display into a location determined by identification label data for the character. Therefore, if the first storage device is formed, for example, by a magnetic disk type memory, the character font data is accessed in the specified sequence in which the characters are stored on the disk. These characters are not accessed from the disk in the order in which they are visually displayed, ie, displayed or printed. As a result, each track containing the desired character font data only needs to be accessed once. That is, the head only needs to be moved once over the track, which significantly reduces the overall access time for character font data stored on disk. In the case of a Japanese language processor, the time required to access Kanji character font data from disk is greatly reduced by the above-described "single access" feature of the present invention. These and other aspects and advantages of the present invention will become apparent from the following detailed description with reference to the drawings. FIGS. 1 and 2 show a data processing apparatus according to the present invention. This data processing device has a central processing unit (CPU) 10 consisting of a data section 12 and a control section 14. This data processing device also includes main memory 1
6 and a plurality of peripheral devices, some of which have associated controllers. Specifically, this data processing device includes a keyboard 18, an attached disk drive controller 2
2, a display device 24 with an attached display controller 26, a cursor device 28 with an attached cursor device controller 29, a raster output scanning (ROS) printer 30 with an attached ROS printer controller 32, and A communication circuit 34 with an attached circuit controller 36 is provided. Keyboard 18 is uncoded and does not require a separate controller. Information is transferred via main data transfer bus 38.
The data is transferred to and from the data section 12 of the CPU 10. Processor 10 in this embodiment is designed to handle 16 bit parallel data, and therefore bus 38 consists of 16 parallel lines. The data bus 38 is connected to the CPU data section 12 as well as to the main memory 16 via a drive and parity circuit 40 and a 32-bit memory data bus 42. Additionally, the data bus 38 is connected to a disk drive controller 22, a display controller 26, a cursor device controller 29,
It is connected to the ROS printer controller 32, circuit controller 36, and keyboard 18. Information is therefore provided directly from the keyboard onto the data bus 38. On the other hand, the disk drive section 24, the cursor device 28, and the ROS printer 30
and communication circuitry 34 are both peripheral devices to which information is transferred by and through the respective controllers 22, 26, 29, 32 and 36. That is, a suitable bus 44 is connected between the disk drive 20 and its controller 22, a bus 46 is connected between the display device 24 and its controller 26, and a bus 47 is connected between the cursor device 28 and its controller 26. A bus 48 is connected between the ROS printer 30 and the controller 32, and a bus 50 is connected between the communication circuit 34 and the controller 36. Bus 44, 46, 47,
The nature and structure of many of the signals transferred through 48 and 50 will now be described. The disk drive controller 22, the display controller 26, and the circuit controller 36 all perform the functions to be performed by the CPU 10.
When one or more services are required, 1
One or more task request signals can be generated in the form of a "wake up" command. Cursor device controller 29 and ROS
Printer controller 32 does not use task requests. The disk drive controller 22 can generate two request signals: KSEC (disk sector task) and KWD (disk word task). These signals are routed through their respective task request lines 52.
It is added to the CPU control section 14. The display controller 26 provides three task request signals related to the display of data: DWT.
(Display Word Task), DHT (Display Horizontal Task) and DVT (Display Vertical Task), these signals are sent to the CPU through their respective task request lines 52.
It is added to the control section 14. Furthermore, the display controller periodically generates a CURT (cursor task) task request signal, and the CPU 10
to execute program routines related to handling cursor data. The circuit controller 36 is capable of generating a single task request signal, NET (Network Task), which is transmitted over its line 52.
It is added to the CPU control section 14. Other task request signals are generated within CPU 10. This signal is used for MPT (main program task), MRT (memory refresh task) and
PART (parity task). The MPT task request signal is related to the main microprogram routine stored in the CPU controller 14 and is always true. That is, the main microprogram routine always requests service. The above MRT task request signal becomes true every 38.08μs, and the main memory 1
Refresh the information stored in 6. The PART task request signal goes true whenever a parity error is detected by parity circuit 40. In order to notify each of the controllers 22, 26, and 36 when the CPU 10 is executing instructions related to the requested service, the control unit 14 includes means described below.
A "task active" status signal is sent back to the controller. These task active signals are transmitted to the control unit 1 as shown in FIG.
4 via line 54 to controller 22,2
6 and 36. Two task active lines 54 are connected to the disk drive controller 22 (related to the KSEC task and KWD task), and four task active lines are connected to the display controller 26 (related to the DWT task, DHT task). , DVT tasks, and CURT tasks), and one task active line 54 is connected to circuit controller 36 (related to NET tasks). The CPU 10, particularly its control unit 14, will be described in detail. Generally, the control unit 14 provides instructions to the data unit 12 for execution. Additionally, instructions in the form of control signals are routed through respective control lines 56 to various inputs/outputs (I/Os).
O) Controllers 22, 26, 29, 32 and 3
6 and executed by the controller. The instructions are sent and executed according to a particular sequence or routine and are identified for the particular task to be serviced. The control section includes means described below,
It is adapted to determine which of the plurality of wakeup task request signals applied to the controller 14 has the highest current priority value. Specifically, each of the plurality of tasks to be serviced is preassigned a unique priority value. That is, execution of services requested of display controller 26 has a higher priority than execution of services requested of circuit controller 36. The control unit 14 sends instructions associated with the highest current task to be serviced to the data unit 12 and the respective I/O controllers for execution. As shown above, the cursor device controller 2
There are no task request signals provided from 9 and ROS printer controller 32. The display controller 26 generates program routines related to processing cursor information.
Processed in response to the CURT task request signal. A printing task is initiated by an operator pressing a command key on keyboard 18. This causes a number of selectable commands to appear in the keytop area 9 on the display device 24.
6 (FIG. 6). One of the commands is a print command, which print command is selected by hitting a key on the keyboard 18 that corresponds to the location of the print command within the keytop area. Details regarding this will be explained later with reference to FIG. However, it is noted here that print command signals generated by keyboard 18 are translated by CPU 10 as "print task requests" and then serviced in the manner described above. To further elaborate on FIG. 12, CPU10
The control unit 14 includes a priority encoder 158 whose task request input terminals are connected to various task request lines 52 from the I/O controllers 22, 26 and 36, and various output lines 162 from the decoder 160. is connected to receive the internally generated task request signal described above, such as the MRT. Task request signal MPT requests the main program to be serviced and is always true (low) as evidenced by ground line 164. Therefore, the main program is always requesting services. Priority encoder 158 includes circuitry (not shown) for generating a multi-bit control signal on each of a plurality of lines 166 with respect to the highest priority wakeup task request signal currently applied as an input to encoder 158. I'm here. Priority encoder 158 has a further input terminal adapted to receive a RESET signal on line 168 from initialization circuit 170.
This will be explained in detail later. Now, the control signal generated on line 166 is applied to the respective input terminals of a current task register 172, which registers are responsive to the control signal to generate a multi-bit address signal, which address signal is in bit-parallel format. is applied to each of a plurality of lines from register 172 to respective input terminals of address memory 176. Address memory 176 preferably includes a plurality of storage locations, each formed by a plurality of multi-bit registers (not shown). Preferably, address memory 176
There are a number of registers equal to and associated with a plurality of tasks that may be performed by CPU 10 as described above. Each register in address memory 176 is addressed by a unique multi-bit code formed by an address signal applied thereto from current task register 172 on line 174. In this embodiment, address memory 176
Each of the registers within can store the next address of an executable microinstruction stored in microinstruction memory 178. In this regard, each of the plurality of address memory registers can be thought of as a program counter for a respective task to be serviced with respect to a corresponding microinstruction stored in instruction memory 178. Each instruction stored in memory 178 is accessed in response to a corresponding address signal applied on address line 180 from address memory 176. Each instruction includes an instruction field, preferably consisting of 22 bits, and a next address field, preferably consisting of 10 bits. This instruction field is loaded into the instruction register 182 via line 184 and then transferred to the CPU via a suitable decoder 160.
10 data portions 12. Some of these decoded instructions are also sent to I/O controllers 22, 26 and 36. The next address field is sent back to the currently addressed register in address memory 176 via line 186. In this manner, each of the plurality of registers within memory 176 can be accessed from instruction memory 178 for execution in accordance with the particular task to be serviced.
always contains the address of the next microinstruction stored in the microinstruction. Portions of the 22-bit instruction field of each of the microinstructions described above are adapted to perform various special functions, some of which are connected to the I/O controllers 22, 26 via control lines 188. and 36 respectively to control the controller, and some are applied via control line 190 to address modification circuit 192 for branching. In this example,
Each microinstruction has a 4-bit special function ``subfield'' within the instruction field, and 2 of the 16 4-bit codes that can be formed are each ``task''.
(TASK) function and "BLOCK" function. Instructions accessed
Once decoded by the appropriate one of decoders 160, the TASK signal component is output on line 19.
4 to the current task register 172 to enable it and cause it to be loaded with an address signal representing the current highest priority task requesting service. This address signal is then applied to address memory 176. The decoded BLOCK signal is applied via another line 194 to the current task register 172 to disable it. The multi-bit address signal present at the output of current task register 172 is applied to address memory 176 via line 174 as well as to task active decoder 198 via line 196. The decoder 198 is responsive to the address signal output of the register 172 and selects one of the plurality of TASK-1s described above depending on the current highest priority task to be serviced.
One of the ACTIVE signals is generated on each line 54. Decoder 198 includes a delay circuit and provides a signal to each I/O controller.
The TASK-ACTIVE signal is delayed by one processor clock cycle. In this way, the appropriate TASK-ACTIVE signal is generated at times corresponding to the execution of instructions associated with the task to be serviced. The controller 14 also includes a clock generator 200, as shown in FIG.
to the task active decoder 198 via line 204, to the address memory 176 via line 206, and to the initialization circuit 170 via line 208. 12, initialization circuit 170 is responsive to a START signal generated when an operator turns on the device. When this START signal is received, circuit 17
A normal circuit in 0 generates a RESET signal and this
The RESET signal is sent to the priority encoder 158 via line 168, to the current task register 172 via line 120, to the task active decoder 198 via line 212, and to the instruction memory 178 via line 214.
is applied to instruction register 182 and decoder 160 via line 216 and to address modification circuit 192 via line 218. Upon receiving the RESET signal, the control unit 14
various components of the system are reset. Initialization circuit 170 also generates a multi-bit initialization address signal on each of the plurality of lines 120 in response to the START signal. In this embodiment, there are 16 possible tasks and associated registers in address memory 176. Therefore, the above initialization address signal is a 4-bit signal,
This signal is initially zero, or 0000, and increases at the rate of the CLOCK signal pulses applied to line 208.
can be increased by increments. The RESET signal above is 16
cycle, or 16 CLOCK signal pulses, at which time the initialization address signal on line 120 goes from zero (0000) to 14 (1111).
increases to The address signal output of the current task register 172 during initialization matches the initialization address signal described above. During initialization, the address signal output of current task register 172 is applied to address memory 176 via AND gate 222, which is enabled by the RESET signal from initialization circuit 170. In this way, address signal (0000) is loaded into register number zero in address memory 176, and address signal 1 (0001) is loaded into register number zero in address memory 176.
is loaded into register number 1, and so on. This process initializes the address memory by setting various registers within the memory to their starting values. For details of the CPU control unit 14 other than those mentioned above,
See, if necessary, US Pat. No. 4,103,330. Next, to explain Fig. 13, CPU10
The data section 12 preferably includes a pair of 32-word register files (R register file 22).
4 and S register files 226), and a number of 1-word registers (T registers 228, L registers 230,
M register 232, memory address register (MAR) 234, and instruction register (IR) 236). The data section 12 also includes an arithmetic logic unit (ALU) 238, a pair of multiplexers 240 and 242, a PROM 244,
It includes a shifter 246, a constant memory 248, and a main memory decode and control circuit 250. As shown in FIG.
a first data input terminal connected to data bus 38 for receiving data from the bus; and
It has a second data input terminal connected to the output terminal of ALU 238. The control input terminal of multiplexer 242 is connected to the output terminal of PROM 244 to control the multiplexer so that its data input is applied at its output terminal. The output terminal of multiplexer 242 is connected to T register 228. The load control of the above T register is performed by the control unit 1.
The output terminal of the T register 228 is connected to the ALU 238. ALU238 is determined by the output of PROM244.
Limited to 16 possible arithmetic and logic functions. PROM 244 is controlled by four control lines from control section 14 of CPU 10. ALU23
The output terminal of 8 is connected to each input terminal of the L register 230, the M register 232, and the MAR 234, and
As mentioned above, it is connected to multiplexer 242. The load control output terminal of the L register 230 is connected to the second input terminal of the M register 232 to control the loading of data thereto, and the second inverted output terminal of the L register 230 is connected to the second input terminal of the M register 232 . is connected to the inverting input terminal of This shifter can shift left and right by one digit and eight cycles. L register 2
The load control of 30 is performed by a load control signal applied from the control section 14. shifter 246
The output terminal of is connected to the inverted data input terminal of the R register file 224, and the output terminal of the M register file 23
The output terminal of S register file 226 is connected to the inverted data input terminal of S register file 226. The output terminals of register files 224 and 226 are both connected to data bus 38. Various functions of the shifter 246 are controlled by control signals from the control section 14. Register files 224 and 226
also receives a control signal from the output terminal of multiplexer 240 and is addressed by an address control signal from controller 14. multiplexer 24
0 itself receives various input control signals from the controller 14. MAR 234 has its output connected to memory address bus 80 and is adapted to apply a 16-bit address signal to main memory 16. Additionally, this 16-bit address signal is applied to decode and control circuit 250, which applies a control signal to main memory 16 via line 82. These control signals relate to the manner in which the 16-bit values stored in main memory are transferred to the driver and parity circuit 40 via the 32-bit memory data bus 42. Instruction register 236 is used by emulator microcode routines and
Retains the currently emulated microinstructions. Therefore, the input terminal of IR 236 is connected to data bus 38, as is the 16-bit output terminal. Additionally, the various output bits (1-4) of the 16-bit output terminal are connected to multiplexer 240 via output lines.
Finally, constant memory 248 is preferably 256 words of 16-bit PROM that holds arbitrary constants. The output terminal of this constant memory is connected to the data bus 38, as shown, and is addressed by a control signal from the control section 14. See US Pat. Nos. 4,103,331 and 4,148,098 for details of conventional alternatives to data section 12. Next, the main memory 16 will be explained in detail with reference to FIG. Memory 16 is preferably capable of storing 65536 16-bit words.
It is an 850μs error correction semiconductor memory. memory 1
The first section 60 of 6 can form and store a bitmap representation of an image to be displayed on display device 24 or a "slice" or segment of an image or page to be printed on ROS printer 30. The direction of this slice may be either the length direction or the width direction, but preferably the width direction. In this embodiment, the resolution capability of printer 30 is significantly greater than that of display device 24. Therefore, it is not possible to create all bitmaps for one page to be printed in the bitmap data section, ie, the first section 60. A bitmap for a page to be printed is then established on a disk in the disk drive 20 and then transferred into widthwise slices, each of which is a predetermined number of bits long. The slices are transferred to the memory 16 and then to the ROS printer controller 32 slice by slice. This will be explained in detail later. A second section 62 of main memory 16 is adapted to store a "Display Control Block" and a "Disk Command Block."
These two blocks are collectively called "DCB". DCB
For the purpose of display controller 2
6 and the disk drive controller 22 will be described later. The third section 64 of the main memory 16 includes:
The first set of characters, i.e. “small”
Character font data for characters is stored and displayed. These small display characters preferably consist of a subset of roman, katakana, and hiragana characters, and each character is preferably formed from a 7.times.7 bitmap matrix. Furthermore, due to this relatively small scale and the complexity of the Kanji character subset, a single "dummy" Kanji character consisting of a predetermined 7x7 bit map matrix pattern is used as a set of small display characters. (see character numbered 65 in FIG. 6). Preferably, only a small display character is displayed in the first page display area 66 on the display device and used for page formatting purposes and the like. This will be explained in detail later with reference to FIG. Fourth storage section 68 of main memory 16
form a pair of data buffers 70 and 72 (FIGS. 9-11). The purpose of these data buffers is to accept "strikes" of large display characters from the disk drive controller 22 and to send selected ones of the characters within each strike to the bitmap data section 60. data buffer 7
How to control 0 and 72 will be explained later. However, it is noted here that the larger set of display characters includes a subset of Roman, Katakana, Hiragana, and Kanji characters. Each character is 18 wide
It is formed by a font data bitmap matrix with a height of 20 bits. Additionally, each character's strike consists of 512 16-bit words,
Therefore, it consists of 22 characters. Preferably,
Only large display characters are displayed in the second text display area 74 (FIG. 6). This forms an enlarged portion of the full page being opened and is used for editorial and inspection purposes. This will also be explained in detail later with reference to FIG. The fifth section 76 of main memory 16 is 1
Form a paired bitmap generation control list. One of these lists is for display and the other for printing. An example of the display bitmap generation control list is shown in FIG. Generally, the bitmap generation control list for a display consists of a list of all large display characters to be displayed. Each such character is listed by a 12-bit character code, which identifies this character and its sets (large display) and subsets (hiragana, katakana, etc.) and its style (bold, italic). , etc.). Additionally, for each character in this list, the x and y coordinate values at which the character is to be placed within the display bitmap are provided. Preferably,
The x and y coordinate values determine the upper left corner of the 18 bit wide by 20 bit high bitmap matrix that forms each large display character. This will be explained in detail later with reference to FIGS. 7 and 8. However, here, using the information contained in the display list,
It is noted that character font data for large display characters is accessed from a disk memory contained in disk drive 20. This data is then loaded into data buffers 70 and 72 for ultimate storage in the appropriate location within bitmap data section 60 and then used for display. Another bitmap generation control list formed in section 76 of main memory 16 is for printing. This list is basically the same as above. However, this list lists the print characters to be included in the particular slice of print bitmap data that is currently being opened. Here, a complete bitmap for printing is formed by arranging one slice at a time on a disk memory, as described above. As will be explained later, the print characters are preferably formed from character font data bitmaps, each of which is 32 bits high and 32 bits wide. This printed character font data is stored in disk memory and preferably includes a complete set of Roman, Hiragana, Katakana and Kanji characters. As each slice of print bitmap data is formed in the bitmap data section 60 and then used for printing, the slice is transferred into disk memory. A new print bitmap generation control list is then established to form the next adjacent print bitmap slice. Once a complete print map has been created and stored on disk memory, this print map is retransferred slice by slice to the bit map data section 60 and from there.
Retransferred to the ROS printer controller 32,
This is serial output to the ROS printer 30. Display device 24 must be left blank during printing. This is because only one bitmap data section 60 is used and to increase memory speed. As will be appreciated, if additional main memory storage space is provided, separate display and print bitmap storage sections can be created. A sixth and final section 78 of main memory 16 is allocated for storage of other data and programs. In particular, program routines associated with the data processing apparatus of the present invention are loaded into section 78 from disk drive 20.
It is finally executed by the CPU 10. As shown in FIGS. 2 and 3, main memory 16 is addressed by a 16-bit address signal applied from data section 12 of CPU 10 to address bus 80. As shown in FIGS. Additionally, appropriate memory control signals are applied from the data section 12 to the main memory via line 82. These control signals divide two 16-bit words into 32 bits during a read operation.
A method for applying bits to the memory data bus to the driver and parity circuit 40, and during a write operation from the circuit 40 to the memory data bus 4.
2 determines how to separate and store the 32-bit composite word provided in main memory 16. Address signals on bus 80 each contain 16 bits.
Controls the location where words are to be stored or retrieved. Additional details regarding the preferred main memory 16 are disclosed in U.S. Pat. Nos. 4,103,331 and 4,148,098. Having described the various storage sections of main memory 16 above, disk memory 84 will now be described with reference to FIG. In this embodiment, disk drive 20 comprises a Diablo model 31 or model 44 disk drive. Both drives can accommodate a removable disk cartridge (not shown) containing a disk memory 84. As is customary, disk drive 20 includes means for reading data from and writing data to both sides of disk memory 84. Preferably, each side of the disk memory has 12 sectors and up to 406 tracks. For convenience of explanation, disk memory 84 is shown in FIG. 4 in the same format as main memory 16 in FIG. 3. However, unlike main memory 16, where 16-bit words are accessed in parallel, 16-bit words are accessed serially from disk memory 84, one bit at a time. Thus, in forming the five elementary sections of the disk memory 84, the data contents of these sections are stored serially in the distinguishable sections of the distinguishable tracks on the two storage surfaces of the disk. As shown in FIG. 4, a first storage section 86 of disk memory 84 is connected to a
is adapted to store a complete bitmap of the page of text to be printed. This page consists of the print characters described above. That is, each print character is formed from a 32-bit x 32-bit character matrix. As previously mentioned, character font data representing the bitmap matrix for each print character is stored in the second font data storage section 8 of the disk memory 84.
8 and includes characters for each subset of Romaji, Hiragana, Katakana, and Kanji.
The print bitmap is opened one slice at a time in the bitmap data section 60 of the main memory 16, then transferred to the print bitmap section 86 of the disk memory, and then transferred to the bitmap data section 60 of the main memory and the main data transfer bus. 38 to the ROS printer controller 32. Print character data is stored in font data storage section 88 as 512 16-bit word "strike"s. Therefore, 32×
With a 32 bit map matrix, there are 8 printed characters within each strike. Preferably, six strikes are stored on each track, each strike occupying two adjacent sectors. To make data easier to access,
A predetermined specified storage sequence (e.g., A,
B, C, D...) to store print character data and number each strike. Then, in this embodiment, strike numbers 0-5 are stored in one track on one side of the disk;
Strikes 6 to 11 are stored in tracks corresponding to the above tracks on the other side of the disk, strikes 12 to 17 are stored in adjacent tracks on the first side of the disk, and so on. Third storage section 9 of disk memory 84
0 stores a bitmap matrix 18 bits wide by 20 bits high that forms each of the large display characters. Also, font data for this large display character is stored with each strike having 512 words. That is, there are 22 characters per strike. The manner in which the strikes are stored on the disk surface is preferably the same as for the printed character strikes described above. As mentioned earlier, the set of large display characters is preferably complete Roman, Hiragana,
Contains a subset of each character in Katakana and Kanji. 4, a fourth storage section 92 of disk memory 84 is adapted to store various "text files."
These files contain data representing each document being opened. Each document consists of a predetermined number of pages and is identified by a predetermined code within the text file. Each page of the document is identified by a number within the text file. The information content of the page is identified within the text file by a character identification list. Each character on each page (not a particular set of characters, such as large display characters) is identified in the list by its 12-bit identification code. Additionally, the list includes data about the relative positions of the characters on the page. Create a list for each page in the text file on CPU10
Depending on whether the data is to be displayed or printed, a display bitmap generation control list (FIG. 8) or a print bitmap generation control list can be generated. As previously mentioned, any such list is stored in main memory storage section 76.
(Fig. 3). A fifth and final storage section 94 of disk memory 84 contains other data and programs, such as the main program for carrying out the data processing operations of the apparatus of FIGS. 1 and 2. As mentioned before, this program
When CPU 10 wants to execute this program, it is loaded into storage section 78 of main memory 16. Next, the keyboard 18 will be explained in detail with reference to FIG. As previously mentioned, the keyboard 18 is preferably uncoded, and each of the 63 of the 68 keys shown in FIG. 5, when pressed, produces one of the 63 output lines. Corresponding 1
It is designed to generate signals on two lines.
Each of the remaining five keys, along with an associated one of the original 63 keys, is adapted to generate a signal on the 64th output line. Therefore, 68 output states are formed on the 68 bit output. The 64-bit output from this keyboard is then sent to the main memory 16 via the data bus 38.
(FIG. 3) directly to a pre-allocated storage location in storage section 78 (FIG. 3).
This 64-bit output is actually four 16-bit outputs.
It is added as a word and preferably stored in four adjacent storage locations. This 64-bit output value is then sent to CPU1 under program control.
Sampled periodically by 0. Specifically, each time a key is pressed, the corresponding output line becomes true (binary 0). All other output lines are false (binary 1). The CPU 10 detects this under program control during each sample period and converts the true signal into a 12-bit signal representing the key pressed.
encode into code. As shown in FIG. 5, the keyboard 18 has a group of character keys including characters from the standard alpha and numeric character set and the hiragana character set.
Four additional character keys contain flat characters, so this character set is 48
characters, and the standard Roman characters mentioned above contain only 44 characters. In addition to the character keys described above, there are various function keys and command keys shown below.

[Front] Rakuta key and hiragana key
Rakuta keys are all hiragana characters.
encoded as data.

[Table] Referring again to FIG. 2, the display device 24 and display controller 26 will be described in detail. The display device is preferably a standard CRT display device, such as a standard 875-line raster-scan TV monitor, and is read at a rate of 60 fields per second from a display bitmap formed in storage section 60 of main memory 16. will be refreshed. Display device 24 preferably includes 606 display points (pixels) horizontally and 808 pixels vertically, for a total of 489,648 pixels. Display controller 26 handles the transfer of image data between bitmap storage section 60 of main memory 16 and display device 24. The basic method for displaying image data on a display device is to pull a series of 16-bit words from a display bitmap in storage section 60 of main memory, and then serially extract the bits that form the video signal. . The serial video bits are applied to display device 24 via bus 46. Each scan line consists of 38 16-bit words of the display bitmap. The actual display is formed by one or more display control blocks (DCBs) within storage section 62 of main memory 16. Basically, each DCB contains data that determines the resolution, margins, and positive/negative characteristics of the display.
Additionally, if more than one DCB is used to display data, the DCBs are linked together starting at a predetermined location within main memory 16. This location is in section 78 of main memory and represents a pointer to the first DCB in this chain.
Each subsequent DCB contains a pointer to the next DCB in the chain. Each DCB also contains bitmap start addresses for the two scan lines (odd and even) within each field. For additional details of DCBs applicable to display controller 26, see US Pat. No. 4,103,331. As shown in FIG. 14, display controller 26 includes a 16 word buffer 252 and is adapted to accept image data from bitmap data section 60 of main memory 16 via data bus 38. For that purpose, Batsuhua 2
52 16-bit parallel output terminals are connected to bus 38. Buffer 252 is loaded word by word with 16 words of image data in response to a load command applied on line 266 from control circuit 254. Control circuit 254 includes means for interpreting and decoding various control signals applied to the circuit's input terminals from CPU control 14 via line 56 (FIG. 2). Batsuhua 252
The data stored in one word buffer 252 is connected to the output line of buffer 252.
56, one word at a time. Buffer 256 also connects line 26 from control circuit 254 to
When a load command is received via 8, it is loaded. The output line of buffer 256 is connected to a serialization shift register 258 which serializes the data and transfers it to digital mixer 26.
Give to 0. Register 258 is synchronicity generator 2
62 and applied to line 270. Synchrony generator 262 also provides appropriate video synchronization signals to display device 24 via associated lines of bus 46 (FIG. 2). The BITCLK signal is also applied via line 270 to each clock input terminal of control circuit 254 and cursor shift register 264. This will be explained later. Shift register 258 is loaded with a 16-bit word from the output terminal of buffer 256 upon receiving a load command from control circuit 254 via line 272. Control circuit 254 also sends a load command to cursor shift register 26 on line 274.
4, allowing the register to be loaded with a 16-bit word of cursor data. The above control circuitry also supports the three main microcode task request signals previously mentioned, namely:
It includes means for generating DVT (Display Vertical Task), DHT (Display Horizontal Task) and DWT (Display Word Task). The vertical task described above is "awake" once per field at the beginning of the vertical retrace. The horizontal task described above is woken up once at the beginning of each field and then woken up (essentially at the end of each horizontal scan line) when the word task (DWT) is blocked. The word task described above is controlled by the state of the buffer 252, ie, whether it needs to accept more image data. In addition to these three task request signals, control circuit 254 may also generate a cursor task request signal (CURT) for each horizontal line. This cursor task is CPU1
Enable 0 and cursor device control 2
It processes the x and y coordinate data given to it from 9 via the data bus 38. To further explain FIG. 14, the cursor shift register 264 has its 16 parallel input terminals connected to the data bus 38, and the cursor shift register 264 has 16
Bit words are adapted to be accepted from storage section 78 of main memory. The above storage section contains 16 pieces that form the cursor data.
16 bit words are stored. This will be explained in detail later. Cursor shift register 26
4 is loaded upon receiving a load command from control circuit 254 via line 274 and via line 270 from synchronicity generator 262.
Clocked by the BITCLK signal. The serialized cursor data bits are provided from the output of register 264 to the other input of digital mixer 260, which then merges the cursor data with the image data from bitmap data section 60. The video bits at the output of the mixer are applied via associated lines of bus 46 to display device 24 where they are raster scanned onto the display screen. For additional details regarding the preferred display controller 26, reference may be made to U.S. Pat. No. 4,103,331. Next, referring to FIG. 6, the display device 24
The various display areas and how these areas are generated are described. Generally, the display screen is capable of displaying data on a standard paper size type scale, such as A4 size. The total number of display pixels, i.e. 489,648 pixels, is stored in the main memory 16 where the data to be displayed is mapped.
It has a corresponding bit location in the bit map data section 60 of. So, CPU10
is programmed to effectively separate the entire display into a keytop area 96, a message display area 98, a page display area 66, and a text display area 74. A keytop display area 96 is located in the upper quarter of the display screen. This area generally includes a display of 30 blank keytops arranged in three columns of 10. Each column is separated into a left half and a right half, each with five keys. These keys form a "temporary keyboard" into which the operator can enter more different kinds of symbols than there are keys on the keyboard 18. Therefore, and also as mentioned before, after typing a hiragana character into text,
KANJI mode key press 30 with the same sound
Up to five Kanji characters (from a set of large display characters) are displayed in the keytop display area 96. The most common Kanji characters with typed pronunciation are underlined. To select one of the displayed kanji and replace it in the text, press one of the keys in the group of 30 keys (shown in dashed lines and numbered 100 in Figure 5) in the display area. 96, press a key that corresponds in position to the key position of the kanji character in the temporary keyboard. Keytop area 96 is also used to display a "menu" of commands, including print commands, and to select these commands in the same manner as for Kanji characters. The commands preferably consist of words formed by small display characters. Message area 98 is preferably a white character on a black background display and separates keytop display area 96 from the bottom three-quarters of the display screen. The information displayed in message area 98 includes the name of the document being processed, the page number of the currently displayed page, the amount of unused space for document storage remaining in disk memory 84, and the currently used typing. Contains the mode (e.g. Hiragana). This area is also used to display status and error messages to the operator.
The information displayed in message area 98 also preferably consists of words and symbols formed of small display characters. A page display area 66 displays an entire page of text and an outer edge 67 of fixed size and location.
has. However, inside the edge 67, the operator can form at least one "text box". This text box is simply a rectangular area, the dimensions of which can be determined by the operator, and inside which are displayed small display characters forming the text being processed. The operator can set the size and position of each text box within the edges 67 that define the page, and whether each box has an edge margin. The illustration shows, by way of example, a border margin 10 forming a single text box within the page display area 66.
2 is shown. The operator can also set the "pitch" or spacing between small display characters within text box 102 and the "leading" or spacing between rows within text box 102. A text box may also contain non-deletable fixed text, such as a title for a style, etc. The text box margins 102 can be set by the operator using the cursor device 28. This will be explained in detail later. Text display area 74 is essentially an enlarged portion of the full page display within page display area 66. That is, only small display characters are preferably used in area 66;
Preferably only large display characters are used in area 74. The operator controls whether the text display area is "active" and, if so, its vertical dimension. When the text display area is active, it overlies and replaces a portion of the page display area 66, as shown in FIG. The operator is
Cursor device 28 can be used to adjust both the top margin 104 and bottom margin 106 of text display area 74. I will explain how to do that later. Since the text display area enlarges a portion of the full page within the page display area 66, the text display area can display a full page of text even if it is physically the same size as the full page display. I can't. Thus, the operator typically uses the text display area for editing and viewing text, and the page display area for arranging the text on the page. With reference to FIGS. 2 and 6, the cursor device 28
and the cursor device controller 29 will be explained. Cursor 108 can be displayed at any location on display device 24. The cursor 108 consists of an arbitrary 16-bit by 16-bit patch (indicated by the arrow) which, at the appropriate time, is applied to the digital mixer 260 (fourteenth point) of the display controller 26.
(Fig.) is merged with the image data formed by the display bitmap data. The bit map for the above cursor is main memory 1.
16 in memory section 78 (Figure 3) of 6
Included in bit words. Furthermore, cursor 10
The x and y coordinates for 8 are each 10 bits.
words and are stored in separate 16-bit word locations within storage section 78. In other words, each 10-bit coordinate value is 16
Stored as the 10 least significant bits of the bit word. The coordinate origin for the cursor is the top left corner of the screen. This cursor display is unaffected by changes in display resolution. Positioning of cursor 108 is controlled by an operator using cursor device 28 . This cursor device is often referred to as a "mouse." cursor 10
8 are buttons 110, 112 and 1 on the mouse 28
14 (FIG. 1) to control the typing, editing, command and viewing states of this data processing device. Button 110 controls the organization of text display area 74 and the top margin 104 and bottom margin 106 of this display area.
It is used to change the inspection status, such as determining the Mouse 28 includes an x,y coordinate generator in the form of an x and y position transducer (not shown).
This transducer has a mouse 28 along the work surface.
generates a train of x and y pulses in response to the movement of . These x and y position signals and button command signals are applied to CPU 10 via cursor device controller 29. Therefore, the cursor device controller 29 is basically the mouse 28.
Serves as a storage and front interface via data bus 38 to and from CPU 10. The five output lines of the mouse are included as the five most significant bits of a 16-bit signal applied to data bus 38 by cursor device controller 29 under microcode control. This 16-bit signal is then interpreted by the CPU 10 to execute the button commands added and the 10-bit x-coordinate values and 10 The bit y coordinate value is updated. For further details of the preferred mouse 28, reference may be made to US Pat. No. 3,392,963. An alternative to mice is also disclosed in US Pat. No. 3,987,685. Referring again to FIG. 2, the disk drive controller 22 will be described in detail. The preferred disk drive controller 22 is designed to accommodate a variety of disk drives, such as the aforementioned Diablo models 31 and 44, which are the preferred replacement for disk drive 20. Disk drive controller 22 records three independent blocks of data in each track sector of disk memory 84 (FIG. 4). The first data block is two 16-bit words long and contains the address of the sector. This is called a "head block." The second data block is called the "label block" and is eight 16-bit words long. The third data block is called the "data block" and is 256 16-bit words long. Each block can be read, written or checked independently. However, once writing begins, it continues until the end of the sector. The main program of this data processing device, which can begin running on CPU 10, communicates with disk drive controller 22 via a four word block of main memory 16 located in storage section 78 of main memory 16. . The first word is interpreted as a pointer to a chain of disk command blocks (DCBs) stored in storage section 62 (FIG. 3) of main memory 16. A disk command block is a 10-word block of main memory in storage section 62 that represents a disk transfer operation to disk drive controller 22 and is used by the controller to perform this operation. Record the condition. Disk drive unit controller 22 of this embodiment
comprises the circuit shown in FIG. 15 and the two microcode tasks mentioned above, namely the sector task (KSEC) and the word task (KWD). FIG. 15 shows the data path within the disk drive controller 22. Specifically, data is loaded from data bus 38 into buffer 280;
After being buffered in the buffer, it is loaded into the shift register 284. Register 284 serially transfers data indicated by output signal DATAOUT, which is phase encoded by data encoder 286 into signal WRITE DATA.
An oscillator 288 clocks this data and sends it to the disk drive 22 via an encoder 286.
Write on the disk surface of the disk memory 84. Data is read from the disk surface and decoded by data decoder 292. The output of this decoder is the output from shift register 284.
Multiplexer 2 under the control of the DATAOUT signal
94. The output of multiplexer 294 is shifted through shift register 296 and loaded into buffer 298 under control of signal BITCLK. Signal BITCLK is a clock signal generated by multiplexer 302 which enables a clock signal approximately equal to one-half the frequency of the signal generated from oscillator 288 to data encoder 286 and data decoder 292. Responds to clock signal READ CLOCK. signal
Under control of BIKCLK, buffer 298 transfers groups of 16 bits of read data to bus 38 in parallel. Control circuit 304 responds to microcode control signals from CPU control section 14 and provides load command signals to various buffers and registers shown in FIG. 15, as well as to disk drive section 20. Additionally, this circuit is responsive to receiving a status signal from disk drive 20 and relays the status signal to data bus 38. This circuit further generates the two task request signals mentioned above, and sends a related task active signal to the CPU controller 1.
Received as a return from 4. For additional details of the preferred disk drive controller 22, reference may be made to U.S. Pat. No. 4,148,098. Next, to explain the ROS printer 30 and its controller 32 shown in FIG. 2, the raster output scanning printer 30 accepts print bitmap data from the controller 32 in a serialized format, and then records this data in an appropriate manner. Any suitable device that can be scanned across the media can be used. An example of such a ROS printer is the Fuji Xerox 1660 printer manufactured by Fuji Xerox Co., Ltd. of Tokyo, Japan. Also,
The ROS printer controller 32 receives 16 print bitmap data from the data bus 38.
Any suitable device capable of accepting bit words and then serializing, synchronizing, and transmitting them to printer 30 can be used. ROS printer 30 and its controller 32
Additionally or alternatively, a ROS printer and associated controller (not shown) may be used at a location remote from the apparatus of FIGS. 1 and 2. One family of ROS printers for use in remote locations include laser scanning xerographic printers, such as the Xerox 7000 copier, which has been modified to include laser scanning ROS optics.
An example of an optical device used in an electrophotographic copier/copier, such as the Xerox 7000 copier, is described in US Pat. No. 3,995,110. A suitable ROS printer controller for controlling such a printer is described by Butler W. Lampson (for "Electronic Image Processor").
Lampson et al., U.S. patent application no.
No. 899751. Print bitmap data is provided to the apparatus of the above-mentioned application via a communication circuit 34. Other examples of ROS printers include:
There is a Xerox 9700 computer printer manufactured by Xerox Corporation of El Segundo, Calif., and a controller for use with this printer is disclosed in U.S. Pat. No. 4,079,458.
The remote ROS printer and associated printer controller illustrated above can be used as printer 30 and controller 32 in place of the Fuji Xerox 1660 printer and associated controller described above, if desired. Referring again to FIG. 2, any suitable communications circuitry 34 and circuit controller 36 may be used to provide data to stations or devices external to the apparatus of FIGS. 1 and 2. Examples of communication circuits and controllers for them are:
Some are disclosed in US Pat. No. 4,063,220. For further details on this circuit and controller, reference may be made to this patent. The main components of the data processing device shown in FIG. 1 have been explained using the block diagram shown in FIG.
The manner in which character font data (large display or print characters) is transferred from disk memory 84 to the appropriate storage location in bitmap data section 60 of main memory 16 will now be described. This process will be described by way of example for the transfer and storage of large display characters, but as will become clear, the process is the same for the transfer and storage of print characters. First, FIG. 7 shows a temporary display bitmap generation control list. This list lists the characters in a specified visualization display sequence, ie, the order in which the characters should be scanned and displayed. The list in Figure 7 is tentative. That is, when actually creating the list, the characters are sorted by CPU 10 into a specified disk storage sequence, ie, the order in which the characters are stored in disk memory 84 (FIG. 8). The list in FIG. 7 merely represents the way characters are generally listed and does not include the unique character sorting features of this data processing system. As shown in FIGS. 7 and 8, this display bitmap generation control list generates identification labels for all large display characters to be displayed on the display screen using a 12-bit identification label code and a 10-bit x and y Contains each coordinate value. This list therefore contains identification label data for all large display characters to be displayed in all large character display areas on the display device, such as text display area 74 and keytop display area 96. The x and y coordinate values are stored in the display bitmap data section 60 of the main memory 16.
ensuring the correct location of every character in the screen ensures the display of that character in the proper location on the screen. The small display character does not appear in this display bitmap generation control list in main memory. That is, the font data itself resides in the main memory.
Therefore, no sorting is necessary for the character identification label data for these characters, and these characters appear in the character identification label list in the text file located in storage section 92 of disk memory 84. Therefore, these characters are displayed according to their specified display sequence, and not according to the order in which they are stored in main memory. For convenience of explanation, the display bitmap generation control lists shown in FIGS. 7 and 8 are each only 13 characters long. Additionally, the 12-bit character identification label code and 10-bit x and y coordinate values for each large display character in this list are numbered, and the numbers representing the 12-bit identification label code are stored in disk memory 84. represents the number of that character within the large display character set stored in the display. For example,
Character number 2 in the sequence "0, 1, 2..." is Roman character C, character number 4 is Roman character E, and below,
The same is true for the entire set of large Roman, Hiragana, Katakana and Kanji display characters (sometimes over 10,000 in total).
The numbers representing each 10-bit x and y coordinate value are designed to be numerically equivalent to the actual 10-bit digital value. As previously mentioned, the display screen is approximately 600 pixels wide by 800 pixels high, and the display bitmap contains the same number of bit storage locations. Therefore, character 2 is located at the coordinates x=500, y=200, and character 4 is located at the coordinates x=200, y=100.
and so on. Needless to say, these x and y values are purely hypothetical;
It is provided by way of example only. In establishing the actual display bitmap generation control list of FIG. The first thing to do is to create a list. As previously mentioned, the character identification label data appearing in the text file is in a specified visualization display sequence, ie, the order in which the characters are to be scanned for visualization display. The specified sequence of characters listed in the temporary control list of FIG. 7 is the same as the specified sequence of characters in the text file list. However, as mentioned earlier, the text file list is a 12-bit identification label code as well as "letting" and "pitching".
In contrast, what appears in the bitmap generation control list is a 12-bit identification label code and x and y coordinate data. Sorting of characters until arriving at the actual display bitmap generation control list shown in FIG. 8 is performed by the CPU 10 under program control. More specifically, the data section 12 of the CPU 10 preferably implements a standard "tree sort" algorithm. Details of such algorithms can be found in Communication of the ACM, Volume 7,
No. 12 (December 1964) by Robert D.
Please refer to "Tree Sort 3", Algorithm No. 7, written by Robert W. Floyd. By executing the program routine that provides this algorithm, the character information in the display bitmap generation control list is determined in the order in which characters are scanned for display (as exemplified by the hypothetical list in Figure 7). The characters are listed in the sequence stored in disk memory 84. This allows a single access to each track on the disk surface to display all large display characters stored in the six strikes on that track in the text display area 74 and keytop display area 9.
6 (FIG. 6).
Tree sorting 3 for character sorting
Details of the preferred program routine for the algorithm are set forth in the program listing in Appendix C attached hereto. As previously mentioned, large display characters are stored on disk memory 84 in strikes of 22 characters each. That is, the first strike (Strike 0) includes large display characters 0-21, the second strike (Strike 1) includes large display characters 22-43, and so on. FIG. 8 shows which strike each of the listed characters is in. This relationship stores character font data for each listed character in main memory 1.
The procedure for actually entering the proper location of the display bitmap in section 60 of 6 is important. To explain in more detail with reference to FIGS. 9-11, character font data is transferred using a pair of data buffers 70 and 72 formed within data buffer section 68 of main memory 16. The bitmap data section 60 of main memory 16 is loaded. In other words, the CPU 10 under program control is
First, examine the bitmap generation control list,
Check to see if any characters from Strike 0 are in this list. Referring to the example of FIG. 8, there are five such characters in this example, numbers 2, 4, 5, 17 and 19. Next, the CPU 10 transfers the 22 characters of strike 0, ie, characters 0 to 21, to the data buffer 70. This transfer commands the disk drive controller 22 to read strike 0 to the disk drive 20, and then causes the disk drive controller to read this strike 16.
This is done by adding the bit words to the transfer bus 38 and transferring them to the data buffer 70 of the main memory 16 in bit-word order. At this stage, the data buffer 72 is open. The CPU 10 then reads the 16-bit words in order:
Characters 2, 4, 5, 17 and 19 are transferred from the data buffer 70 to the main memory 16 determined by the values of the x and y coordinates for each character.
The bitmap data section 60 of the character is transferred to its respective location in the bitmap data section 60 of the character. That is, CPU 10 reads the x and y coordinate values for each character and then transfers the first 16-bit word thereof to the bitmap data section. At about the same time that characters are being transferred from the data buffer 70 to the bitmap data section, the CPU 10
checks whether any character in the bitmap generation control list is in strike 1 on the disk memory. If the character is in strike 1, which is the case in FIG. 8, CPU 10 transfers strike 1 to data buffer 72 in data section 68 of main memory in the manner described above. This step is the 10th step.
As shown in the figure. FIG. 11 shows the next step in the above process, namely the transfer of characters 33, 42 and 43 (the only characters in strike 1 in the list of FIG. 8) from data buffer 72 to bitmap data section 60 of main memory. This shows that. Since character number 59 appears in the above list, data buffer 70 is reloaded with the 22 characters of Strike 2 at approximately the same time as above. This procedure is repeated to transfer all large display characters to be displayed in the entire image to display bitmaps in storage section 60 of main memory. Exactly the same procedure is used for strikes of print character data stored in font data section 88 of disk memory 84.
This is done by the CPU 10 under program control. However, for print data strikes, as mentioned earlier, each 512 word strike consists of only eight characters.
This is because the bitmap forming the matrix for each print character is 32 bits x 32 bits, whereas the map matrix for each large display character is 18 x 20 bits. Also, as previously mentioned, the full print bitmap (residing in disk memory 84) stores the character font data for each slice in a designated storage sequence following character sorting into the bitmap of main memory 16. Slices are opened one by one by transferring the bitmap slices to the data section 60 and then sending the bitmap slices to the disk drive controller 22 to load the corresponding slices of all print bitmaps. Details of program routines associated with establishing display and print bitmap generation control lists and transferring listed characters from disk memory 84 to main memory 16;
Routines related to the formation of multiple display areas on display device 24 are each described in the program listing in Appendix C, which is attached hereto and constitutes a part of this specification. For these routines, there are three execution languages commonly used in software for this data processing device. These are microcode, assembly language and BCPL from the lowest level to the highest level. BCPL is a high level Algol (ALGOL)
BCPL Reference Manual, published by the Xerox Palo Alto Research Center, May 30, 1977, is a programming language for
Manual). Although the present invention has been described above with reference to its embodiments, those skilled in the art can make various modifications, substitutions, etc. without departing from the spirit and scope of the present invention as defined by the claims.

[Brief explanation of drawings]

FIG. 1 is a perspective view of the data processing device of the present invention, and FIG.
The figure shows a block diagram of the data processing device shown in Fig. 1, Fig. 3 shows various storage areas in the main memory shown in Fig. 2, and Fig. 4 shows the magnetic recording disk in the disk drive section shown in Fig. 2. FIG. 5 is a top view showing the arrangement of keys in the keyboard shown in FIG. 2; FIG. 6 is a diagram illustrating an image display on the display device shown in FIG. 2; It is. FIG. 7 is a diagram showing a temporary display bitmap generation control list stored in the main memory of FIGS. 2 and 6, in which characters are arranged in a designated visualization display sequence. FIG. 8 is a diagram showing the display bitmap generation control list of FIG. 7, in which the characters are sorted into designated storage sequences.
FIGS. 9-11 show loading a large character strike from a disk into a data buffer formed in the main memory of FIGS. 2 and 3 for display, and then from this data buffer to a bitmap data portion of the main memory. FIG.
Fig. 12 is a block diagram of the control section of the CPU shown in Fig. 2, Fig. 13 is a block diagram of the data section of the CPU shown in Fig. 2, and Fig. 14 is a block diagram of the display controller shown in Fig. 2. 15 is a block diagram of the disk drive unit controller shown in FIG. 2. 10...Central processing unit (CPU), 12...CPU
Data section, 14...CPU control section, 16...
Main memory, 20...Disk drive unit, 22...
... Disk drive controller, 24 ... Display device, 26 ... Display controller, 28 ... Cursor device, 29 ... Cursor device controller, 30 ... Raster output scanning (ROS) printer, 32 ... ROS printer controller, 34...Communication circuit, 36...Communication circuit controller, 38...Main data transfer bus, 4
0...Driver and parity circuit, 42...Memory data bus, 60, 62, 64, 68, 76, 7
8...Storage section in main memory, 80...
. . . memory address bus, 84 . . . disk memory, 86, 88, 90, 92, 94 . . . storage section within disk memory.

Claims (1)

[Scope of Claims] 1. A first storage device for storing character font data representing a plurality of characters, each of the characters being displayed as a bitmap of a predetermined size by the font data,
the plurality of characters are stored in a specified storage sequence; a second storage device for storing a bitmap representation of the image; and a second storage device for controlling the image display device to display the image according to character font data stored in the bitmap representation of the image in the second storage device. and a third storage device for storing a list of identification data for at least some of the preselected characters to be visually displayed. , said identification data identifying the type and style of each character and its desired location on said background area, further comprising a data control device for controlling the processing and handling of the character font data; The data control device includes a sorting device for sorting the identification data in the third storage device into the specified storage sequence, and a sorting device for sorting the identification data in the third storage device into the specified storage sequence, and an access device for accessing character font data for each identified character in said list in an accessed storage sequence; and said bitmap display in said second storage device for character font data for each accessed character. a loading device for loading the character into a location determined by identification data for the character. 2. A data processing device according to claim 1, wherein the image display device comprises a raster output scanning device. 3. A data processing device according to claim 2, wherein said raster output scanning device is a CRT display device. 4. The data processing device according to claim 2, wherein the raster output scanning device is a ROS printer. 5. The data processing device according to claim 1, wherein the first storage device includes a first random access memory. 6. The data processing device according to claim 5, wherein the first random access memory is a magnetic storage medium. 7. The data processing apparatus according to claim 6, wherein the second and third storage devices respectively include first and second storage areas within a second random access memory. 8. The data processing apparatus according to claim 7, wherein said second random access memory comprises a solid state memory device. 9. The data control device is coupled to a central processing unit and the first storage device, and controls access to character font data from the first storage device, and controls access to character font data from the first storage device, and a storage control device for controlling transfer to a processing device, coupled to the central processing device, the storage control device, the second storage device, and the visualization control device, from the storage control device to the central processing device; and a data transfer bus for enabling transfer of character font data from the central processing unit to the second storage device and from the second storage device to the visualization control device. A data processing device according to claim 1. 10 The data control device further comprises an address bus coupled between the central processing unit and the second storage device for applying address signals from the central processing unit to the second storage device. A data processing device according to claim 9. 11 The image display device includes a CRT display device, the first storage device includes a magnetic random access memory device, and the second and third storage devices include first and third storage devices on a solid state random access memory device. The data processing device according to claim 1, each comprising a second storage area. 12 The image display device includes a ROS printer,
The first and second storage devices each include a first and second storage area on a magnetic random access memory device, and the third storage device includes a first storage area on a solid state random access device. A data processing device according to claim 1, comprising: 13 The patent further comprises a buffer storage device formed in a second storage area of the solid state random access memory device, the buffer device storing character font data accessed from the first storage device. Claim 12
The data processing device described in Section 1. 14 further comprising a fourth storage device for storing predetermined segments of the bitmap representation of the image, the fourth storage device being formed in a third storage area on the solid state random access memory device; The data control device controls the transfer of character font data from the buffer device to the fourth storage device, and the data control device also controls the transfer of character font data from the buffer device to the fourth storage device. 14. The data processing device according to claim 13, which controls the transfer of character data between. 15 Claim 1 further comprises a display device for displaying the image.
4. The data processing device according to item 4. 16 The fourth storage device stores segments of the printed bitmap during image formation and stores the segments of the print bitmap during image formation.
16. A data processing device as claimed in claim 15, used for printing by a ROS printer or for storing a complete display bitmap during image formation and displaying by said display device. 17. The data processing device according to claim 1, wherein the plurality of characters include Roman characters, Hiragana characters, Katakana characters, and Kanji characters, thereby making it possible to process Japanese text.