JP3797517B2 - Bus expansion system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus expansion system used for bus expansion in an information processing apparatus, a control apparatus for an electronic exchange, and the like.
[0002]
[Prior art]
In general, in an information processing apparatus, when predetermined communication is performed between functional units connected through a bus, the bus right adjustment is performed. That is, until one communication is completed, the bus is locked, and control is performed so that other communication is not interrupted. This is called a bus lock system. When there are many functional units to be connected to the bus, a predetermined bus expansion device is used to connect a plurality of buses. When a device with such bus expansion is controlled by a normal bus lock method, all the buses are often occupied by one functional unit for a long time, resulting in poor communication efficiency. Therefore, the bus is controlled by the split bus method.
[0003]
In the split bus system, one communication is divided into a plurality of cycles such as a command cycle and an answer cycle, and bus contention is taken in each cycle. This shortens the time for occupying the bus in one communication. Furthermore, when bus expansion is performed, all the buses are occupied at once by performing bus arbitration separately between the basic bus, the expansion bus, and the inside of the bus expansion device that connects the two. Control so that nothing happens.
[0004]
[Problems to be solved by the invention]
By the way, the conventional techniques as described above have the following problems to be solved. For example, consider a case where an interface buffer is provided in a bus expansion device that connects a basic bus and an expansion bus, and an interface is provided between the basic bus and the expansion bus. When reading data from a register connected to this buffer through this buffer, if the command cycle ends and another communication uses the buffer, the command read into the buffer in the command cycle is rewritten with another communication data. End up.
[0005]
Therefore, when a register is provided in the bus expansion device, a dedicated buffer for holding commands and the like is provided between the register and the buffer to prevent rewriting. However, in this case, when a number of registers are provided in the bus expansion device, there is a problem that the amount of hardware increases as a whole.
[0006]
[Means for Solving the Problems]
The present invention adopts the following configuration in order to solve the above points.
<Configuration 1>
One bus expansion device connected to the basic bus and the other bus expansion device connected to the expansion bus , the interface buffer provided in each of the one and other bus expansion devices, and for these interfaces An intermediary buffer connected to the buffer via an inter-unit bus , a register storing data read by the intermediary buffer, and the inter-unit buffer with respect to any of the buffers that first output a bus right request and a bus arbitration unit for setting a bus of the bus, the basic bus and the interface buffer which has received the read command through one of said expansion bus, receives the setting of the bus right for the inter-unit bus supplying the read command to the intermediary buffer, command receiving a normal response from the intermediary buffer Opening the bus to detect the end of the cycle, the mediation buffer, the conjunction from the register to supply running the read command and receives the read command to the buffer for the interface to read out the data In the bus expansion system that outputs the normal response to the interface buffer , the intermediary buffer receives the read command and outputs the normal response to the bus arbitration unit before starting the answer cycle. outputs a bus right request, the bus arbitration unit receives the said bus request from the mediation buffer before release of the bus of the buffer the interface, the said intermediary buffer after opening of said bus unit setting the bus right between bus, bus expansion system characterized in that.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described using specific examples.
<Concrete example>
FIG. 1 is a block diagram showing a bus expansion system of the present invention.
The apparatus shown in the figure adopts a split bus system, and the microprocessor chip 2 of the processor 1 accesses the basic bus 3, while the function unit 6 connected to the expansion bus 5 via the bus expansion devices 4A and 4B. The register 7 can be accessed. A bus expansion device 4A for expanding the basic bus 3 and a bus expansion device 4B for expanding the expansion bus 5 are connected to each other by an inter-unit bus 8.
[0009]
The bus expansion device 4A is provided with a buffer 9A and a bus arbitration unit 10. The bus expansion device 4B is provided with buffers 9B and 9C and a register 11 directly connected to the buffer 9B. The buffer 9A is a buffer for taking an interface between the basic bus 3 and the bus expansion device 4A. The buffer 9C is a buffer for taking an interface between the expansion bus 5 and the bus expansion device 4B. The buffer 9B is a buffer for taking an interface when the expansion bus 5 is accessed from the basic bus 3 through the bus expansion device 4A. Data transfer between the buffer 9A and the buffer 9C is performed via the buffer 9B. Is called. Furthermore, the buffer 9B allows access to the register 11 in the bus expansion device 4A.
[0010]
In the above configuration, when data is transferred from the processor 1 connected to the basic bus 3 to the register 7 in the functional unit 6 connected to the expansion bus 5, the following procedure is executed.
First, the processor 1 secures the bus right of the basic bus 3 by bus contention adjustment, and transfers the corresponding data to the buffer 9A. When a normal response is returned from the buffer 9A, the processor 1 releases the bus right of the basic bus 3. Next, the buffer 9 </ b> A requests the bus right of the inter-unit bus 8 to the bus arbitration unit 10 via the request / acknowledge line 12. When the bus right is secured, the data is transferred to the buffer 9C via the buffer 9B, and after confirming a normal response, the bus right of the inter-unit bus 8 is released. The buffer 9C acquires the bus right of the expansion bus 5 and transfers the corresponding data to the register 7 in the functional unit 6.
[0011]
As described above, data transfer from the basic bus 3 to the expansion bus 5 is performed. These procedures are the same as those performed in the conventional system.
Next, consider a case where the processor 1 accesses the register 11 via the buffer 9B. According to the split bus method, one communication is divided into a command cycle and an answer cycle. First, after an access request command is stored in the buffer 9A by the processor 1, a command cycle is executed by the buffer 9A. That is, a command is transmitted from the buffer 9A to the buffer 9B, and preparations for reading data from the register 11 are made.
[0012]
During this time, the buffer 9A acquires the bus right of the inter-unit bus 8, and completes a series of command cycles.
In the next answer cycle, a procedure such as request, acknowledge, answer, and status response is executed by the buffer 9B. That is, a command is transferred from the buffer 9A to the buffer 9B by the command cycle, and data corresponding to the buffer 9A is returned from the buffer 9B as a response by the next answer cycle.
[0013]
However, according to the principle of the split bus system, the inter-unit bus 8 is temporarily opened between the command cycle and the answer cycle. Therefore, if there is another access request using the buffer 9B during this period, the command cycle can be interrupted. When another command cycle is interrupted, the command taken into the buffer 9B is overwritten with other data and disappears.
[0014]
The inter-unit bus 8 is released when the buffer 9B receives the normal status, negates the request (invalid state), and the bus arbitration unit 10 negates the acknowledgement.
[0015]
Therefore, in the present invention, when an access request to the register 11 is made, the command cycle and the answer cycle using the buffer 9B are continuously performed, and the use of the buffer 9B by another communication is prevented. . For this purpose, the buffer 9B sends an answer cycle request to the bus arbitration unit 10 before returning a status for releasing the bus right. As a result, the bus right is preferentially reserved. Thereafter, when the status is returned, the bus right preferentially moves to the buffer 9B, and the buffer 9B can execute the answer cycle while keeping the internal state.
[0016]
FIG. 2 shows a specific inter-unit bus sequence chart based on the above principle.
In the figure, it is assumed that two types of communication {circle around (1)} and {circle around (2)} using the buffer 9A are requested successively. Communication (1) is a data access request to the register 11. Communication (2) is an access request to the buffer 9C. First, when the bus right of the inter-unit bus 8 is given to the communication {circle around (1)} that makes the access request first, the command cycle of the communication {circle around (1)} is started.
[0017]
In step S1, a request is made from the buffer 9A to the bus arbitration unit 10, and in step S2, the bus arbitration unit 10 acknowledges to give the bus right to the buffer 9A. Next, a command is transmitted from the buffer 9A to the buffer 9B (step S3), and the command is transferred from the buffer 9B to the register 11 (step S4). The buffer 9B then sends a status to the buffer 9A, but immediately before that, sends a request for an answer cycle to the bus arbitration unit 10 (step S5). Subsequently, the status is transmitted to the buffer 9A (step S6).
[0018]
If there is a request from the buffer 9B before the status is returned from the buffer 9B and the bus right by the buffer 9A is released, the bus arbitration unit 10 gives the bus right to the buffer 9B in preference to the communication (2). . Therefore, after the command cycle for communication (1) is completed, the answer cycle for communication (1) is continuously executed. That is, an acknowledge is transmitted from the bus arbitration unit 10 to the buffer 9B, the bus right is given to the buffer 9B (step S7), and data is read from the register 11 to the buffer 9B (step S8).
[0019]
The buffer 9B executes an answer for transferring the read data to the buffer 9A (step S9). Finally, in step S10, the buffer 9A transmits a status to the buffer 9B. Thus, a series of data access processing from the buffer 9A to the register 11 is completed. Thereafter, a command cycle for communication (2) is started. That is, a request is made from the buffer 9A to the bus arbitration unit 10 (step S11), and the bus arbitration unit 10 returns an acknowledge in response thereto (step S12).
[0020]
The buffer 9A thus acquires the bus right of the inter-unit bus 8, and transmits a command to the buffer 9C through the buffer 9B (steps S13 and S14). In response to this, the buffer 9C returns a status to the buffer 9A via the buffer 9B (steps S15 and S16). Thus, the command cycle of communication (2) is completed.
[0021]
Next, when the answer cycle of communication {circle around (2)} is started, a request is transmitted from the buffer 9C to the bus arbitration unit 10 (step S17), and an acknowledgment in response thereto is returned (step S18). When acquiring the bus right, the buffer 9C returns an answer to the buffer 9A through the buffer 9B in step S19 (step S20). When the answer is received, the buffer 9A returns a status to the buffer 9C through the buffer 9B (steps S21 and S22).
[0022]
FIG. 3 shows an inter-unit bus sequence chart of a comparative example for explaining the effect of the present invention.
If general split bus control is performed without performing the above control, the sequence shown in FIG. In this case, a buffer 9D is provided between the register 11 and the buffer 9B. The buffer 9D is provided to hold the command for a certain period when the register 11 is accessed.
[0023]
Communication {circle over (1)} is for an access request from the buffer 9A to the register 11 as already described. Communication (2) is an access request from the buffer 9A to the buffer 9C. Here, the processing of step S1 to step S6 is a command cycle of communication (1). When the command cycle of communication {circle around (1)} is executed and the bus right of the inter-unit bus 8 is released, the command cycle of communication {circle around (2)} is executed. After that, when the inter-unit bus 8 is released, an answer cycle of communication (1) is executed, and finally an answer cycle of communication (2) is executed.
[0024]
When processing proceeds in such a procedure, when the command cycle of communication (1) is executed, the command stored in the buffer 9B is for communication (2) when the command cycle of communication (2) is executed. It will be overwritten by the commands needed for. Therefore, the buffer 9D holds the command, the answer cycle of the communication (1), reading of data from the register 11 according to the stored commands in the buffer 9 D is performed.
[0025]
However, providing such a dedicated buffer 9D for each of the registers provided in the bus expansion device increases the size and cost of hardware. Compared to this, in the system of the present invention shown in FIG. 1, the register 11 can be directly connected to the buffer 9B, so that a dedicated buffer is not required. In addition, in the above example, the bus expansion device is configured by connecting two types of devices having a bus arbitration unit and a register, but these devices can take any configuration, and on either side A bus arbitration unit may be provided.
[0026]
【The invention's effect】
As described above, an arbitrary number of registers 11 can be provided in the above bus expansion device, and these are all buffers 9B arranged so as to function as an interface between the basic bus 3 and the expansion bus 5. It becomes possible to connect directly to. Therefore, the hardware configuration of the bus expansion device can be simplified and downsized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a specific example of a bus expansion system of the present invention.
FIG. 2 is an inter-unit bus sequence chart according to the present invention.
FIG. 3 is an inter-unit bus sequence chart of a comparative example.
[Explanation of symbols]
1 Processor 3 Basic bus 4A, 4B Bus expansion device 5 Expansion bus 6 Functional unit 9A, 9B, 9C Buffer 10 Bus arbitration unit 11 Register

Claims (1)

One bus expansion device connected to the basic bus and the other bus expansion device connected to the expansion bus , the interface buffer provided in each of the one and other bus expansion devices, and for these interfaces An intermediary buffer connected to the buffer via an inter-unit bus , a register storing data read by the intermediary buffer, and the inter-unit buffer with respect to any of the buffers that first output a bus right request and a bus arbitration unit for setting the bus of the bus,
The interface buffer that receives a read command via either the basic bus or the expansion bus receives the setting of the bus right of the inter-unit bus and supplies the read command to the intermediary buffer. When receiving the normal response from the buffer and detecting the end of the command cycle, the bus right is released,
The mediation buffer is a bus for outputting the normal response to said buffer for the interface with running and receives a read command the read command from the register to be supplied to the buffer for the interface to read out the data In the extended system,
The intermediary buffer outputs a bus right request to the bus arbitration unit to start an answer cycle before receiving the normal response after receiving the read command ,
When the bus arbitration unit receives the bus right request from the intermediary buffer before the bus right of the interface buffer is released, the bus arbitration unit sets the bus right of the inter-unit bus in the intermediary buffer after the bus right is released. To
A bus expansion system characterized by that.

Images