JPH0236016B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an inter-computer data transfer system for performing data transfer processing such as data communication and data transfer between computers, and particularly relates to a control system for the data transfer system. Concerning a simple data transfer system.

[Conventional technology]

In a conventional data transfer system between computers, the opposing channel devices that act as an interface for each computer system each have a built-in microprocessor and have the same configuration, and both communicate via a communication line. Data communication is generally performed according to a defined communication protocol.

FIG. 2 is a block diagram showing the configuration of such a conventional data transfer system between computers.

In FIG. 2, 1 is the central processing unit (CPU) of one computer system (hereinafter referred to as the A system), 2 is the memory of this A system, and 3 is the central processing unit of this A system. It is a common bus. Further, 4 is a central processing unit of another computer system (hereinafter, this system will be referred to as B system), 5 is a memory of this B system, and 6 is a common bus of this B system.

Furthermore, 11 and 12 are channel devices that serve as interfaces for the A system and the B system, respectively, which constitute a data transfer system between computers.

Here, the internal configurations of the channel devices 11 and 12 are the same, and 21 and 41 are microprocessors (μP), 22 and 42 are channel control registers, and 23 and 43 are microprocessor buses. , 24, 44 are memories for the microprocessor. Further, 25 and 45 are DMA control circuits, 26 and 46 are DMA circuits, 27 and 37 are line control circuits, and 28 and 48 are line interface circuits. and 60 is a dual channel device, 1
This is a communication line between 1 and 12.

For example, through a communication device with such a configuration,
When attempting to transfer data from system A to system B, data transmission is performed according to the following procedure.

First, the memory address of memory 2 where the data to be transferred by CPU 1 is stored, the number of bytes to be transferred, B
When a command requesting transfer to the system and other necessary information are set in the channel control register 22, an interrupt is notified to the microprocessor 21 by this setting, and the microprocessor 2
1 controls the line control circuit 27 to perform predetermined processing as a line link establishment process for communication with the microprocessor 41 of the channel device 12 of the B system.

Here, when the line control circuit 27 operates on the opposing line control circuit 47 to establish a link, data is transferred between the microprocessor 21 and the microprocessor 41 according to a specified communication protocol. Ru.

Now, when the microprocessor 41 receives the data transfer request from the microprocessor 21,
Raise an interrupt to CPU 4 to notify that there is a data transfer request from system A.

Upon receiving this notification, the CPU 4 transfers information consisting of the memory address of the memory 5 to which data should be received, a command for permitting data transfer, and, if necessary, the number of bytes to be transferred, to the channel control register 4.
Set to 2.

Microprocessor 41 that recognized this setting
Based on this information, the DMA control circuit 45
It sets up the microprocessor 21, activates it, and notifies the microprocessor 21 via the line 60 that preparations for data transfer are complete.

The microprocessor 21 releases the line link for inter-microprocessor communication, and this time,
When requesting the line control circuit 27 for line control for DMA transfer between the channel devices 11 and 12,
Set up the DMA control circuit 25 based on the information set in the channel control register 22,
Start DMA transfer processing.

As a result, data sequentially read from the memory 2 via the DMA circuit 26 is transmitted to the line control circuit 27,
47, and is stored in the memory 5 via the DMA circuit 46.

In this way, data transfer is performed between the A system and the B system.

In the above explanation, data is transferred synchronously between the A system, the B system, and the CPU, but the CPU 1 of the A system transfers other information, including the transfer data storage memory address of the other system. along with the channel control register 22
If the data is set in , the channel device 12 of the B system can directly store the transferred data in the designated area of the memory 5 without any interaction with the CPU 4.

[Problem that the invention seeks to solve]

Such conventional data transfer systems between computers have the following problems.

Prior to data transfer between the A and B systems, it is necessary to communicate between the microprocessors of both channel devices.
Moreover, the communication is performed via a line that requires complicated communication control procedures. For these reasons, the overhead for data transfer becomes large, and the throughput of communication between computers becomes low.

The hardware and software for line control become complicated.

[Purpose of the invention]

The present invention has been made in view of the problems of the prior art, and in addition to solving the problems of the prior art, the device has a simple configuration, has little overhead, and The purpose of this invention is to provide an inter-computer data transfer system that allows efficient inter-computer communication.

[Means for solving problems]

The means of the present invention for solving the above problems and achieving the above object is to provide a channel device equipped with a microprocessor as a channel device of one of the computer systems in a data transfer system between computers. The microprocessor bus in the main channel device having the microprocessor and the expansion bus in the counterpart sub-channel device are configured to be connectable via the inter-channel device expansion bus, and the microprocessor bus is connected to the sub-channel device. By expanding the address space of the microprocessor bus to the other channel device for data transfer, when data is transferred between computers, the channel control information storage unit and DMA transfer control unit of each channel device are used. is coupled to the expanded microprocessor bus, and the expanded microprocessor bus is used as a DMA transfer bus between the channel devices.

[Effect]

With the above configuration, the opposing channel devices are tightly coupled, and the microprocessor can equally access the slaves such as memory and registers in both channel devices, and manage these channel devices collectively. It becomes possible to do so.

As a result, the communication control means in the data transfer system between computers becomes extremely simple, and data transfer with low overhead and high throughput can be performed.

Moreover, since only one microprocessor is required and both channel devices can be implemented with simple hardware, the entire system is simple.

Furthermore, the microprocessor can easily be used for processes other than data communication, such as sensing and controlling the state of a partner system, and can realize a wide variety of processes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an inter-computer data transfer system according to an embodiment of the present invention.
Components that are the same as those in FIG. 2 are designated by the same reference numerals.

The data transfer system between computers shown in the figure has a main channel device 13 in its own computer system, and a sub-channel device 14 in the computer system serving as its communication partner, and these main channel devices 13 and the sub-channel device The devices 14 are connected by an inter-channel device expansion bus 35.

Here, the main channel device 13 is provided with a bus expansion control circuit 30, a bus controller 31, and a bus master switching circuit 32, and the sub channel device 14 is provided with a bus slave switching control circuit 33.
, a bus slave switching circuit 34, and a sub-channel device internal expansion bus 36 are provided, respectively. The microprocessor bus 23 is connected to an inter-channel device expansion bus 35 and an intra-channel device expansion bus 36 via a bus master switching circuit 32, thereby expanding the range of this bus.

As a result, the channel control register 42 on the side of the sub-channel device 14 and the control registers included in the DMA control circuit 45 are controlled by the microprocessor bus 2.
It can be mapped onto the address space of 3. Therefore, from the perspective of the microprocessor 21, these are slaves.

Now, when the microprocessor 21 attempts to access the control register 42 of the sub-channel device 14, the bus expansion control section 30 determines the address and instructs the bus controller 31 to access the control register 42 of the expansion bus 35.
Request the use of.

After confirming that the expansion bus 35 is not being used for DMA transfer, the bus controller 31 controls the bus master switching circuit 32 to connect the microprocessor bus 23 and expansion bus 35 to Expansion bus 35 to Setusa 21
to open.

Next, the microprocessor 21 sends a program mode transfer control signal to the channel device 14 via the expansion bus 35. When the bus slave switching control circuit 33 receives the program mode transfer control signal from the microprocessor 21 from the expansion bus 35, it sends a control signal to the bus slave switching circuit 34, and transfers the control signal to the expansion bus 35 and the sub-channel device internal expansion bus. 36.

In this way, the microprocessor 21 accesses the channel control register 42 and DMA control of the sub-channel device 14 in the normal program mode, just as it accesses the memory or registers (slave circuit) in the main channel device. circuit 45
can be accessed.

In addition, when accessing via the expansion bus connected in this way, data transfer control is performed between the microprocessor 21 and the slave in a handshake mode.

Here, the microprocessor 21 activates the DMA control circuit 25 and the DMA control circuit 45 to enable data to be transferred by DMA between the main channel device 13 and the sub-channel device 14.

That is, this is the DMA circuit 26 or DMA
When data to be transferred to the other channel device side is set in the data buffer register in one of the circuits 46, and in this state, this fact is notified to the DMA control circuit 25 or the DMA control circuit 4.
When the DMA control circuit 25 or the DMA control circuit 45 is notified to the bus controller 31
request to use the expansion bus 35.

After confirming that the microprocessor 21 is not using the expansion bus 35 or making a request to use it, the bus controller 31 releases the expansion bus 35 for DMA transfer and transfers the expansion bus 35 to the bus master switching circuit 32. A route between the DMA circuit 26 and the expansion bus 35 is established via the DMA circuit 26 and the expansion bus 35. Further, the bus slave switching control circuit 33 receives the data from the expansion bus 35.
Upon receiving the DMA transfer control signal, it acts on the bus slave switching circuit 34 to open a route between the expansion bus 35 and the DMA circuit 46.

Here, DMA transfer between the DMA circuit 26 and the DMA circuit 46 can be easily realized by using the data line of the expansion bus 35, some control signal lines, and some control signal lines dedicated to DMA transfer. It is something.

By the way, since various DMA transfer methods are already known, a detailed explanation thereof will be omitted here.

Now, in this embodiment, the bus controller 31 receives data from the expansion bus 35 from the microprocessor 21 while the expansion bus 35 is being used for DMA transfer.
5, bus priority control is performed so that the DMA transfer is temporarily interrupted and the microprocessor 21 is made to use the expansion bus. Even during DMA transfer between the main and sub channel devices, the microprocessor 21 can access slaves such as the channel control register 42 on the expansion bus 36 in the sub channel device, which facilitates such processing. .

Next, the overall operation when data is communicated from system A to system B using such a data transfer system between computers will be explained.

When the CPU 1 sets a command for requesting communication between computers and information necessary for data transfer in the channel control register 22, the microprocessor 21 is notified by an interrupt.

Recognizing the request for intercomputer communication processing, the microprocessor 21 accesses the sub-channel device 14 side in the normal program mode, sends an interrupt to the CPU 4 of the B system via the channel control register 42, and sends an interrupt from the A system to the CPU 4 of the B system. Notify that there is a data transfer request.

Upon receiving this, the CPU 4 sets a command in response to the data transfer request and other information necessary for the transfer in the channel control register 42, and then sends the command to the microprocessor via the interrupt request line provided in the expansion bus 35. 21, the microprocessor 21 registers the channel control register 42.
Reads the transfer command information set in .

Next, the microprocessor 21 controls the DMA control circuit 25 according to the transfer command information from the CPU 1.
After setting up the DMA control circuit 45 according to the transfer command information from the CPU 4, the DMA transfer is started.

As a result, under the control of the DMA control circuit 25, each time the DMA circuit 26 reads data from the memory 2 and takes the read data into the input data buffer register of the DMA circuit 26, the DMA control circuit 25 is the bus controller 3
1 to use the expansion bus 35, and if it is granted, the data line and microprocessor bus phase of the expansion bus 35 are added.
Both channel devices can be controlled using DMA transfer control lines.
Controls data transfer between DMA transfer control units.

The DMA circuit 46 takes in the data sent from the main channel device 13 side into its output data buffer register, and stores this data in the memory 5 under the control of the DMA control circuit 45.

In the above embodiment, the DMA transfer control between the main and sub-channel devices is based on the conventional technology, except that the data transfer path is not a line but an expansion bus of the microprocessor bus. There is no difference.

In this way, the CPU 4 of the B system can access the memory 5 of its own system and receive the transferred data.

The above is a case where data is transferred from system A to system B.
Next, when data is transmitted to the system, the microprocessor 21 inputs the channel control register 42 in the subchannel device 14.
Access to the DMA control circuit 45, etc. is controlled by the channel control register 22 in the own channel device 13,
Since this can be done in the same way as when accessing the DMA control circuit 25, the data communication procedure can also be executed in the same way.

That is, when the CPU 4 sets a command requesting communication between computers and information necessary for data transfer in the channel control register 42, the expansion bus 35
microprocessor 21 by an interrupt via
will be notified.

The microprocessor 21, which has recognized the request for intercomputer communication processing, notifies the CPU 1 that there is a data transfer request from the B system.

Upon receiving this, the CPU 1 sets a command in response to the data transfer request and other information necessary for the transfer in the channel control register 22. At this point, an interrupt is generated in the microprocessor 21, and the microprocessor 21 reads out the transfer command information set in the channel control register 22.

Thereafter, predetermined data is transferred from the B system to the A system by the same process as described above.

Note that the transfer of data from system B to system A does not involve interrupt processing to the microprocessor 21, but rather the microprocessor 21 periodically polls the channel control register 42 and receives the request. It may be determined whether or not.

Therefore, even when the A system receives communication data from the B system under the initiative of the CPU 1 of the A system, similar processing can be performed.

Furthermore, if either system's CPU directly transfers data to or from the other system's memory without notifying the other system's CPU (without synchronizing with the other system's CPU), If the command to that effect and the memory address of the partner system are included as transfer command information in the channel control register of the channel device, the main and sub channel devices 13 and 14 can execute the process without any problem.

Here, the channel control register is not limited to a register, but may be anything that can store control information such as commands for data transfer. Therefore, a portion of memory or the like may be used, and this may be any storage device.

In addition, in the embodiment, data transfer between two systems, A system and B system, is explained as an example, but it is possible to transfer data with other computers using similar systems. Of course, such a system can be applied between computers.

Furthermore, when data is transferred between computers, the expanded microprocessor bus is used as a DMA link between the main channel device and the sub-channel device.
It is also possible to use it as a transfer bus in a time-sharing manner.

〔Effect of the invention〕

As described above, in the present invention, a channel device equipped with a microprocessor that acts as an interface for each computer system is provided as a channel device of one of the computer systems, and a main channel device equipped with this microprocessor is provided. By configuring the microprocessor bus in the channel device and the expansion bus in the counterpart sub-channel device to be connectable via the inter-channel device expansion bus, and extending the microprocessor bus into the sub-channel device, the microprocessor bus can be expanded into the sub-channel device. When extending the address space of the Setusa bus to a data transfer partner channel device and transferring data between computers, the channel control information storage unit and DMA transfer control unit of each channel device are transferred to the expanded microprocessor. the expanded microprocessor bus between the channel devices.
Since it is used as a DMA transfer bus, the opposing channel devices are tightly coupled, and the microprocessor can access the slaves in both channel devices equally and manage these channel devices collectively. becomes possible.

As a result, the communication control procedure in the data transfer system between computers becomes extremely simple, and data transfer can be performed with little overhead and high throughput.

Moreover, since only one microprocessor is required and both channel devices can be implemented with simple hardware, the entire system is simple.

Furthermore, the microprocessor can easily perform processing other than data communication, such as sensing and controlling the state of a partner system, and can realize a wide variety of processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an inter-computer data transfer system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional inter-computer data transfer system. 1, 4... central processing unit, (CPU), 2, 5,
24,44...Memory, 3,6...Common bus, 1
1, 12... Channel device, 13... Main channel device, 14... Sub channel device, 21, 23...
Microprocessor, 22, 42... Channel control register, 25, 45... DMA control circuit, 2
6, 46...DMA circuit, 27...Line control circuit, 28...Line interface, 30...Bus expansion control circuit, 31...Bus controller, 32
... Bus master switching circuit, 33 ... Bus slave switching circuit, 34 ... Bus slave switching circuit, 35
. . . Expansion bus between channel devices, 36 . . . Expansion bus within sub-channel devices.

Claims (1)

[Claims] 1. In a data transfer system between computers, a channel device equipped with a microprocessor is provided as a channel device of one of the computer systems, and the microprocessor in the main channel device having the microprocessor is The address space of the microprocessor bus is expanded by configuring the microprocessor bus to be connectable to the expansion bus in the sub-channel device of the other party via an inter-channel device expansion bus, and extending the microprocessor bus into the sub-channel device. When data transfer is extended to the other party's channel device and data is transferred between computers, the channel control information storage section and DMA transfer control section of each channel device are coupled to the expanded microprocessor bus, and the corresponding An expanded microprocessor bus connects the channel devices.
A data transfer system between computers characterized by being used as a DMA transfer bus. 2. The main channel device and the sub channel device are collectively managed by a microprocessor, and when data is transferred between computers, the expanded microprocessor bus is used as a DMA between the channel device and the sub channel device. 2. The data transfer system between computers according to claim 1, wherein the data transfer system is used as a transfer bus in a time-sharing manner.