KR20000003010A - Duplication device of processor using two common memorys and method thereof - Google Patents

Abstract

PURPOSE: Duplication device of processor using two common memories and method thereof is provided to be simple structure of hardware and software and to improve performance of system. CONSTITUTION: The device comprises two processor boards and memories for duplication, serial communication channel for serial communicating between the two processor, control channel for transmitting control signals related duplication, and data channel for transmitting duplication data and address. Thereby, it is possible to be easy control of buffer. Also, it is possible to improve performance of system.

Description

Redundant Devices and Methods for Processors Using Two Shared Memory

The present invention relates to an apparatus and method for duplication of a processor using two shared memories, and more particularly, to implement redundancy through active and long-term memory sharing in an active / standby redundant structure. An apparatus and method are provided.

In general, the existing redundancy scheme is a memory-sharing redundancy scheme in which one processor is shared by two processor boards, and each processor board has its own memory, and the memory contents of the active processor are equally updated in the standby memory. Therefore, there is a redundant structure of concurrent write that matches the memory contents between two processors.

In the former case, since a single memory is shared by two redundant processors, the redundancy structure is simple. However, if a memory problem occurs, both the active and the standby are affected. On the other hand, in the latter case, the reliability of redundancy is maintained by retaining the Mars / Standby memory itself, but there is a problem in that the structure of hardware and software for implementing redundancy is complicated.

Accordingly, the present invention has been devised to solve the above-described problems, and has two shared memories for simplifying the hardware and software structure like the memory sharing type redundancy structure while ensuring the reliability of the parallel structure redundancy structure. An object of the present invention is to provide an apparatus and method for duplexing a processor using the same.

The above and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a block diagram of a redundant device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10, 40: control channel 20, 50: data channel

30, 60: serial communication control 100, 500: processor

200, 400: memory 300: back panel

In order to achieve the above object, a preferred embodiment of a processor redundancy apparatus using two shared memories according to the present invention,

Two processor boards and memory for redundancy;

A serial communication channel for active / standby negotiation and serial communication between the two processors;

A control channel for conveying control signals associated with redundancy; And

It includes a data channel for carrying redundant data and addresses.

In the present embodiment, the serial communication channel is preferably composed of a controller for serial communication between active / standby negotiation and two redundant processors and a unidirectional buffer for transmit / receive signals.

The control channel is a path for transmitting alarm signals of each board and control signals related to active / standby redundancy, and is preferably composed of an associated signal and a unidirectional buffer.

The data channel is preferably composed of control signals necessary for memory access, an address and a data bus, and a bidirectional buffer for transferring them to the other side.

A preferred embodiment of a processor duplication method using two shared memories according to the present invention is an apparatus comprising two processor boards for duplication and a memory, a serial communication channel, a control channel and a data channel,

Two redundant processors are configured to determine activation / standby over a serial communication channel;

When the activation / standby is determined, an activation signal and a connection signal are transferred through the control channel to the active state to the atmosphere and the atmosphere to the active state;

The active signal and the connection signal is a process of determining the duplex connection by looking at the other side active signal and the other side connection signal received from the other party through the control channel;

If the duplex connection is properly established, setting the direction of the data channel address and the data buffer, and the memory control signal buffer to direct the active to the standby and the standby to enter the active; And

When the activity updates data in the memory, the process includes updating the data in the standby memory with the same data through the data channel.

In the present embodiment, when the duplex connection is properly established, the address of the data channel, the direction of the data buffer, and the memory control signal buffer are set to move outward toward the standby, and the standby is set out of active. It is desirable to block the local buffer to prevent the standby central processing unit from accessing the redundant memory area.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a duplexing apparatus according to the present invention. Referring to the configuration of the present invention with reference to Figure 1, two processor boards (10, 50) for redundancy and memory (20, 40) and serial communication channel for active / standby negotiation (negotiation) and serial communication between the two processors (Serial Communication Channel: S-CH), and Control Channel (C-CH) for transmitting control signals related to duplication, and Data Channel (D-CH) for delivering duplicated data and addresses. Is done.

The serial communication channel consists of a controller for serial communication and a unidirectional buffer for transmit / receive signals (Tx / Rx), and is used for serial communication between active / standby negotiations and two redundant processors.

The control channel is a path for transmitting alarm signals of each board and control signals related to active / standby redundancy. The control channel includes an associated signal and a unidirectional buffer.

The data channel consists of control signals needed for memory access, an address and data bus, and a bidirectional buffer for transferring them to the other side.

First, the two redundant processors decide on active / standby through the serial communication channel, and once active / standby is determined, activation sets the active signal (ACT * signal) and the connect signal (CON * signal) to low. Assert, and the activation signal and the connection signal are delivered to the atmosphere through the control channel. On the other hand, the standby keeps the active signal high and the connect signal low. The active / connected signal on the atmospheric side is also passed to the active side via the control channel.

Activation looks at the other party's active signal / counterpart connection signal (OT_ACT * / OT_CON * signal) transmitted from the other party through its active / connected signal and control channel to determine whether the redundant connection is established correctly. Set the direction of the data channel address and data buffer, and the memory control signal buffer to the standby.

On the other hand, the standby determines whether the redundant connection is properly performed by looking at the other active / relative connection signal transmitted from the other party through its active / connection signal and control channel, and if the duplex connection is properly performed, the address, data buffer, The direction of the memory control signal buffer is then set to come in active. The local buffer must be blocked so that the central processing unit (CPU) on the standby side cannot access the redundant memory area.

In this state, when the active updates data in the memory, the same data as the active is updated in the standby memory through the data channel.

While the invention is susceptible to various modifications and alternative forms, the disclosure thereof has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

In the present application operating as described above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

By separating the local memory area and the parallel recording area separately as in the redundant structure of the parallel recording method, there is no need to write the same data twice in the local memory area and the parallel recording area. In addition, once the direction of the buffer of the data channel and the control channel is set, the state is maintained until duplication switching occurs, so that the control of the buffer is much easier than the duplication structure of the parallel recording method.

In addition, as in the parallel recording duplex structure, the active bus cycle does not end when the acknowledgment (Ack) signal indicating that the parallel recording is completed from the air is not used. .

Claims (6)

Two processor boards and memory for redundancy; A serial communication channel for active / standby negotiation and serial communication between the two processors; A control channel for conveying control signals associated with redundancy; And Redundancy unit for processors using two shared memories, including data channels for carrying redundant data and addresses. The method of claim 1, wherein the serial communication channel, Redundancy of a processor using two shared memories, consisting of a controller for active / standby negotiation and serial communication between two redundant processors and a unidirectional buffer for transmit / receive signals. The method of claim 1, wherein the control channel, Redundancy of a processor using two shared memories, consisting of an associated signal and a unidirectional buffer, as a path for conveying alarm signals of each board and control signals related to active / standby redundancy. The method of claim 1, wherein the data channel, Redundancy of a processor using two shared memories, consisting of control signals required for memory access, an address and data bus, and a bidirectional buffer for passing them to the other side. In a device consisting of two processor boards and memory for redundancy, a serial communication channel, a control channel and a data channel, Two redundant processors are configured to determine activation / standby over a serial communication channel; When the activation / standby is determined, an activation signal and a connection signal are transferred through the control channel to the active state to the atmosphere and the atmosphere to the active state; The active signal and the connection signal is a process of determining the duplex connection by looking at the other side active signal and the other side connection signal received from the other party through the control channel; If the duplex connection is properly established, setting the direction of the data channel address and the data buffer, and the memory control signal buffer to direct the active to the standby and the standby to enter the active; And And if the activation updates data in a memory, updating the standby memory with data identical to the activation through a data channel. 6. The method of claim 5, wherein, when the duplex connection is properly established, the direction of the data channel address, the data buffer, and the memory control signal buffer are set to move outward toward the standby, and the standby is set out of active. , And a local side buffer to prevent the central processing unit on the standby side from accessing the duplicated memory area.