JPS6111874A - Data transfer system between computers - Google Patents

Abstract

PURPOSE:To simplify communication control procedure by extending the address space of a bus of a microprocessor built in a channel device up to the inside of the opposite channel device to which data are to be transferred. CONSTITUTION:After checking that an extended bus 35 is not used for data transfer, a bus controller 31 controls a bus master switching circuit 32 to couple a microprocessor bus 23 with the extended bus 35 and open the extended bus 35 to a microprocessor 21. Then, the microprocessor 21 sends a transfer control signal in a program mode to a channel device 14 through the extended bus 35. Receiving a transfer control signal in a program mode from the microprocessor 21 through the extended bus 35, a bus slave switching control circuit 33 sends a control signal to a bus slave switching circuit 34 to control the coupling of the extended bus 35 with an extended bus 36 in a sub-channel device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer system between computers for performing data transfer processing such as data communication and data transfer between computers, and in particular, to a system for data transfer between computers. Concerning a simple data transfer system.

[Conventional technology]

In a conventional data transfer system between computers, opposing channel devices that act as interfaces for each computer system each have a built-in microprocessor and have the same configuration.
Data communication is generally performed according to a defined communication protocol.

FIG. 2 is a block diagram showing the configuration of such a conventional data transfer system between computers.

In FIG. 2, 1 represents one computer system (hereinafter referred to as
This system will be referred to as A system) central processing unit (C
P U), 2 is the memory of this A system, 3
is the common bus of this A system. Further, 4 is a central processing unit of another computer system (hereinafter, this system will be referred to as B system), 5 is a memory of this B system, and 6 is a common bus of this B system.

Further, 11 and 12 are channel devices that serve as interfaces for the A system and the B system, respectively, which constitute a data transfer system between computers.

Here, the internal configurations of channel devices 11.12 are the same, and 21.41 is a microprocessor (
μP), 22.42 is a channel control register, 23.
43 is a microprocessor bus, and 24.44 is a memory for the microprocessor. Also, 25.45 is
DMA control circuit.

26.46 is a DMA circuit, 27.37 is a line control circuit, and 28.4'8 is a line interface circuit. 60 is a communication line between both channel devices 11.12.

For example, when data is to be transferred from system A to system B via a communication device having such a configuration, data transmission is performed according to the following procedure.

First, the memory address of memory 2 where the data to be transferred is stored, the number of bytes to transfer, the command requesting transfer to the B system, and other necessary information are set in the channel control register 22. The interrupt is notified to the microprocessor 21, and the microprocessor 21 controls the line control circuit 27 to perform predetermined processing as a line link establishment process for communication with the microprocessor 41 of the channel device 12 of the B system.

Here, the line control circuit 27 is connected to the opposing line control circuit 4.
7 to establish a link, data is transferred between microprocessor 21 and microprocessor 41 according to a defined communication protocol.

Now, the microprocessor 41, which has received the data transfer request from the microprocessor 21, raises an interrupt to the CPU 4 to notify that there is a data transfer request from the A system.

Upon receiving this notification, the CPU 4 sets information in the channel control register 42, including the memory address of the memory 5 to receive the data, a command for permitting data transfer, and, if necessary, the number of bytes to be transferred.

Upon recognizing this setting, the microprocessor 41 powers up the DMA control circuit 45 based on this information, activates it, and then notifies the microprocessor 21 via the line 60 that preparations for data transfer are complete.
to notify.

The microprocessor 21 releases the line link for inter-microprocessor communication and requests the line control circuit 27 to control the line for DMA transfer between the channel devices 11 and 12. register 22
Based on the information set in , the DMA control circuit 25 is set up and DMA transfer processing is started.

As a result, the data sequentially outputted from the memory 2 via the DMA circuit 26 is transferred according to the communication protocol defined by the line control circuit 27.
The data is stored in the memory 5 via the .

In this way, data transfer is performed between the A system and the B system.

In the above explanation, A system, B system, and CP
In the case of synchronizing data transfer between U0,
If the cput of the A system sets data in the channel control register 22 along with other information, including the transfer data storage memory address of the other system, the channel device 12 of the B system can perform direct transfer without interaction with the CPU 4. It is also possible to store data in a designated area of memory 5.

[Problem that the invention seeks to solve]

Such conventional data transfer systems between computers have the following problems.

■Prior to data transfer between the A system and the B system, it is necessary to communicate between the microprocessors of both channel devices. Moreover, the communication is performed via a line that requires complicated communication control procedures. For these reasons, the overhead for data transfer becomes large, and the throughput of computing engine communication becomes low.

The hardware and software for 0-line control become complicated.

[Purpose of the invention]

The present invention was made in view of the problems of the prior art, and in addition to solving the problems of the prior art, the device has a simple configuration, low overhead, and high efficiency. The purpose of this invention is to provide a data transfer system between computers that allows for good communication between computers.

[Means for solving problems]

The means of the present invention for solving the above problems and achieving the above object is to provide a channel device equipped with a microprocessor as a channel device of one of the computer systems in a data transfer system between computers. When the address space of the bus in this microprocessor is expanded to include the channel device of the other party of data transfer, and data is transferred between computers, the channel control information storage unit and DMA of each channel device are expanded.
A transfer control section is coupled to the bus, and the bus is used as a DMA transfer bus between channel devices.

[Effect]

With the above configuration, the opposing channel devices are tightly coupled, and the microprocessor
Slaves such as memories and registers in both channel devices can be accessed equally, making it possible to collectively manage these channel devices.

As a result, the communication control procedure in the data transfer system between computers has become extremely simple, with little overhead (
, which can perform data transfer with high throughput.

Moreover, since only one microprocessor is required and both channel devices can be implemented with simple hardware, the overall system is simple.

Furthermore, the microprocessor can easily be used for processing other than data communication, such as sensing and controlling the state of a partner system, and can realize a wide variety of processing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an inter-computer data transfer system according to an embodiment of the present invention.

Components that are the same as those in FIG. 2 are designated by the same reference numerals.

The data transfer system between computers shown in the figure has a main channel device &13 in its own computer system, and a sub-channel device 14 in the computer system serving as its communication partner. The channel devices 14 are connected by an inter-channel device expansion bus 35.

Here, the main channel device 13 includes a bus extension side i-circuit 3.
0, bus controller 31, bus mask switching circuit 32
The sub channel device 14 is provided with a bus slave switching control circuit 33 and a bus slave switching circuit 34.
, and a sub-channel device internal expansion bus 36 are provided, respectively. The microprocessor bus 23 is connected to the inter-channel device expansion bus 3 via the bus mask switching circuit 32.
5. Connected to the sub-channel device internal expansion bus 36 to expand the range of this bus.

As a result, the channel control registers 42 of the 14 examples of sub-channel devices and the DMA t! Control registers and the like included in the J control circuit 45 can be mapped onto the address space of the microprocessor bus 23. therefore,
From the perspective of the microprocessor 21, these are slaves.

Now, when the microprocessor 21 attempts to access the control register 42 of the sub-channel device 14, the bus expansion control unit 30 determines the address and requests the bus controller 31 to use the expansion bus 35.

After confirming that the expansion bus 35 is not being used for DMA transfer, the bus controller 31 controls the bus mask switching circuit 32 and controls the microprocessor bus 23.
and the expansion bus 35, the microprocessor 2
1, the expansion bus 35 is opened.

Next, the microprocessor 21 transfers the program mode transfer control signal to the channel device 14 via the expansion bus 35.
Send to. When the bus slave switching control circuit 33 receives the program mode transfer control signal from the microprocessor 21 from the expansion bus 35, it sends a control signal to the bus slave switching circuit 34, and transfers the control signal to the expansion bus 35 and the sub-channel device internal expansion bus. 36.

In this way, the microprocessor 21 accesses the channel control register 42 and DM"ltd1m on the side of the secondary channel device 14 in the normal program mode, just as it accesses the memory or registers (circuits that become slaves) in the main channel device. Circuit 45 can be accessed.

In addition, when accessing via the expansion bus connected in this way, data transfer control is performed between the microprocessor 21 and the slave in a handshake mode.

Here, the microprocessor 21 controls the DMA control circuit 25.
and DMA control circuit 45 to activate the main channel device 13. A state is established in which data can be transferred by DMA with the sub-channel device 14.

That is, this is the DMA circuit 26 or the DMA circuit 46.
When data to be transferred to the other channel device side is set in the data buffer register in one of the circuits, and in this state, this fact is sent to the DMA control circuit 25 or the MA control circuit 45. When notified, DMA
The control circuit 25 or the DMA control circuit 45 requests the bus controller 31 to use the expansion bus 35.

After confirming that the microprocessor 21 is not using the expansion bus 35 or making a request to use it, the bus controller 31 releases the expansion bus 35 for DMA transfer, and uses the bus mask switching circuit 32 to open the expansion bus 35 for DMA transfer. DM via
A route between A circuit 26 and expansion nomas 35 is established. In addition, the slave switching control circuit 33 is connected to the expansion bus 3.
When the DMA transfer control signal from 5 is received, it acts on the path/slave switching circuit 34 and transfers the expansion bus 35 and DMA circuit 46.
Establish a route between.

Here, the D between the DMA circuit 26 and the DMA circuit 46 is
MA transfer can be easily realized by using the data lines of the expansion bus 35, some control signal lines, and some control signal lines dedicated to DMA transfer.

By the way, since various DMA transfer methods are already known, a detailed explanation thereof will be omitted here.

Now, in this embodiment, when the hash controller 31 receives a request to use the expansion bus 35 from the microprocessor 21 while the expansion bus 35 is being used for DMA transfer, it temporarily interrupts the DMA transfer. Assume that bus priority control is performed so that the microprocessor node 21 uses the extended nozzle. Even during DMA transfer between the main and sub channel devices, the microprocessor 21 can access slaves such as the channel control register 42 on the expansion bus 36 in the sub channel device, making this process easy. Become.

Next, the overall operation when data is communicated from system A to system B using such a data transfer system between computers will be described.

When the CPUI sets a command for requesting communication between computers and information necessary for data transfer in the channel control register 22, the microprocessor 21 is notified by an interrupt.

The microprocessor 21, which has recognized the request for computer communication processing, executes the sub-channel device 14 in the normal program mode.
access the side and via the channel control register 42,
B system's CP tJ 4 & raise 1 included immediately,
System A requests data transfer (notifies that there is).

Upon receiving this, the CPU 4 sets a command to respond to the data transfer request and information necessary for other transfers in the channel control register 42, and then sends the command to the microcontroller via the interrupt request line provided in the expansion bus 35. An interrupt is generated in the processor 21, and the microprocessor 21 reads the transfer command information set in the channel control register 42.

Next, the microprocessor 21 sets up the DMA siI control circuit 25 according to the transfer command information from the CPU, and further sets up the DMA control circuit 45 according to the transfer command information from the CPU 4.
Start DMA transfer.

As a result, under the control of the DMA control circuit 25, the DMA
Each time the circuit 26 reads data from the memory 2 and captures the read data into the input data buffer register of the DMA circuit 26, the DMA control circuit 25 requests the path controller 31 to use the expansion bus 35. , if it is permitted, DMs added in addition to the data lines of the expansion bus 35, the microprocessor bus phase, etc.
The A transfer control line is used to control data transfer between the DMA transfer control units of both channel devices.

The DMA circuit 46 takes in the data sent from the main channel device 13 side into its output data buffer register, and stores this data in the memory 5 under the control of the DMA control circuit 45.

In the above embodiment, DM between the main and sub channel devices
Regarding the A transfer control, there is no difference from that of the prior art except that the data transfer path is not a line but an expansion bus of the microprocessor bus.

In this way, the CPU 4 of the B system can access the memory 5 of its own system and receive the transferred data.

The above is a case in which data is transmitted from system A to system B. Next, a case in which a large amount of data is transmitted from system B to system A will be explained. Since access to the channel control register 42 and DMA control path circuit 45 in the channel device 13 can be performed in the same way as when accessing the channel control register 22 and DMA control circuit 25 in the own channel device 13, similar processing is performed for the data communication procedure. It can be executed with

That is, when the CPU 4 controls the channel and sets a command for requesting communication between computers and information necessary for data transfer in the instantaneous processor 42, the microprocessor 21 is notified by an interrupt via the expansion bus 35.

The microprocessor 21, which has recognized the request for computing institution communication processing, notifies the CPUI that there is a data transfer request from the B system.

Upon receiving this, the CPU 1 sets a command in response to the data transfer request and other information necessary for the transfer in the channel control register 22. At this point, an interrupt is generated in the microprocessor 21, and the microprocessor 21 reads out the transfer command information set in the channel control register 22.

Thereafter, predetermined data is transferred from the B system to the A system by the same process as described above.

In addition, data transfer from system B to system A is as follows:
Instead of such an interrupt process to the microprocessor 21, the microprocessor 21 may periodically poll the channel control register 42 to determine whether or not there is a request.

Therefore, under the initiative of the CPUI of the A system,
Similar processing can be used when the system receives communication data from the B system.

Furthermore, if the CPU of either system directly transfers data to or from the memory of the other system without notifying the other system's CPU (without synchronizing with the other system's CPU), If the command to that effect and the memory address of the partner system are included as transfer command information in the channel control register of the channel device, the main and sub channel devices 13 and 14 can execute the process without any problem.

Here, the channel control register is not limited to a register, but may be anything that can store control information such as commands for data transfer. Therefore, a portion of memory, etc. may be used, and this
It may also be a storage device.

In addition, in the embodiment, data transfer between two systems, A system and B system, is explained as an example.
Data can be transferred to other computers using a similar system, and it goes without saying that such a system can be applied between multiple computers.

〔Effect of the invention〕

As described above, in the present invention, a channel device equipped with a microprocessor is provided as a channel device of one of the computer systems to be used as an interface for each computer system, and the bus in this microprocessor is When extending the address space to the other party's channel device and performing data transfer between computers, the channel control information storage unit and DMA transfer control unit of each channel device are coupled to the bus, and the bus is connected to the channel device. Since it is used as a DMA transfer bus between the two channel devices, the opposing channel devices are tightly coupled, and the microprocessor can access the slaves in both channel devices equally and manage these channel devices collectively. becomes possible.

As a result, the communication control procedure in the data transfer system between computers has become extremely simple, with little overhead (
, and can perform data transfer with high throughput.

Moreover, since only one microprocessor is required and both channel devices can be implemented with simple hardware, the overall system is simple.

Furthermore, the microprocessor can easily perform processing other than data communication, such as sensing and controlling the state of a partner system, and can realize a wide variety of processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an inter-computer data transfer system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional inter-computer data transfer system. 1.4- Central Processing Unit (CPU). 2.5, 24.44 - Memory. 3.6--Common bus, 11.12--Channel device, 13--Main channel device. 14...-Subchannel device. 21.23--Microprocessor. 22.42...-Channel control register. 25', 45 ・-DMA control i circuit. 26.46"--DMA circuit, 27--line control circuit, 28--line interface. 30--bus expansion fldl control circuit, 31---
Bus controller, 32--bus mask switching circuit. 33 --- Bus slave switching circuit. 34-- Bus slave switching circuit. 35-11-Channel Interdevice Expansion Bus. 36--Subchannel device internal expansion bus.

Claims (2)

[Claims] (1) In a data transfer system between computers, a channel device equipped with a microprocessor is provided as a channel device of one of the computer systems, and the address space of the bus in this microprocessor extends into the channel device of the other party for data transfer. When expanding and transferring data between computers, the channel control information storage section and DMA transfer control section of each channel device are coupled to the bus, and the bus is used as a DMA transfer bus between the channel devices. A data transfer system between computers featuring the following. (2) The channel device with a built-in microprocessor is the main channel device, and the other channel device is the secondary channel device. These channel devices are collectively managed by this microprocessor, and when data is transferred between computers, the bus is 2. The computer-to-computer data transfer system according to claim 1, wherein the data transfer system between computers is used in a time-sharing manner as a DMA transfer bus between a main channel device and a sub-channel device.