KR100328626B1 - Method for preventing dead lock of bus direction multiprocessing system - Google Patents

Abstract

PURPOSE: A method for preventing a dead lock of a bus direction multiprocessing system is provided to prevent a fatal error caused by a bus access retrial between processors by repeatedly reading a flag through processors, performing a locking operation if the flag is cleared, clearing the flag after completing a related operation in a corresponding processor in a locking process. CONSTITUTION: A processor judges whether a cache miss is generated at a reading period(ST100). If a cache miss is generated, a system bus using right is requested for accessing to a main memory. If an arbitration is successful(ST103), an address is operated on a bus(ST104) and it is judged whether a memory response with respect to the operated address exists(ST105). If the memory response exists, data are waited(ST106). If data are reached(ST107), a related cache status is updated or a shared related data is progressed(ST108). The cycle is completed(ST109), an address of other block is observed, an address bus is checked, and a reading flag/SHD flag is cleared(ST110). A bus period snoops continuously and it is judges whether a reading flag is set or not(ST111). If the reading flag is set and a bus access to other processor is reading period(ST112, ST113), a shared operation SHD flag is set and operated on a bus instead of a snack operation(ST114).

Description

How to Prevent Deadlock in Bus-Directed Multiprocessing Systems

The present invention relates to the prevention of deadlock by cache memory in a multiple processing system in which multiple processors share a bus. More specifically, the present invention relates to retrying bus access between processors in order to maintain cache identity. Of course, the present invention relates to a deadlock prevention method of a bus direction multiprocessing system to solve a problem in which a large number of processors may cause a dead lock and cause a fatal error in the system.

In general, a multiprocessing system bus having a shared memory structure in which a plurality of processor boards and memory boards are connected to a system bus is a synchronization bus that operates in synchronization with a clock and has a pending protocol.

In the pending protocol, the request and response periods are separated on the bus, and each of them can be generated in succession.

In other words, requesting data from one processor memory and responding from the memory are separate, while another processor can continue to perform the same operation continuously from the very next cycle in which the first processor drives an address on the bus. Is the pending protocol.

Multiprocessor architectures that share a bus have cache memory, which is very significant.

The cache memory is a small high-speed memory located between the processor and the main memory, and plays an important role in improving processor access time and reducing traffic on the bus.

In terms of hardware implementation, however, it is very difficult because the cache memory is fast and maintains its coherency.

Because each processor has its own cache memory and always accesses it, keeping each cache memory the same for the same address is very important, otherwise it is a fatal error of the system.

FIG. 1 is a signal flow diagram for the deadlock prevention of the conventional bus direction multiprocessing system. As shown in FIG. 1, it is determined whether the processor reads a cache read miss during a read cycle (step ST1). The cache is accessed (step ST2) and the desired data is lost (step ST3).

If it is determined in step 5T1 that the cache read miss is requested, the system bus license is requested to access the main memory, and if it succeeds in arbitration (step ST4), the address is driven on the bus ( Step ST5) It is determined whether there is a response of the memory to the driven address (step ST6).

As a result of the determination, if there is a memory response, it waits for data (step; ST7), and when data arrives (step; ST8), the relevant cache state is updated internally and the related data processing is performed (step; ST9).

Then, the cycle is completed (step ST10) and the address observation on the other bus and the address bus are checked (step ST11).

At this time, after the processor first drives an address on the bus, the processor continuously observes the address on the bus from the next bus cycle (step ST12). The address driven by the processor and the address driven by the other processor on the bus coincide. The lower surface (step; ST13) As in FIG. 2, a Snack (Snoop ack) is driven on the bus (step; ST14).

The other processor running the same address then knows that the current bus cycle was meaningless and attempts to repeat the cycle again, as in the second diagram.

Running Snack this way prevents other processors from accessing the main memory at the same address for their desired time is necessary to maintain cache identity.

At this time, one processor needs a long time of at least 10 clocks based on a bus clock to start a system bus cycle and perform internal processing.

However, the deadlock prevention method of the conventional bus-oriented multiprocessing system requires that multiple processors perform their respective processes in the operating system of the multiprocessor system, but in some cases, the operations of each processor must be synchronized. ) Function.

The lock function assimilates operations by multiple processors writing and clearing flags at one address.

At this time, multiple processors access one address at the same time. As described above, a processor runs a snack for a long time until the processor accesses the bus and finishes the internal processing. When a processor accesses an address in successive bus cycles and also mixes reads and writes, each other drives a snack to repeatedly useless bus accesses, resulting in performance degradation and infinite repetition cycles if more processors are used. There was a problem that could lead to a fatal situation in the system.

Accordingly, an object of the present invention is to read the flag repeatedly through the processor during the lock operation in view of the conventional problem, and if the flag is clear, perform the lock operation and the processor clears the flag after completing the related operation The present invention provides a method for preventing deadlock in a bus direction multiprocessing system that prevents a fatal error due to a retry between buses between processors.

The deadlock prevention method of the bus direction multi-processing system of the present invention for achieving the above object is a case where the processor has a cache miss inside the board and reads it by determining whether its bus period is read or write on the system bus. Setting a read flag indicating that a read-related bus cycle has been started; After driving an address on the bus and snooping the bus state until data arrives in memory, it sets the SHD flag and drives the shard on the bus when the pipeline match and the bus access of another processor is read. In the case of writing, driving the snack and updating the cache state of the cache to the shard after the data arrives if the shard is driven at least once; After the data arrives from the main memory until the end of the internal processing, if the pipeline matches the snack is characterized in that it consists of a step of repetition.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

3 is a signal flow diagram for deadlock prevention of the inventive bus-direction multiprocessing system, as shown therein, determining whether the read of the cas memory is missed (ST100); Accessing the cache to read the desired data and ending the cycle if it is not the cache read miss (ST101, ST102); Requesting a system bus license if it is the cas read miss and determining whether the mediation is successful (ST103); If the system bus arbitration is successful, driving an address bus and determining whether there is an address response (ST104, ST105); Waiting for data if there is an address response, and internally updating a relevant number of caches or processing shard (Shared) related data internally and completing a cycle (ST106-ST109); Clearing the read flag and the SHD flag by checking and checking the disabled address from the next period after the cycle is completed (ST110); Retrieving whether a read flag is set in a casable read period after the successful system bus arbitration (ST111); Driving address observation on the bus and shards or snacks if the read flag is set (ST112); Determining whether there is an address match and another master read cycle after driving the shard or snack (ST113); Driving a shard to set an SHD flag if there is a read cycle from the address match or another master (ST114); If it is determined in the step ST111 that the read flag is not set, determining whether or not the address observation on the bus and the address bus coincide (ST115, ST116); Driving a snack-on bus when the result of the determination is identical or there is no other master read cycle as a result of the determination in step ST113 (ST117); Judging whether or not a read flag is set based on the data received in step ST107; Observing the disabled address observation and the shard or snack drive and enable address if the read flag setting is set, and determining whether the addresses match (ST119, ST120); If the address matches, the step of driving Snack on Bus (ST121) is performed.

Thus, the working effect of the present invention made in detail with reference to FIGS. 3 and 4 as follows.

First, it is determined whether or not the cache read miss occurs when the processor is in a read cycle (step ST100), and if the cache hit (Hit) is its own, the cache is accessed (step ST101), and the desired data is read (step ST102).

If it is determined in step ST100 and the cache read miss, the system bus is requested to access the main memory, and if it succeeds in arbitration (step ST103), the address is driven on the bus. (Step ST104) It is determined whether there is a response of the memory to the driven address (step ST105).

As a result of the determination, if there is a memory response, data is waited (step ST106), and when data arrives (step ST107), the cache status is updated internally or the shard-related data processing is performed (step ST108).

Then, the cycle is completed (step ST109) and the address observation on another bus and the address bus check and read flag / SHD flag are cleared (step ST110).

At this point, the processor sets the read flag that it has started a read-related bus cycle since the first drive on the bus.

Subsequently, when the bus cycle is continuously sniffed and it is determined whether the read flag is set at the cache read cycle (step 111), the read cycle is set and the bus access of another processor is the read cycle. (Step; ST112, ST113) Instead of driving a snack on the bus, it is driven by setting the shard drive SHD flag (step; ST114).

If the read flag is not set during the cacheable read cycle period in step ST111, the address on the bus is snooped and the address bus is checked (step ST115) to determine whether the addresses match (step ST115). ; ST116).

As a result of the determination, if the address buses match, Snack on bus is driven (step ST117).

When the SHD signal is driven on the bus in step ST114, the processor that attempted to access the read-related bus does not repeat, but after performing a normal read, updates its cache state to S and the main memory is also on the bus. If the snack is driven, but did not respond, but when the SHD is driven, as in the fourth degree, the normal response.

At this time, of course, when sniffing the bus operation after the read flag is set, when the bus access of another processor is other than the read period, the snack is driven and repetitive.

After the data arrives in step ST107, if a pipeline match is generated regardless of the type of bus access (read / write) during bus snooping, a snack is generated and repeated, and the internal processing is performed. Invalidate (disable) the generation generating circuit (step ST110).

If the SHD flag is set during internal processing (step ST118), it is not updating the cache state of itself with V at the time of updating, and the read flag and the SHD flag are released (step ST110).

In practice, for operating systems or hardware test programs, all processors access concurrently to one address in the flag test operation of the lock operation (if the flag is set, iteration cycles, and the actual hardware operation reads from one address in the shared area). Because of this, the design and implementation can have a great effect as in the present invention.

In the present invention, the update to the cache (Valid-exclusive) in the cache identity maintenance-related cache state indicates that valid data exists only in the main memory and one cache, and is a processor read period, a cache miss, and a main memory. When getting data, the status is updated to V.

In addition, the update to S (Shared) indicates a state in which valid data is shared by the main memory and two or more caches, and when the processor reads and caches the data from the main memory, the existing V state or S There is a cache in the state, which drives the shard signal on the bus to update the cache state of the processor and its own cache to S.

D (Dirty) indicates the state that valid data exists in only one cache. When a write occurs, the cache with dirty state is sniffing the bus state because the cache response method is a write-back method. Only in the case of a pipeline match, the processors are iterated again and the data is written back to main memory.

I (Invalid) indicates that the cache contents are invalid.

As described in detail above, according to the present invention, the flag is repeatedly read through the processors during the lock operation, and if the flag is cleared, the lock operation is performed and the processor clears the flag after completing the related operation. A fatal error caused by retrying a bus access between them is prevented.

1 is a signal flow diagram for deadlock prevention in a conventional bus direction multiprocessing system.

2 is a table diagram of a bus state sampling state according to FIG.

3 is a signal flow diagram for deadlock prevention in a bus-oriented multiprocessing system of the present invention.

4 is a table of bus state sampling states according to FIG.

***** Explanation of symbols for main parts of drawing *****

S: Shard V: Valleyd Exclusive

D: Dirty I: Envelop

Claims (1)

Setting a read flag indicating that the processor has started a read-related bus cycle when the processor detects a cache miss in the board and determines whether the bus cycle is a read or write on the system bus; After driving an address on the bus, it snoops the bus state until data arrives in memory, sets an SHD flag and drives a shard on the bus when the pipeline matches and another processor's bus access is read. In the case of writing, driving the snack and updating the cache state of the cache to the shard after the data arrives if the shard is driven at least once; After the data arrives from the main memory until the end of the internal processing, if the pipeline matches the method to prevent the deadlock of the bus direction multi-processing system characterized in that the step of driving the snacks and repeating.