JP2522571B2 - Electronic equipment data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an MPU (microprocessor unit).
The present invention relates to a data transfer device for an electronic device, which is controlled by, and includes a DMAC (Direct Memory Access Controller).

[Prior Art] Conventionally, as electronic devices such as laser printers and word processors, those configured as shown in FIG. 6 are known. This consists of a program ROM (Read Only Memory) 3, RAM (Random Access Memory) 4, DMAC on the MPU1 as the main body of the control unit via the bus line 2.
5. Connect output port 6 and so on. Then, the MPU 1 performs data processing according to the program set in the program ROM 3 and writes the required data in the line buffer of the RAM 4 or the like. On the other hand, when the data request signal REQ is received from the peripheral circuit 7 such as the printer or the display unit, the DMAC 5 causes the RA
The M4 is accessed to transfer the required data written in the line buffer or the like to the output port 6. It also generates a port clock signal PC and sends the required data on the output port 6 to the peripheral circuit 7. By configuring in this way MP
The burden on U1 is reduced and high-speed processing is possible.

However, in this case, in order for the DMAC 5 to transfer the required data on the RAM 4 to the output port 6, it was necessary to transfer the right to use the bus line 2 from the MPU 1 to the DMAC 5 side.

[Problems to be Solved by the Invention] As described above, the MPU1 is conventionally used during data transfer by the DMAC5.
Couldn't use bus line 2. Therefore, when a large amount of data is transferred by the DMAC 5, there is a problem that the bus usage efficiency of the MPU 1 is reduced and the processing speed is reduced.

Therefore, the present invention intends to provide a data transfer device for an electronic device, which can secure a high bus usage efficiency of the MPU even when a large amount of data is transferred by the DMAC and prevent a decrease in processing speed.

[Means for Solving the Problems] The present invention provides an MPU that performs data processing according to a program read from a program ROM via a bus line and writes required data to a memory via a bus line, and an MPU that responds to a data request from the outside. In an electronic device including a DMAC that transfers data written in the temporary storage unit to the output port, the temporary storage unit is connected to the output port without a bus line, and the DMAC reads the temporary storage unit. An address generation unit that generates an address, a signal detection unit that detects a read signal from the MPU or a write signal other than a write signal to the temporary storage unit, a determination unit that determines whether there is a data request from the outside, and this determination unit If a signal is detected by the detecting means in the state where it is determined that there is a data request, the address generating means is generated from the temporary storage section. Data of the generated address is obtained and a data transfer control means for transferring read Te to the output port.

The temporary storage unit is preferably arranged in the same address area as the program ROM.

[Operation] By taking such a measure, when a data request is generated from the outside, the required data written in the temporary storage unit becomes a read signal from the MPU or a write signal other than the write signal to the temporary storage unit. In response, the data is transferred from the temporary storage unit to the output port without passing through the bus line.
Therefore, the DMAC can transfer the data in the temporary storage unit to the output port without using the bus line. However, MPU
Since data transfer cannot be performed while the required data is being written to the temporary storage unit, the MPU can write the data stably.

Also, since the program ROM is a read-only memory for the MPU, and the temporary storage section is a write-only memory, the temporary storage section can be placed in the same address area as the program ROM, thus making the address space effective. Used to save memory space.

[Embodiment] An embodiment in which the present invention is applied to a printer as an electronic device will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration. A program ROM 13, a work RAM 14, a DMAC 15 and a buffer RAM 16 as a temporary storage unit are connected to an MPU 11 as a control unit main body via a bus line 12. Buffer RAM above
Output port 17 is directly connected to 16. This output port
A peripheral circuit 18 relating to the printer is connected to 17.

The program ROM 13 stores program data for the MPU 11 to perform data processing. The work RAM 14 is formed with various memory areas used by the MPU 11 for data processing. The print data obtained by the data processing of the MPU 11 is written in the buffer RAM 16. And the second
As shown in the figure, the program ROM 13 and the buffer R
The same addresses a1 to ai are assigned to the AM16, and different addresses aj to an are assigned to the work RAM 14.

Therefore, the memory access control circuit shown in FIG. 3 is incorporated in the MPU 11. That is, the first address determination unit 21 determines that the memory address to be accessed is a1 to
Output when within ai range (chip select signal) ▲ ▼
Is set to the low level "L", and the second address determination unit 22 outputs (chip select signal for the work RAM 14) ▲ ▼ to the low level "L" when the address of the memory to be accessed is within the range of aj to an. "It is. On the other hand, the read signal output unit 23 sets the output (read signal) ▲ ▼ to the low level “L” when reading data from the memory, and the write signal output unit 24 outputs the data to the memory. The output (write signal) ▲ ▼ is set to the low level “L” when writing is performed. Then, the logical product of the output ▲ ▼ from the first address determination section 21 and the output ▲ ▼ from the read signal output section 23 is first calculated.
The gate circuit 25 of the
Is output as a chip select signal ▲ ▼ for the above, and the logical product of the output ▲ ▼ and the output ▲ ▼ from the write signal output unit 24 is calculated by the second gate circuit 26,
The output is output as a chip select signal ▲ ▼ for the buffer RAM 16.

FIG. 4 is a diagram showing a circuit configuration of the DMAC 15. this
A read signal ▲ ▼, a write signal ▲ ▼, and a chip select signal ▲ ▼ for the buffer RAM 16 are input to the DMAC 15 from the MPU 11, and a print data request signal ▲ ▼ is input from the peripheral circuit 18. Then, the logical sum of the read signal ▲ ▼ and the write signal ▲ ▼
Of the first gate circuit 31 and the logical product of the output of the first gate circuit 31 and the chip select signal ▲ ▼ are calculated by the second gate circuit 32, and the output of the second gate circuit 32 and the The logical product of the print data request signal ▲ ▼ is calculated by the third gate circuit 33 to obtain the third gate circuit.
The output of 33 is applied to the signal processing unit 34. The signal processing unit 34 outputs the signal S1 for instructing the address generation unit 35 to generate an address in response to the output of the third gate circuit 33 becoming the low level "L", and Read signal to buffer RAM16 ▲
Output ▼. Also, output port 17
To the port clock signal ▲ ▼. That is, the first gate circuit 31 and the second gate circuit 32 compose signal detecting means, and the third gate circuit composes data request presence / absence determining means. The signal processing unit 34 also functions as a data transfer control means. The address generator 35 is composed of, for example, a counter, and "1" to "i" are input according to the input of the signal S1.
Buffer RA by counting up in the range
Generate an address for M35 and add its address ADD
(A1 to ai) is output to the RAM 35.

In the present embodiment configured as described above, the MPU 11 appropriately sets the output ▲ ▼ of the first address determination unit 21 to the low level "L" and outputs the output ▲ of the read signal output unit 23.
The program ROM 13 is accessed by setting ▼ to a low level "L", the programs set in the addresses a1 to ai are sequentially read, and data processing is performed according to the read program. At this time, when data is written to the work RAM 14, the MPU 11 sets the output ▲ ▼ of the second address determination unit 22 to the low level "L" and the output ▲ ▼ of the write signal output unit 24. Is set to low level "L" to access the work RAM14, and the addresses aj to an
Data is written in the memory area formed inside. When data is read from the work RAM 14, the MPU 11 outputs the second address determination unit 22
▼ is set to low level “L”, and the output ▲ ▼ of the read signal output unit 23 is set to low level “L”, and the work RAM 1
4 is accessed to read data from the memory area formed in the addresses aj to an.

In this way, if data processing is performed in the MPU11 and the required print data is obtained, this print data is buffered.
Written to RAM16. That is, the MPU 11 sets the output ▲ ▼ of the first address determination section 21 to the low level “L” and sets the output ▲ ▼ of the write signal output section 24 to the low level “L”. As a result, the chip select signal ▲ ▼ for the buffer RAM 16 becomes the low level “L”, the buffer RAM 16 is accessed, and the print data is written in the line buffer formed in the addresses a1 to ai.

On the other hand, in the DMAC15, the MPU11 is a program ROM.
When either the work RAM 14 or the buffer RAM 16 is accessed and the read signal RE or the write signal ▲ ▼ becomes low level "L", the output of the first gate circuit 31 becomes low level "L". However, when the MPU 11 accesses the buffer RAM 16, the output of the second gate circuit 32 remains high level "H" because the chip select signal ▲ ▼ is low level "L". As a result, the peripheral circuit 18
Irrespective of the presence / absence of the print data request signal ▲ from the third gate circuit 33, the output of the third gate circuit 33 continues to be at the high level "H", and the buffer RAM read signal ▲ from the signal processing unit 34
Also at ▼, the high level “H” is continued (time point t in FIG. 5).
1). Therefore, data transfer from the buffer RAM 16 is not performed.

On the other hand, MPU11 is program ROM13 or work RA
Chip select signal when M14 is accessed ▲
Since ▼ remains low level “H”, the output of the second gate circuit 32 becomes low level “L”. Therefore, if the print data request signal ▲ ▼ is input from the peripheral circuit 18 at this time, the output of the third gate circuit 33 becomes low level "L", and the buffer RAM read signal ▲ ▼ from the signal processing unit 34 also. Low level "L" (time t3 in Fig. 5)
And t6). In addition, the address generator 35 causes the buffer RA
The M16 read address is generated. As a result, the print data for one line written in the address is transferred to the output port 17 in synchronization with the rising edge of the buffer RAM read signal (▼) (at time t4 and t4 in FIG. 5).
t7). After that, the print data transferred to the output port 17 is sent to the peripheral circuit 18 in synchronization with the port clock signal {circle over ()} output from the signal processing unit 34.

If the print data request signal ▲ ▼ is not input when the output of the second gate circuit 32 becomes low level “L”, the output of the third gate circuit 33 becomes high level “H”. There is a buffer RAM from the signal processing unit 34
The high level “H” of the read signal ▲ ▼ also continues (time points t2 and t5 in FIG. 5). Therefore, also in this case, data transfer from the buffer RAM 16 is not performed.

Thus, according to the present embodiment, the DMAC 15 outputs the print data in the buffer RAM 16 to the print data request from the peripheral circuit 18 without using the bus line 12.
Can be transferred to. Therefore, when transferring data, the bus line 12
DMA does not need to be transferred from MPU11 to DMAC15.
Even if a large amount of data is transferred by C5
The bus usage efficiency of MPU1 can be maintained high without affecting the bus usage efficiency of MPU1. Therefore, the problem that the processing speed is reduced is eliminated.

In addition, the timing of data transfer by DMAC15 is set to MPU1.
Since it is synchronized with the read signal ▲ ▼ from 1 or the write signal ▲ ▼ other than the write signal for the buffer RAM 16, the required data write operation to the buffer RAM 16 by the MPU 11 is stably performed. Therefore, the data processing efficiency of the MPU 11 is also improved. Moreover, the read signal ▲ ▼ from the MPU 11 is output every time the MPU 11 reads the program from the program ROM 13, and this program reading is performed frequently, so it is too late from the data request from the peripheral circuit 18. There is also an advantage that data can be transferred to the output port 17 without the need.

Further, according to the present embodiment, the program R for the MPU 11 is
Since the OM 13 is a read-only memory and the buffer RAM 16 is a write-only memory, the buffer RAM 16 can be arranged in the same address area as the program ROM 13. Therefore, effective use of the address space is achieved,
You can save memory space.

It goes without saying that the present invention is not applied only to a printer as an electronic device. For example, when applied to a data communication device as an electronic device, DM
The transmission data may be transferred as the required data transferred by the AC 15, and the screen data may be transferred when applied to the display device.

[Effects of the Invention] As described in detail above, according to the present invention, even if a large amount of data is transferred by the DMAC, the bus usage efficiency of the MPU can be kept high and the processing speed can be prevented from decreasing. A transfer device can be provided.

Further, according to the second aspect, it is possible to obtain an excellent effect that the address space of the memory can be effectively utilized.

[Brief description of drawings]

1 to 5 are diagrams showing an embodiment of the present invention, in which FIG. 1 is a block diagram showing the entire structure, FIG. 2 is a diagram showing a memory map, and FIG. 3 is a memory access in an MPU. Circuit diagram of control circuit, Fig. 4 is circuit diagram of DMAC, and Fig. 5 is
FIG. 6 is a timing diagram of main signals in the DMAC, and FIG. 6 is a diagram showing a configuration of a conventional example. 11 …… MPU (Micro Processor Unit), 12…
... bus line, 13 ... program ROM (read only memory), 14 ... work RAM (random access memory)
Memory), 15 ... DMAC (Direct Memory Access Controller), 16 ... Buffer RAM, 17 ... Output port, 18 ... Peripheral circuits.

Claims (2)

(57) [Claims] 1. An MPU (microprocessor unit) which processes data according to a program read from a program ROM (read only memory) via a bus line and writes required data to a temporary storage unit via the bus line. And transfer the data written in the temporary storage unit to the output port in response to a data request from the outside.
DMAC (Direct Memory Access Controller)
In the electronic device comprising, the temporary storage unit is connected to the output port without the bus line, the DMAC, an address generation unit that generates a read address for the temporary storage unit, and the MPU Signal detecting means for detecting a read signal from the device or a write signal other than the write signal for the temporary storage section, a judging means for judging whether or not there is a data request from the outside, and a state in which the data request is judged by this judging means. And a data transfer control means for reading the data of the address generated by the address generation means from the temporary storage unit and transferring the data to the output port when the detection means detects the signal. Data transfer device for electronic equipment. 2. The data transfer device for an electronic device according to claim 1, wherein the temporary storage unit is arranged in the same address area as the program ROM.