JP2677954B2 - Memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system for storing a two-dimensional digital video signal, and more particularly, it optimizes the size of the memory for storing the two-dimensional video signal using an address mapping technique. Memory system that can be implemented.

[0002]

A two-dimensional (hereinafter 2D) digital video signal includes a series of digital video "frames", each frame defined by a matrix of pixels.

Generally, in a video signal processing device, 2
The D digital video signal is processed in frame units. Therefore, a frame memory system is required to process the 2D video signal.

A conventional memory system for processing a 2D digital video signal has a frame memory of a specific size and an address generator. The frame memory has a plurality of storage locations, and the brightness levels of pixels are stored in the storage locations.

The address generator generates an address, and one address consists of a plurality of bits and is used to specify a storage location in the frame memory.

The position of each pixel stored in the frame memory can be indicated by a matrix number, and the address bit is composed of a horizontal address component X indicating a column position and a vertical address component Y indicating a row position. If the horizontal address component consists of M bits and the vertical address component consists of ^N bits, the entire memory addressed by the (M + N) bits has 2 ^M × 2 ^N storage locations.

Since the size of the memory is produced according to industry standards (ie the storage location is, for example, 2 ^{M + N}
Fixed to individual), does not always match the actual size of the video frame. Therefore, in the conventional memory system, the whole memory cannot be used. For example, when a frame signal composed of pixels of 1280 columns × 720 rows is stored in the frame memory, the frame memory has 11 bits of horizontal and 1 bits.
It will be addressed as a 0-bit vertical address component, ie will have a memory size of 2 ¹¹ × 2 ¹⁰ (2 ¹¹ ), which is much larger than the actual memory size needed for 1280 × 720. .

[0008]

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide an improved memory system that can optimize memory size with 2D video signal size using address mapping techniques. Is to provide.

[0009]

A memory system according to the present invention comprises a large number of pixels arranged in (2 ^M + X) columns and (2 ^N + Y) rows, where X and Y are 2 ^M-2 and 2, respectively. ^N-1
A (M + 1) -bit horizontal address component indicating the (2 ^M + X) columns and the (2 ^N + Y) rows (N) for storing the following two-dimensional digital video signals.
It has a vertical address component of +1) bits (M + N
And a means for generating a virtual address of +2) bits and for storing the two-dimensional digital video signal, and having 2 ^{M + N + 1} storage locations, each storage location can store one pixel, (M + N + 1) It comprises memory means addressed by a physical address of bits and mapping means for mapping the virtual address to the physical address.

The mapping means maps the most significant bit of the horizontal address component and the most significant bit of the vertical address component forming the virtual address in order to perform mapping from the virtual address to the physical address in units of areas. It is preferable to divide the storage location of the memory means into four areas by utilizing the above.

The four areas include a first area having a half size of all the storage areas, a second area having a half size of the first area, and a second area. It is preferably composed of a third region having a half size and a fourth region having a half size of the third region.

The first area is addressed to the most significant bit of the physical address, the second area is addressed to the most significant bit of the physical address and one adjacent bit, and the third area is Addressing the most significant bit and two adjacent bits of the physical address, the fourth area preferably comprises the most significant bit and three adjacent bits of the physical address.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates the use of an address mapping technique according to one embodiment of the memory system of the present invention, 1280 × 7.
FIG. 2 is a block diagram of a memory system that stores 2D video signals (frame signals) of 20 sizes.

As shown in FIG. 1, the memory system comprises a virtual address generator 10, an address mapping circuit 20 and a memory 30. The virtual address generator 10 generates a "virtual" address having a horizontal address component AH and a vertical address component AV. The virtual address is for addressing multiple storage locations in "virtual" memory. The storage locations are arranged to correspond to the locations of pixels within the signal frame. In the virtual address, the horizontal address and vertical address components are 1
The horizontal address is 11 because it is generated for virtual memory with storage locations arranged from 280 columns by 720 rows.
The vertical address is composed of 10 bits. As shown in FIG. 1, the 11-bit horizontal address component AH [10. . . 0] and 10-bit vertical address component AV [9. . 0] is provided to the address mapping circuit 20.

Address mapping circuit 20 maps virtual addresses to "physical (or real)" addresses in memory 30 using the address mapping techniques of the present invention (discussed below). When the mapping is completed, the 20-bit physical address [19. . 0] is provided to the memory 30.

The address mapping technique according to the present invention is
It is explained as follows.

The 2D video signal of 1280 columns × 720 rows is
It can be represented by (2 ^M + X) × (2 ^N + Y).

Here, M and N are the numbers of bits contained in the horizontal and vertical address components provided in the standard memory. This is expanded as follows.

(2 ^M + X) × (2 ^N + Y) = 2 ^{M + N} +2 ^M Y + X2 ^N + XY (1) Here, if X < 2 ^M−2 and Y < 2 ^N−1 , then (1) is shown as follows.

( ^2M + X) × ( ^2N + Y) < ^{2M + N} + ^{2M + N-1} + ^{2M + N-2} + ^{2M + N-3} (2) As can be seen from the equation (2), the first term is ^{2M + N} pieces. 2) is the half of the first term 2
^{M + N-1} storage locations are required, the third term requires 2 ^{M + N-2} storage locations, which is half of the second term, and the fourth term is 2 ^{M + N−,} which is half of the third term. Requires ³ storage areas. That is, when all storage locations are added up,
2 ^{M + N + 1} or less.

2 (a) and 2 (b) describe the above mapping technique two-dimensionally. In FIG. 2A, there are two square boxes 22 and 24. Box 22
Indicates a 2 ^{M + 1} × 2 ^{N + 1} memory. The box 24 shows a signal frame composed of (2 ^M + X) × (2 ^N + Y) pixels.

As shown in FIG. 2A, the four areas A, B, C and D are arranged corresponding to the four terms of the equation (1). That is, the region A corresponds to 2 ^{M + N} of the first term, the region B corresponds to 2 ^M Y of the second term, the region C corresponds to X2 ^{N of} the third term, and the region D is the last term XY. Are divided according to.

Similarly, in FIG. 2 (b), there are five rectangular regions A ', B', C ', D'and E', and A ', B', C'and D '. The former shows a memory of 2 ^M × 2 ^{N + 1} and the latter shows a storage position of a frame signal after address mapping.

As shown in FIG. 2B, four areas A
′, B ′, C ′, and D ′ are divided corresponding to the four terms in formula (2), that is, 2 ^{M + N} , 2 ^{M + N−1} , 2 ^{M + N−2,} and 2 ^{M + N−3.} is there. The area E'indicates an area remaining after the address mapping. The present invention performs address mapping in consideration of four areas. That is, the virtual address areas A, B, C and D shown in FIG. 2A are mapped to the physical address areas A ′, B ′, C ′ and D ′ shown in FIG. 2B. After address mapping, the memory size is optimized with the actual or physical frame signal.

According to the invention, the partitions corresponding to the four virtual address areas A, B, C and D (FIG. 2 (a)) are the most significant bit (MSB) of the horizontal address component element within the virtual address and Made to the most significant bit of the vertical address component element. If the two most significant bits are 0,0,
If the area A is 0 or 1, the area B is divided into the area B, the area 1, 0 is divided into the area C, and the area 1 is divided into the area D. Therefore, area-by-area address mapping from the virtual address area to the physical address area is performed.

FIGS. 3A to 3D show the structure of one physical address provided directly from the memory 30. Since the size of the physical address memory 30 is 2 ²⁰ , the physical address is composed of 20 bits. In the preferred embodiment, the physical address is divided into four forms corresponding to the four regions A ', B', C'and D '(FIG. 2 (b)). The four forms are shown in Figures 3 (a)-(d). FIG.
As shown in (a), the MSB is 0, which is the area A.
'Indicates. Also, the remaining addresses (excluding MSB) 1
9 bits address each storage location in area A '.

Similarly, as shown in FIG.
B and one adjacent bit 1 and 0 each indicate a region B '. Further, the lower address 18 bits is the area B '.
Are provided to address each storage location in.

As shown in FIG. 3 (c), the MSB
And the two adjacent bits are 1, 1 and 0, which indicates the region C '. Also, the lower 17 bits except the MSB and two adjacent bits are provided to address each storage location in the area C '.

Finally, as shown in FIG. 3 (d), MS
B and the three adjacent bits are 1, 1, 1 and 0, which indicates the area D '. The lower 16 bits except MSB and 3 adjacent bits are provided to each storage location in the area D '.

FIG. 4 is a detailed circuit diagram of the address mapping circuit which constitutes the memory system. As shown in FIG. 4, the address mapping circuit 20 includes a time delay block 40 and 12 multiplexers, and the virtual address area AH [10. . 0] and AV [9. . 0] to the physical address area A [19. . 0] to address mapping.

In four forms of physical address (see FIG.
(A)-(d)), lower address bits A [7. . 0] are the same address bits, that is, A
H [7. . 0], the lower address bits A
[7. . 0] is AH [7. . 0] can be used as it is. However, the upper address bits of the word, ie [19. . 8] are different from each other, it is necessary to change the address.

Twelve multiplexers are provided for address modification.

Each multiplexer has four input terminals I
It has N0, IN1, IN2, IN3 and selection signal input terminals S0 and S1. Although not shown in the drawing, one output terminal is provided through which the selected address is provided to the memory 30. IN0, IN
The virtual addresses provided to 1, IN2 and IN3 have the same address form as shown in FIGS. 3 (a)-(d). That is, the addresses provided to the four input terminals IN0, IN1, IN2 and IN3 of the first multiplexer 42 are AH8, AH8, AV0 and AV.
0. The addresses provided to the four input terminals IN0, IN1, IN2 and IN3 of the second multiplexer 44 are AH9, AH9, AV1 and AV1. After changing the address in the same manner, at the end, four input terminals IN0 of the 12th multiplexer 46,
The addresses of IN1, IN2 and IN3 are 0, 1, 1 and 1, and 0 or 1 is not an artificial virtual address bit but is artificially created and provided. On the other hand, the time delay block 40 receives the address bits A [7. . 0] input timing address A [8. . 19].

The select signals provided to S1 and S0 are the horizontal address MSB or AH0 and the vertical address MSB or AV9.

If AH10 and AV9 are 0 and 0 respectively, I
The address provided to N0 is selected to address area A'of the physical address area. Also, AH10, AV9
Are 0 and 1, respectively, the address provided to IN1 is selected to address the area B'of the physical address area.
If AH10 and AV9 are 1 and 0, respectively, the address provided to IN2 is selected to address the area C'of the physical address area. If AH10 and AV9 are 1 and 1, respectively, the address provided to IN3 is selected to address the area D'of the physical address area.

Although the present invention has been described by means of specific embodiments, it is known that a person skilled in the art of the present invention can modify the invention without departing from the scope of the invention defined by the claims. ing.

[0037]

By optimizing the memory size to the frame size of the two-dimensional video signal, the complexity of the memory system can be reduced, and as a result, the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a memory system of the present invention.

FIG. 2 is a diagram exemplifying a two-dimensional address mapping technique.

FIG. 3 is a diagram showing a structure of one word of a physical address.

FIG. 4 is a detailed diagram of an address mapping circuit used in the memory system of the present invention.

[Explanation of symbols]

 10 virtual address generator 20 address mapping circuit 30 memory 40 time delay block 42, 44, 46 multiplexer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-59-151258 (JP, A) JP-A-61-208173 (JP, A) JP-A- 64-81569 (JP, A) JP-A-3- 53387 (JP, A) JP 3-172974 (JP, A) JP 3-185492 (JP, A) JP 3-189879 (JP, A) JP 4-340634 (JP, A)

Claims (4)

(57) [Claims] 1. A plurality of pixels arranged in (2 ^M + X) columns and (2 ^N + Y) rows, wherein X and Y are 2 ^M−2 and 2 respectively.
^A two-dimensional digital video signal of ^N-1 or less is stored, and a horizontal address component of (M + 1) bits indicating the (2 ^M + X) columns and (N + 1) bits indicating the (2 ^N + Y) rows. Means for generating a virtual address of (M + N + 2) bits having a vertical address component of, and storing the two-dimensional digital video signal,
Memory means having ^{M + N + 1} storage locations, each storage location capable of storing one pixel, and memory means addressed by a (M + N + 1) -bit physical address; and mapping for mapping the virtual address to the physical address. A memory system comprising means. 2. The mapping means, in order to perform mapping from the virtual address to the physical address in units of areas, the most significant bit of the horizontal address component and the most significant bit of the vertical address component forming the virtual address. The storage location of the memory means is 4 using bits.
The memory system according to claim 1, wherein the memory system is divided into individual areas. 3. The four areas include a first area having a half size of all the storage areas, a second area having a half size of the first area, and a second area. 3. The memory system according to claim 2, comprising a third region having a half size and a fourth region having a half size of the third region. 4. The first area is addressed to the most significant bit of the physical address, the second area is addressed to the most significant bit and one adjacent bit of the physical address, and the third area is 4. The memory system according to claim 3, wherein the most significant bit and two adjacent bits of the physical address are addressed, and the fourth area is addressed by the most significant bit and three adjacent bits of the physical address.