JPS60194487A - High-speed memory accessing circuit for crt display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an am memory access control circuit for a CRT display device, and more particularly, to an am memory access control circuit for a CRT display device, which is used in a rask scan type color graphic display device, and is used to control image memory storing graphic data at high speed. Related to image memory access control circuit.

DESCRIPTION OF THE PRIOR ART FIG. 1 is a schematic block diagram of a color graphic display device which forms the background of the present invention.

First, with reference to FIG. 1, operation 1 of a conventional Rask scan type 5-graphic display device will be explained. Let me briefly explain about Z. Data is provided from the host computer 1 to the graphic data management section 3 via the transmission line and the host interno-Ace 2. The graphic data management unit 3 receives data from the Hosmy Combi coater 1, arranges the data so that it can be displayed as a graphic, and stores it in a ceramic buffer (not shown). Data analysis section 4 extracts the contents of the buffer, analyzes the data, and performs arithmetic operations based on the start point coordinates and end point coordinates. Then, the coordinate conversion clip section 5 performs mold clamping of the necessary matrix and its f-form when enlarging or reducing the figure by one rotation or by flattening the figure.

Furthermore, when a part of a figure on the CRT display screen is surrounded by a frame, the figure that protrudes from the frame is clipped.

When the DDA control filling section 6 fills in a figure,
Generates line segments decomposed into inner lines from the coordinates of the vertices of each vector, and fills in the fill data accordingly. D
Generate DA7 fitting wire -〇- nF+! The generator calculates intermediate coordinates in the vector connecting the starting point and the ending point based on data from the DDA control filling unit 6, and develops the calculated result in the image memory 8 to form a straight line. The image memory 8 stores each dot on the line as it is generated by r) DA7.

The data stored in the image memory 8 is given to a video control section 9, converted into an analog signal by D/Δ conversion, converted into a video signal based on a color conversion table, and given to a color monitor 10. . As a result, graphics based on the data output from the host computer 1 are displayed on the color monitor 10.

Figure 2 is a block diagram showing the image memory 8 and its peripheral circuits shown in Figure 1, Figure 3 is a diagram showing the screen configuration of a color monitor, and Figure 4 is a diagram showing the screen configuration of a color monitor. 3 is a timing chart for explaining the operation of the image memory shown in FIG. 2. FIG.

Next, a more detailed operation of the image memory 8 shown in FIG. 1 will be described with reference to FIGS. 2 to 4. The color monitor 10 is shown in FIG.
Bit, Y coordinate Consists of 1024 pits. For this purpose, as shown in FIG. 2, 64. 11 k bytes
)-RAM 81 and 86 are used. As an address signal, the XI output address signal 5AX5 no 1 no 10
, Y read address signals 5AYO to 9. XI included at 1
Nos Shinzuki WAX 5 to 10. Y...Including address signal WA
YO to 9 are sent to the address multiplexer 11. The address multiplexer 11 is given from the memory cycle controller 14] (Based on the ΔSAD signal, address signals ΔDo to 7
is given to D-RAMs 81 to 86.

Further, the lower three bits WΔx2 to WΔx4 of the write address signal are sent to the chip select decoder 12. Based on the applied signal, the chip select decoder 12
Chip select signals C8O to C5 for selecting any one of the six D-RAMs 81 to 86 are applied to the memory cycle controller 514. 4-bit write data WDO or 3 is read modify write gate 13
given to. This read modify write gate 1
3 performs read-modify-write to determine write data DiO to 3. That is, when the write data Wl)O to Wl) 3 is input to the read modify write gate 13, the write data DiO to 3 are transferred to the D-RAM 8 by assuming an appropriate relationship with the output data DOO to 3.
Give from 1 to 86.

The memory cycle controller 14 receives the horizontal synchronization signal RES.
A memory read cycle is determined in synchronization with YNC, and a write cycle is determined by an external write signal 5TORE. Then, address control signals RASO to 5. CASO or 5. Write enable signal WEO
5 to 11-RAMs 81 to 86, respectively, and a load signal L1) to the parallel load shift register 15.

Next, referring to FIG. 4, the operation of the image 9-memory circuit 8 shown in FIG. 2 will be described. During writing, at the falling edge of the address control signal RAS, Y
The Y direction is addressed by the 8 bits of the m write address signals MWAY2 to MWAY9, and the X write address signals WAX5 to WAX10. 8 bits of Y write address signal WAY0.1
The direction is specified as 71 address, and the write data W of 4 pits 1~
When D O<', read modification is performed so that data 3 has an appropriate relationship with read data DOO to 3, and 4-bit data DiOIeK to 3 is changed to r)-RA.
M81J! [Written in block 86.

At the time of reading, the Y direction is addressed based on the 8-bit 1-Y read address signal 5AY2 to 9 at the falling timing of the address control signal RAS, and the 8-bit X direction is specified at the falling timing of the address control signal CAS. Read address signal 5AX5 to 10. The X direction is addressed based on Yl<output address signal SΔY0.1.

As a result, 24 bits of data are read out at a time from the D-RAMs 81 to 86 by 410 bits and applied to the para-1 norroad shift register 15. The parallel load shift register 15 is controlled by the load signal L I) from the memory cycle controller 14.
- Load the data of 24 bits 1 to 1 from RAM81 to '86 in 4ρ columns. At step 1, the predetermined video scanning frequency is shifted by one pulse and output as serial data.

In the color graphic display device configured as described above, the video scanning frequency is determined by D.
- Memory leak of RAM81 to 86. The current D-RAM access speed is limited to a video scanning frequency band of 55 MH2, and 60 l-1z non-interlaced C
It is not compatible with RT display devices. Roughly speaking, parallel load shift 1 to register 1 that shifts successive signals
5, there is no inexpensive integrated circuit that can operate in the 100M1-Iz frequency band, and a new idea is required.

Also, for high-speed writing to image memory, D-RAM
Since there is a limit to the memory recycle of 81 to 86, it is necessary to increase the number of simultaneous write pins. In this case, an efficient lower writing rear configuration must be considered.

OBJECTS OF THE INVENTION Therefore, the main purpose of this invention is to realize a high-speed memory cycle 1) to obtain an optimal CRT display 1 noise that can display good Illii# in a high-resolution CRT display device. An object of the present invention is to provide an image memory access control circuit for an apparatus.

Structure of the Invention To summarize the present invention, an image memory is created by a dynamic random access memory that can be continuously written in N1bb (je mode), and an external video A signal control circuit is provided with J:
The address given by The first parallel-to-serial conversion means serially outputs a plurality of bits of data corresponding to the odd-numbered area of the second data. The data is serially outputted, and the second parallel-to-serial conversion means serially outputs multiple bits of data corresponding to the even-numbered area of the first data. The parallel/serial conversion means is configured to serially output data of a plurality of pins 1 to 1 corresponding to an even number area of the second data.

EXAMPLES The present invention will be explained in more detail below using examples shown in the drawings.

FIG. 5 is a timing chart for explaining the successive output timing of the D-RAM used in one embodiment of the present invention. D-RAM81 to 86 shown in FIG. 2 above
is a second clock pulse (FIG. 5(C)) having twice the frequency of the first clock pulse shown in FIG. 5(a).
) and a third pulse whose phase is shifted by one period of the first clock pulse 13- with respect to this second clock pulse (Fig. 5(d)). 5. The data shown in FIG. 5(b) cannot be read. That is, the odd number data 1, 3, 5, . . . stored in the D-RAMs 81 to 86 are read out by the second clock pulse (FIG. 5(e)). Furthermore, even data 2, 4, .
6... are read out (FIG. 5(r)). Hereinafter, in this embodiment R, the mode in which odd data is read out using the second clock pulse will be referred to as the eVen mode, and the mode in which even numbered data will be read out in the third clock pulse will be referred to as the odd mode.

FIG. 6 is a block diagram showing a memory cycle controller 20 included in one embodiment of the present invention. The memory cycle controller 20 shown in FIG. 6 corresponds to the memory cycle controller 14 shown in FIG.
be. First, with reference to Figure 6, the memory cycle controller 1
- The configuration of the roller 20 will be explained. counter times ff
121 includes two hexadecimal counters, and is configured to be able to operate by switching between a hexadecimal counter and a 24-decimal 14-counter.

The counter circuit 21 is supplied with clock pulses such as a write signal 5TORE and a horizontal synchronization signal RESYNC from the outside. When the counter circuit 21 is given a write signal 5TORE from the outside, it becomes a hexadecimal counter for cycles 1 to 1, and outputs 1'? STOP
If E is not input and GJ, lead cycle, 2 for cycle.
It becomes a quaternary counter. When the write signal 5TORE is input to the counter circuit 21, the counter circuit 21 outputs a reset pulse every time 12 clock pulses are removed. That is, the counter circuit 21 outputs two reset pulses during the cycle. Conversely, if the write signal STORE is not input, the counter circuit 21 becomes a 24-base counter. , 24 clock pulses ffj and one reset pulse is output.

The reset pulse output from the counter circuit 21 is RA
It cannot be given to the S generation shift register 23, the CAS generation shift register 24, the WE generation shift register 25, and the LD generation shift register 26 as a ``-1-'' pulse.

Write signal from outside @5roRF is timing ROM22
It is also given to The timing ROM 22 stores write timing data and read timing data in advance, and outputs the write timing data when the external write signal \'3 STORE is input, and outputs the write timing data if it is not input. Output timing data. The write timing data or read timing data outputted from the timing ROM 22 is stored in the above-mentioned RAS generation shift]~register 23 and CAS generation shift 1~register 2/l.
To ＼! [: Given to the generation shift register 25 and the LD generation shift register 26.

Note that clock pulses are input to these shift registers 234-26. Based on the reset pulse from the counter circuit 21, the RAS generation shift register 23 reads the write timing data or the read timing data read from the timing ROM 22, shifts them sequentially according to the cock pulse, and sets the address. Outputs control signals RASO to 5. Similarly, CAS generation shift registers 1 to 24 output address control signals CASO to 5, WF generation shift register 25 outputs write enable signals WEO to 5, and ID generation shift register 26 outputs load pulse LD1.
．． 2 respectively.

Address control signals RASO to 5. output from these shift registers 23 to 26 are used. CASO or 5
．． Write enable signals WEO to 5 are applied to the D-RAMs 81 to 86 shown in FIG. 2 mentioned above. Also, a load pulse L D 1 output from the LDD shift register 26 .

2 is applied to a parallel load shift register circuit 30 shown in FIG. 7, which will be described later.

FIG. 7 is a block diagram of a parallel load shift register circuit 30 included in one embodiment of the present invention. This parallel load shift register circuit 30 corresponds to the parallel load shift register circuit 15 shown in FIG. First, the configuration will be explained with reference to FIG. 7-17. The parallel load shift register circuit 30, as explained in FIG. 5 above,
A circuit 31 that shifts odd data read from the D-RAMs 81 to 86 in even mode and outputs shift data, and a circuit that shifts even data read in odd mode by shift 1) and outputs shift 1 data. 32.

The circuit 31 for shifting odd number data includes controller 1, roll counters 311 and 312, and shift registers 313 and 3.
14 and a gate circuit 315. A load pulse L D 1 and a clock pulse are input to the control counter 311, and the first 12 of the 24-bit odd data read from the ll-RAMs 81 to 86 are inputted to the control counter 311.
It generates a timing pulse for loading bit data into the shift register 313 in synchronization with the load pulse L D 1, and also generates a switching signal for switching the gate circuit 315. control [1-counter 31
The timing pulse output from 1 is sent to shift register 3.
13, and the switching signal is applied to the gate circuit 18-315. A clock pulse is applied to the shift register 313. Therefore, shift register 3
13 loads the first 12 bits of the odd data read from the D-RAMs 81 to 86 based on the timing pulse from the control counter 311, and sequentially shifts and outputs the data in accordance with the clock pulse.

Shift data output from this shift register 313 is given to a gate circuit 315.

]The control force sensor 312 has a load pulse L I)
2 and a clock pulse are given. Then, the clock pulses are counted in synchronization with the control counter 2, and the II-RAM 8
Of the 24-bit odd data read from 1 to 86, the latter 12-bit data is transferred to the shift register 31/86.
A hold signal for holding the shift register 31/I while the shift register 313, which shifts the data of the first 12 pis I- of the odd data, is performing a shift operation. is also output. The timing pulse and hold signal output from the control counter 312 are applied to the shift 1 noister 314. A clock pulse is input to the shift 1 register 314. Therefore, the shift register 31/I loads the latter 12 bits of odd number data based on the timing pulse from the second control counter 312, maintains the hold state while the small field signal is applied, and loads the first 12 bits of odd data. After the bit odd data is shifted I~, the second half is shifted based on the clock pulse.
Shifts and outputs 2-pill odd data.

The shift 1-data output from the shift register 314 is provided to a gate circuit 315. The circuits 1 to 315 are switched to the shift register 313 side or 314 side based on a switching signal from the control counter 311, and output the output of each shift 1 register 313, 314 as composite shift data.

The circuit 32 for shifting even number data is configured in substantially the same manner as the circuit 31 for shifting odd number data described above, and includes control counters 321 and 322.

Shift 1 noister 323 and 324 and gate circuit 32
Contains 5. Then, the control counter 321 transfers the first 12 bits of even data to the shift register 323 [J
- Outputs timing pulses for
A switching signal for switching the gate circuit 325 is output. In addition, the control counter 322 uses a timing pulse to load the even number data of the second half 12 bits into the shift register 324, and shifts the shift register 323 only during the period when the shift register 323 is shifting the even number data of the first half 12 bits.
A hold signal is output to put the register 324 into a hold state. The shift register 323 shifts the first 12 bits of even data, and after the first 12 bits of even data has been shifted, the shift register 324 shifts the second half 12 bits of even data.
Shift the even number of bits. The gate circuit 325 switches between the output of the shift data 323 and the output of the shift register 324 and outputs it as composite shift data.

FIG. 8 is a timing chart 1 to 21 for explaining the operations in FIGS. 2, 6, and 7. Next, with reference to FIG. 2 and FIGS. 5 to 7, a specific operation of an embodiment of the present invention will be described.

When the write signal STORE is not input from the outside, the counter circuit 21 operates as a 2/1 counter, and outputs a reset signal every time it counts 24 clock pulses as shown in FIG. 8(a). .

The RAS generation shift register 23, CΔS generation shift register 24, WE generation shift register 25, and LD generation shift register 26 load the read timing data read from the timing ROM 22 based on the reset signal from the counter circuit 21, and clock It is sequentially shifted and output according to the pulse. That is, the RAS generation shift register 23 outputs the address control signal RAS shown in FIG. 8(b), and the CAS generation shift register 24 outputs the address control signal CΔS shown in FIG. 8(C).

This address control signal CΔSG has a timing of falling twice in one read cycle period.

This is the "()
, 24 bits of data as the first half data that overturns to 0'', and 24 bits of data as the second half data corresponding to '1.0' of the X read address 5AX5.6 at the next falling timing. This is to output .

Since the WE generation shift 1 register 25 outputs the write enable signal WF, it continues to maintain a high level during the read cycle as shown in FIG. 8(d). The LD generation shift 1 nozzle 26 outputs the dimensional load pulse LI) shown in FIG. 8(e).

This load pulse 1. - Two Ds are output between one lead and one Noicle II.

This includes 2/1 bit data corresponding to o, o'' of X read address 5AX5.6 and
．． This is because it is necessary to load 24 bits of data corresponding to 6 i, o'' into the parallel load shift register circuit 30.

On the other hand, when the write signal 5TORE is input, the counter circuit 21 operates as a hexadecimal counter and outputs a reset pulse every time it counts 12 clock pulses. Each shift 1 register 23 to 26 is shown in FIG. 8(b).
Address control signals RAS, CAS, read cycle 1, enable signal WE, and load pulse LD consisting of read cycles 1 to 2 shown in -) or e') are output.

The D-RAMs 81 to 86 shown in FIG. 2 are supplied with atto1nos control signals RAS and CAS from the memory cycle controller 1 and the above-mentioned memory cycle controller 20, and are supplied with address signals ADO to 7 from the address multiplexer 11 shown in FIG. Then, as shown in FIG. 8 ((+)), the first half and second half of the data are read out within one read-cycle period. That is, each D-RAM 81 to 86 reads the output data DOO to 4 bits 1 to 4, respectively. 3, that is, a total of 24 bits of data is read twice.At this time, each 2/I bit 1
The data .about. is divided into 12-bit odd number data, 12-bit even number data, etc., and is output as described in FIG. The first half 12 bits of odd number data are given to the shift 1 register 313 of the parallel load shift register circuit 30, the first half 12 bits of even number data are given to the shift register 323, and the second half of 12 bits of odd number data are given to the shift register 323. 314, second half 1
The 2-bit even data is provided to shift register 324.

In the parallel load shift register circuit 30, the controllers 1 to 1
The roll counter 311 counts four clock pulses in synchronization with the load pulse LD1 shown in FIG.
It generates a timing signal for loading the first half of 12 bits of odd data into the register 313, and also generates a switching signal for switching the gate circuit 315 to the shift register 313 side. Therefore, shift register 3
13, as shown in FIG. 8(h), the first 12 bits of odd number data are loaded in accordance with the timing signal from the counter 311, and the first 12 bits of odd number data loaded as described above are loaded in accordance with the clock pulse. are sequentially shifted and outputted via the gate circuit 315.

Similarly, the control counter 321 issues a timing signal for loading the first 25-12 bits of even data into the shift register 323, and also switches the gate circuit 325 to the shift 1 to register 323 side. The switching outputs 13 months. .

Therefore, the seed register 323 loads the first 12 bits of even data as shown in FIG. 8(i),
The gate circuit 32 is sequentially shifted according to the clock pulse.
Output via 5.

On the other hand, the control counter 312 increments four clock pulses in synchronization with the next load pulse L D 2, generates a timing pulse for loading the latter 12 bits of odd number data into the shift register 314, and outputs a hold signal to put the shift register 314 in a hold state while the shift register 314 is performing a shift operation.

Therefore, as shown in FIG. 8 (j), the shift register 314 loads the latter 12 bits of odd number data, and then, as shown in FIG.
After the shift operation of 3, the gate circuit 315 is sequentially shifted.
Output via.

After completing the shift operation of the shift register 313, the circuit 315 outputs the control counter 311.
It is switched to the shift register 314 side in accordance with a switching signal from. Similarly, the control counter 322 counts clock pulses according to the next load pulse D2, and generates a timing signal for loading the latter 12-bit even data into the shift 1 register 324, and also generates a hold signal. do. Therefore, the shift 1 register 324 loads the latter 12 bits of even data, and when the hold signal disappears, that is, after the shift register 323 completes the shift operation, the shift 1 register 324 loads it in the manner shown in FIG. 8(n) according to the clock pulse. Shift data sequentially. This data is output via gate circuit 325.

At this time, after the gate circuit 325 completes the shift operation of the shift register 323, it is switched to the shift register 324 side. Therefore, from the gate circuit 315, as shown in FIG. Output odd number data sequentially. Further, as shown in FIG. 8(0), the goo 1~ circuit 325 is connected to the even data of the first half 12 bits 1~ loaded to the shift 1 register 323 and the shift 1~ circuit 325.
The even data of the latter half of 12 pins 1- loaded into the register 324 is output in sequence.

In this way, each of the 24-bit synthesized shift 1 to data output from the gate circuits 315 and 325 is generated as shown in FIG.
The signal is applied to the video control section 9 in synchronization with the clock pulse shown in a), and is converted into a video signal.

In the above description, the I)-RAMs 81 to 86 are used to set the X coordinate to 1280 bits and the Y coordinate to 1024 bits, but the present invention is not limited to this, and the number of coordinates may be further increased. In this case, it is naturally necessary to increase the scanning frequency, but Nibb ILeMo
This can be solved by executing the readout of de four times and configuring the parallel shift 1 to registers in four columns.

Furthermore, in the above explanation, 24-bit data is stored in 6 D
- 16 bits can be read out from RAMs 81 to 86 at once, but the invention is not limited to this, and by changing the configuration of D-RAM.

It is also possible to configure it with 20 pits or 32 bits.

In FIG. 9Δ and FIG. 9B, Y address Yo of D-RAM
1 indicates the data written to −0 or Yo=1, respectively.
FIG. 10 is a diagram showing a shift register for reading out the data written as shown in FIG. 9B from the r)-RAM.

The dimensions shown in FIG. 9A are: uni, r)-RAM, e.g. Y address Y; When writing 24-bit data to -0 or Yo=1, conventionally it was common to write in 4-bit sections. However, with the method of writing 4 bits at a time in one write cycle period, the self-transfer time becomes long, so a method of dividing 8 bits at a time in the x address direction may be considered.

However, in the data writing method in one embodiment of the present invention, as shown in FIG.
0 11.16 17 18 19 to the first group (
1), 4 5 6 7, 1213 14 15.2
0, 21, 22, and 23 are divided into a second group (II), and a total of 818 bits (4 bits in the X direction and 2 bits in the Y direction) are written in one write recycle period. In the graphic display device applied to the present invention, as explained in FIG.
Vector analysis is performed between the starting point coordinates and the ending point coordinates, and the starting point coordinates and the ending point coordinates are linearly interpolated using DI')A7 and displayed on the color monitor 10, so the IC uses 4 bits in the x direction, for example. , 2 pips in the Y direction] is easier to handle.

As shown in Figure 9B, 4 bits in the X direction and 2 bits in the Y direction.
Synthesis of bits To store 8 bits, Yo(r)=
X2・αtenα'Y.

Yo (I) =

When controlled as follows, if α=1, 30-bit data of 4 bits in the X direction and 2 bits of money and goods in the Y direction can be input at a time, and if α-〇, Combined 8-bit data of 8 bits in the direction and 1 bit in the Y direction can be input at once.

When data is written in the manner shown in FIG. 9B described above, when read by the memory cycle controller shown in FIG. 6 described above, 24 bits are written in the X direction.

) 1 direction 1 pixel data is read at once, so
This causes the inconvenience that data is not read out in the order in which it was written. A circuit as shown in Fig. 10 is required.

In FIG. 10, the shift 1 nozzle 33 has 24 pips.
-, 24-bit data read from the D-RAM is loaded with the [1-] pulse, and is sequentially shifted and output in accordance with the clock pulse. The output of the least significant bit of the shift 1 register 33 is returned to the least significant bit, and is output from the least significant bit to the fifth bit 1 which is 4 bits higher than the least significant bit. The output of the least significant bit is applied to one input terminal of AND gate 351, and the output of the fifth bit is applied to one input of AND gate 353. Then, AT1 NOS signal @Yo is given to the other input of AND game 1 to 351, and the other AN
The other input terminal of the D gate 353 receives the address signal Y inverted by the inverter 352. I can get excited. And A.N.
r) The respective outputs of gates 351 and 353 are outputted via OR gate 354.

Address signal Y. is the minimum unit of Yflj marks stored in the image memory, and changes from O to 1 every horizontal scanning line. That is, address signal Y. is set to 0'' or °1'' during the horizontal blanking period. And address signal Y. If becomes 1°', AND game 1-3
51 is opened, and shift data is output from the least significant bits of shift 1 to register 33. Address signal Y. but"
When it becomes O11, the AND gate 353 is heard and shift I-data is output from the fifth bit of the shift register 33.

Effects of the Invention As described above, according to the present invention, different addresses are specified in the N1bblLe mode during one read cycle period of the image memory, and the first and second data are respectively read according to clock pulses of different phases. Read out the data in the odd number m area and the data in the even number area, and
The parallel-to-serial conversion means serially outputs parallel data of multiple bits corresponding to the odd-numbered area of the first data, and after the first parallel-to-serial conversion means outputs the data, the third The parallel-to-serial conversion means receives multiple bits of data corresponding to the back odd number (ii'1 area) of the second data.
The second parallel-to-serial conversion means serially outputs multiple bits of data corresponding to the even-numbered area of the first data, and the second parallel-to-serial conversion means outputs the data. After that, the data corresponding to the even number area of the second data can be received by the fourth parallel-to-serial conversion means and outputted in series. The number of bits read from the image memory can be increased without using the read cycle period as a read cycle period.Therefore, it is possible to display high-resolution graphics using the 601-IZ non-interlace CRT. Furthermore, since the first and second data read from the image memory are divided into odd and even data and output in series, it is also possible to use a relatively low-speed shift register. For example, l
) Since the image memory and peripheral circuits can be configured with inexpensive elements such as RAM and T1-, the cost of the entire system can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a conventional color graphic display device. FIG. 2 is a schematic block diagram of an image memory that is the background of the present invention and to which an embodiment of the present invention is applied. FIG. 3 is a diagram for explaining the screen configuration of a color monitor. FIG. 4 is a timing chart for explaining the operation of FIG. 2. FIG. 5 shows the timing 1/-1 when odd number data and even number data are read out from the image memory used in one embodiment of the present invention.
It is ~. FIG. 6 is a block diagram of the same (memory cycle 9). FIG. 7 is a block diagram of the parallel load shift 1 register circuit. This is a timing chart 1 for explaining the operation of Fig. 7. Figs. 9A and 9B are diagrams showing data stored at the address signal @Yo = 0 or Yo = 1 of the image meter. 10 is a block diagram showing the shift 1 register circuit for reading the data shown in FIG. 9B. In the figure, 8 is an image memory, 9 is a video control roll section, and 10 is a color Monitor, 11 is address multiple pre-crisis, 12 & chip select decoder, 13 is read modify write gate, 20 is memory cycle controller circuit, 21 is counter circuit, 22 is timing ROM, 23 is RAS!F * Shift 1~ register, 2
4 is a CAS generation shift register, 25 is a WE generation shift register, 26 is an IO generation shift register, 30 is a parallel load shift register circuit, 31 is a shift register circuit for odd number data, 32 is a shift for even data Register circuits, 81 to 86 are D-RAMs, 3
11. 312, 321, 322 are control counters, 313, 314, 323, 324 are shift registers,
315 and 325 indicate Goo 1-circuits. i E δ −〇 − + −−ノ + −ノ ν

Claims (2)

[Claims] (1) In a CRT display device that displays figures on a CR7 screen using a plurality of drivers 1,
Contains a storage area corresponding to all drivers 1- on the T screen, N1h
This is a high-speed memory access circuit that accesses at high speed an image memory drawn as J: in a dynamic random access memory that can be read and occupied in BLJE mode, and the circuit accesses data in an odd-numbered area according to clock pulses of different phases. A clock pulse generating means for extracting data of an even-numbered area from the image memory in parallel, an address given by an external video signal control circuit, and first and second clock pulses each consisting of a plurality of bits from each address. atone control means for generating first and second load pulses corresponding to the first and second data while generating an address control signal for reading data from the image memory; a tenth parallel-to-serial conversion means for receiving and serially outputting data to a plurality of pins 1 corresponding to an odd numbered area of the first data read out; the first data read out from the image memory; a second parallel-to-serial converter that receives and serially outputs data of a plurality of bits corresponding to an even numbered area among the second data read from the image memory; a third parallel-to-serial conversion means for receiving and serially outputting data of multiple bits; a fourth parallel-to-serial converter for serially outputting data based on the first load pulse; The first and third parallel-to-serial conversion means are disabled, and after the first parallel-to-serial conversion means outputs data, the first and third parallel-to-serial conversion means are activated. Based on the first control means to control and the second load pulse, the second parallel-to-serial conversion means outputs data in series.
#4 of Book R! controlling the second and fourth parallel-to-serial conversion means to disable the direct conversion means and enable the fourth parallel-to-serial conversion means after the second parallel-to-serial conversion means outputs data; A high speed memory access circuit for a CRT display device, comprising a second control means. (2) The first control means counts clock pulses from the clock pulse generation means based on the first [l-do pulse, and
a tenth counter circuit that outputs a third load pulse for loading a plurality of bits of data corresponding to an odd numbered area of the first data into the parallel-to-serial conversion means; Based on C1, a clock pulse from the clock pulse generation means is used as an argument to load a plurality of bits of data corresponding to an odd-numbered area of the second data into the third parallel-to-serial conversion means.
and a second hold signal for placing the third parallel-to-serial converter in a hold state while the first parallel-to-serial converter is outputting data. a counter circuit, the second control means counts clock pulses from the clock pulse generation means ^t1 based on the second load pulse, and outputs the clock pulses to the second parallel-to-serial conversion means. a third counter circuit that generates a fifth load pulse for loading data of a plurality of pips 1 to 1 corresponding to an even number area of the first data; The clock pulse generating means calculates the 11 ivy pulses of Rihi Ranori, and inputs the plurality of bits of data corresponding to the even number area of the second data to the fourth parallel-to-serial converting means. While the 20th parallel-to-serial conversion means is outputting data, the 4th
2. A high-speed memory access circuit for a CRT display device according to claim 1, further comprising a fourth counter circuit for generating a second hold signal for placing the parallel-to-serial conversion means in a hold state.