JP3048153B2 - Memory circuit and method of storing data stream - Google Patents

Description

Description: FIELD OF THE INVENTION The invention relates generally to digital memory circuits. In particular, the present invention relates to digital memory circuits that are particularly advantageous when used for video.

BACKGROUND OF THE INVENTION For digital TV, VCR and related video applications, a combined frame or field memory for storing pixels such that the entirety represents the entire video frame. Often used. The frame memory is used to generate various special effects such as frame fixation, zoom, pan, split screen monitor operation, and the like. While frame memories can be constructed using ordinary discrete integrated circuits, such frame memories are relatively expensive, consume undesirably large amounts of power, and undesirably large locations. Occupy. This is a major problem when the purpose of such a frame memory is to use it in a product. Thus, a single integrated circuit, alone or in combination with as few other integrated circuits as possible, would be an improvement over a frame memory constructed using ordinary discrete integrated circuits. become.

Conventional integrated circuit devices have sought to address this frame memory problem. However, these devices have not been able to create an architecture that adequately meets the needs for video. For example, when creating a wide variety of special effects, a small number of frames typically required
Devices containing only memory functions can be used. But
Since it has to be combined with a large number of conventional individual integrated circuits, there is little improvement over frame memories consisting solely of conventional individual integrated circuits. On the other hand,
Conventional frame memory integrated circuits can include random access memory with complete on-chip address calculations. In video applications utilizing such a frame memory, the entire frame memory is accessed serially. In this way, the special effects of frame fixed and split screen monitor operations are supported. However, zoom and pan functions are not possible or practical with such devices.

Accordingly, the industry does not require a large amount of peripheral integrated circuits, and the circuitry of the circuit to provide a wide range of various special effects.
There is a need for a frame memory integrated circuit that optimizes the architecture.

SUMMARY OF THE INVENTION Accordingly, an advantage of the present invention is to provide a frame memory circuit that allows limited random access. Thus, a device constructed in accordance with the present invention can be efficiently used for a wide variety of special effects video applications.

Another advantage of the present invention is that it provides a memory circuit that includes various address calculation modes. That is, a portion of the address calculation for a particular effect function can be transferred to a memory circuit, and in video applications utilizing this memory circuit, there is no need to allocate processing power to the calculation.

The advantages of the invention described above are, in one form, for data
It is performed by a memory circuit that stores and supplies the stream. This memory circuit enables both serial access and random access. The data input of the random access memory array is coupled to a data buffer, which allows the operation of the memory array to be synchronized with the data stream. . The address input of the random access memory array is coupled to an address sequencer, which generates a series of memory addresses that are successively applied to the memory array. An address buffer register is also coupled to the address sequencer. An address buffer register provides a random access address to the address sequencer and initializes a series of memory addresses provided by the address sequencer.

The invention will be better understood from the following detailed description of the drawings. Throughout the drawings, the same reference numerals are used for similar parts.

FIG. 1 shows a video frame 10 as it appears on a picture tube or other video display terminal. Although the frame 10 appears to the viewer as a continuous video image, the frame 10
10 can be represented electrically as a number of digitized pixels 12. Each pixel 12 defines parameters such as color and relative intensity for one of a number of very small areas in the image of frame 10. Accordingly, frame 10 may include a relatively large number of pixels 12. For example, pixel 12
A frame with 488 columns and 488 rows of pixels 12 has a total of 238,144 pixels per frame.

Typically, the pixels 12 are transmitted or otherwise processed in a predetermined order to preserve the spatial relationship between the pixels 12. For example, in a typical raster scanning application, pixel 12 is a pixel 12 representing pixel 12 in the first row and first column of frame 10.
Starting at a, the data can be transmitted to the memory device or the video display device in sequence, which is the first of the frames 10.
It continues in order up to pixel 12b representing pixel 12 in the last column of the row. Immediately after transmitting the pixel 12b and synchronization information (not shown), the pixel 12c representing the pixel 12 in the first column of the second row is transmitted, followed by the second row of the frame 10. The remaining pixels 12 can be transmitted in order. The transmission of pixels 12 continues in this manner until a pixel 12d representing pixel 12 in the last column of the last row of frame 10 has been transmitted. Therefore, any processing device that knows the timing relationship between pixel 12 and the first pixel 12a will be
You know the spatial position of the pixels 12 in the system 10, or you can easily calculate it.

Digital TV, VCR, etc.
May have a large frame memory or a field memory capable of storing data. The combination of the pixels 12 is a serial data stream for the frame memory.
It becomes. Apart from special effects, the relative order of the pixels 12 in this serial data stream must generally be preserved when reading from frame memory to preserve the spatial relationship of the pixels 12. Must. However, various special effects do not require an order to be preserved in this way, and when pixels 12 are read from frame memory, preserving the order of pixels 12 wastes valuable computing time. There is.

One such special effect is a zoom effect that enlarges a small portion of the frame to fill the entire video display. For example, if the frame 10 of FIG. 1 represents the entire video display, the area of the frame 10 delimited by rows i and j and columns m and n is enlarged by the zoom special effect. , The entire frame 10 can be filled. For this reason,
In the special effect, lines i and j in frame 10
And all pixels 12 outside the area delimited by columns m and n have no effect and can be discarded. In other words, pixels 12 that do not work in this manner need not be stored in or read from frame memory. Therefore, the pixel 12 at column m and row i is used as the first pixel 12a of the zoom special effect. Valid pixels 12 can be overlapped to complete an entire row of frame 10, and rows can be overlapped to complete the vertical component of the zoom effect.

In the split screen special effect, the entire frame 10 is defined by a screen such as that delimited by row j and the last row of the frame 10 and column n and the last column of the frame 10. Can be reduced to a small area. To achieve this special effect, only one pixel 12 is used for every predetermined number of pixels 12 in the entire frame 10 of pixels 12, and the intermediate inactive pixels are used.
Ignore 12 (ie skip pixels). In the example shown in FIG. 1, a reduced frame is formed using only pixels 12 from one for every three columns of frame 10 and one for every three rows.

The present invention provides a memory circuit which functions as a frame memory and can efficiently implement the above-mentioned and other special effects. FIG. 2 is a block diagram of the memory circuit 14 constructed according to the present invention. Generally, the memory circuit 14 of the preferred embodiment comprises 262,
Represents a single-chip integrated circuit having a storage content of 2 ²⁰ , or 1,048,576 bits, organized as 144 4-bit wide words. Therefore, the 488 × 488 frame of pixel 12
A sufficient amount of word is provided to buffer or store the entire system (see FIG. 1). If more than four bits of precision are required to accurately describe each pixel, additional memory circuitry 14 can be used to store such extra bits.

Memory circuit 14 generally operates in a serial access mode, but has a special feature that allows random access of memory circuit 14 on a limited scale. One skilled in the art will understand that serial access refers to a data storage and read mode in which data must be read from memory in the same order as the data was stored in memory. It will be understood. Further, random access refers to the ability to write, read, or otherwise access any location in the memory array by providing a unique address corresponding to that memory location.

More specifically, the memory circuit 14 has a serial pixel data input.
16a, which in the preferred embodiment provides 4 bits of data. Serial pixel data input 16a is coupled to the input port of write serial latch 18a, and write serial latch 8a.
The output port of a is coupled to the input port of write register 20a. The output port of write register 20a is coupled to data input port 22a of memory array 24. In the preferred embodiment, memory array 24 has 2 ¹⁸ , or 262,144.
A dynamic random access memory (DRAM) array with four 4-bit memory locations. memory·
The data output port 22b of array 24 is coupled to the data input port of read register 20b, and the data output port of read register 20b is connected to the data input port of read serial latch 18b. To be joined. The data output port of the read serial latch 18b is coupled to the serial pixel data output 16b, which, in the preferred embodiment, provides four bits of data.

The serial write clock terminal 26a is the write address generator 2
8a, coupled to the clock input of the arbitration and control circuit 30, and the write serial latch 18a. Similarly, the serial read clock terminal 26b is connected to the read address generator 28b, the arbitration and control circuit 3
0, and is coupled to the clock input of the read serial latch 18b. The output of the refresh address and timing circuit 32 is coupled to the input of the arbitration and control circuit 30, and the output of the arbitration and control circuit 30 is the clock input of the write register 20a, the clock input of the read register 20b, the memory array 2
4 and is coupled to the address input of the memory array 24.

As shown in FIG. 2, address generators 28a and 28b are structurally similar to one another in a preferred embodiment. That is, the write control data terminal 34a is coupled to the serial data input of the address buffer register 36a in the write address generator 28a. Read control data terminal 34b is coupled to the serial data input of address buffer register 36b in read address generator 28b. Similarly, write control strobe terminal 38a is coupled to the clock input of address buffer register 36a, and read control strobe terminal 38b is coupled to the clock input of address buffer register 36b. The data output of address buffer register 36a is coupled to the data input of address sequencer 40a, and the data output of address buffer register 36b is the data input of address sequencer 40b. Is combined with Write reset terminal 42a is coupled to the clear input of address sequencer 40a, and write transfer terminal 44a is coupled to the preset input of address sequencer 40a. Read reset terminal 42b is coupled to the clear input of address sequencer 40b, and read transfer terminal 44b is coupled to the preset input of address sequencer 40b. Terminal 26a is address generator 2
8a is coupled to the clock input of the address sequencer 40a and the terminal 26b is connected to the address sequencer in the address generator 28b.
Coupled to the clock input of the gen 40b. The output (46a) of address sequencer 40a provides an output signal from address generator 28a and is coupled to the input of arbitration and control circuit 30. Similarly, the output (46b) of address sequencer 40b provides an output signal from address generator 20b and is coupled to arbitration and control circuit 30. The memory circuit 14 can be provided in a 20-pin integrated circuit package.

As mentioned earlier, the memory circuit 14 has a serial access mode.
Mode or limited random access mode. Further, data can be stored or written to the memory circuit 14 asynchronously with reading or supplying data from the memory circuit 14. Terminal 42
By activating the write reset signal of a to clear the address sequencer 40a, the memory circuit 14 can be written in series. Thereafter, while a serial write clock signal is output to the terminal 26a, four bits are input to the data input 16a.
By applying a bit data nibble, a 4-bit wide serial data stream can be stored in the memory circuit 14. Once the serial write clock signal is issued, the write serial latch 18a temporarily stores or buffers one 4-bit data nibble. Write serial latch 18a acts as a 4-bit wide shift register. Therefore, the subsequent 4-bit nibble of the serial pixel data stream applied to data input 16a is:
Thereafter, when the serial write clock signal is output, the serial latch 18a shifts in.

Further, each time a serial write clock signal is issued, the address sequencer 40a of the write address generator 28a supplies a new random access address to the arbitration and control circuit 30. In other words, the address sequencer 40a stores the data stream stored in the write serial latch 18a.
A stream of an address corresponding to the system is supplied to the arbitration and control circuit 30.

Arbitration and control circuit 30 receives addresses from address generators 28a-28b and refresh address and timing circuit 32. Circuit 30 monitors these inputs and various timing signals to determine which addresses provided to these inputs are to be transferred to memory array 24. Arbitration and control circuit 30 includes the usual logic circuitry that controls the timing operation of the dynamic memories that make up memory array 24. That is, the arbitration and control circuit 30
Sends the address generated by the address generator 28a to the memory array 24 so that data can be written to the memory array 24, but for refresh operations or read access of the memory array 24. , A delay may occur. Thus, the arbitration and control circuit 30 also has storage to prevent the addresses generated by the address generators 28a-28b from being lost when immediate access to the memory array 24 is prevented. When the arbitration and control circuit 30 determines when serial pixel data can be written to the memory array 24, the data is transferred from the write serial latch 18a to the write register 20a, and then the memory array. Written on 24. Therefore, the combination of the write serial latch 18a and the write register 20a is of a double buffer type, so that the memory array 24 can operate asynchronously with respect to storage of serial pixel data in the memory circuit 14.

Reading data from memory array 24 is performed in a manner similar to that described above for storing data in memory array 24. That is, the address generated by the address generator 28b is transferred through the arbitration and control circuit 30 at an appropriate time, and the data from the memory array 24 is read into the read register 20b. The data is transferred to the read serial latch 18b, and the data is transferred to a data output terminal by applying a serial read clock signal to a terminal 26b.
16b so that it can occur. The generation of the serial data output (16b) is asynchronous with respect to the operation of the memory array 24 and also for storing serial pixel data in the memory circuit 14 from the terminal 16a. It is asynchronous.

The limited random access feature of the memory circuit 14
Obtained by address generators 28a-28b. In the memory circuit 14 of the embodiment shown in FIG.
a and read address generator 28b are write address generators.
The structure and operation are the same, except that the read address generator 28b generates a read address while the read address generator 28b generates a write address. Therefore, as an explanation of both address generators 28a-28b, the write address generator
Only 28a will be explained. Those skilled in the art will appreciate that the preferred embodiment operates the read address generator 28b in a similar manner.

The random access address is obtained by sequentially applying this address to the control data terminal 34a and activating a control strobe signal applied to terminal 38a when valid data appears at terminal 34a. It can be loaded serially into the address buffer register 36a. For this reason, the second
In the illustrated embodiment, the address buffer register 36
a represents a serial shift register. The use of a serial shift register saves the number of external components required to construct the memory circuit 14 on an integrated circuit, as compared to a parallel load register. After the random access address is input to the address buffer register 36a, a write transfer signal is applied to the terminal 44a, thereby making it available to the data sequencer 40.
can be forwarded to a. In the preferred embodiment of the present invention, the address sequencer 40a has a presettable 2
It may represent a binary counter or other pre-settable sequencer circuit. That is, the transferred address begins a series of addresses subsequently generated by the address generator 28a. Address sequencer 40
If a is a binary counter, subsequent addresses increment or decrement, starting from this preset value.

If the memory array 24 stores 218 4-bit words, the address buffer register 36a stores ¹⁸ bits.
Advantageously, it is a bit register, and the address sequencer 40a may be an 18-bit counter or other sequencer circuit. On the other hand, the address buffer register 36a and the address sequencer 40a may have a smaller number of bits, for example, 9 bits. Address buffer register for 9 bits
Random access address supplied from 36a are each Bae - di- or line 2 ^9, namely 512 word - If storing the de memory Paix - can access the first di or row.

By providing limited random access features, including the address buffer register 36a,
The memory circuit 14 can be efficiently used by the special effect. For example, using serial access mode,
By writing the entire frame to the memory array 24,
A zoom effect can be achieved. Row i column m in FIG.
The starting pixel address, such as the pixel address at, can be loaded into the read address buffer register 36b and transferred to the address sequencer 40b. Frame 10
Of the portion to be expanded to the entire frame, for example, row i, for example, until the pixel corresponding to row i, column n appears at the output terminal 16b, the serial mode or the sequential mode.
Read from memory array 24 with Random access from address buffer register 36b
By transferring the address to the address sequencer 40b, a certain number of rows can be repeated as many times as necessary to perform the vertical zoom operation. Then, the line (i +
1) The address corresponding to the pixel in column m is loaded into the address buffer register 36b, and the address
It can be transferred to the kensa 40b. This process is continued until the last pixel of the frame to be enlarged is output from the memory array 24. This feature allows the video device to begin accessing memory circuit 14 from the first address, such as pixel 12a (shown in FIG. 1), to access unused pixels stored in memory array 24. No need to do. As a result, the operation becomes faster.

In the present invention, another embodiment of the address generators 28a to 28b
Is also conceivable. A first alternative is address generator 28a.
28b are shown in FIG. FIG. 3 shows only one address generator 28. The address generator 28 shown in FIG. 3 is a write address generator 28a or a read generator 28b.
(See FIG. 2).

In the address generator 28 of the first alternative embodiment, the address buffer registers 36 can be loaded either serially or in parallel. That is, it may represent either the write control data terminal 34a or the read control data terminal 34b as described above with reference to FIG.
Is coupled to the serial data input of the address buffer register 36. A control strobe terminal 38 is coupled to the serial clock input of the address buffer register 36 and the serial clock input of the address offset register 48. The parallel data output of address buffer register 36 is coupled to a first input of adder 50 and to a data input of address sequencer 40. The parallel data output of address offset register 48 is coupled to a second input of adder 50. The output of adder 50 is coupled to the parallel data input of address buffer register 36, and transfer terminal 44 is coupled to the parallel clock input of address buffer 36 and the preset input of address sequencer 40. The most significant bit of the parallel data output or serial output bit of address buffer register 36 is coupled to the serial data input of address offset register 48. Series clock terminal
26 is coupled to the clock input of the address sequencer 40, and the reset terminal 42 is coupled to the clear input of the address sequencer 40. The data output of address sequencer 40 is coupled to the output (46) of the address generator.

In this alternative first embodiment, the address buffer register 36 and the address sequencer 40 operate in a manner similar to that described above for the address generators 28a-28b of FIG. However, in this first alternative embodiment, the control data supplied to terminal 34 is used to load both address buffer register 36 and address offset register 48. Therefore, the extra bits of the control data
It is loaded into memory circuit 14 without the need for extra integrated circuit pins. In addition, the most significant bit or serial output bit 51 from the address off register 48 can be sent to the control data input for the other of the read and write address generators 28a and 28b (see FIG. 1). Is advantageous. Further, the control strobe signal applied to terminal 38 can be sent to the other of the control strobe terminals 38a and 38b of FIG. This 2 between address generators 28a and 28b
One connection removes two integrated circuit pins from the structure shown in FIG.

In the first alternative embodiment just described of the present invention, the control data contained in the address offset register 48 is:
The value is added to the value of the current initial address stored in the address buffer register 36, and becomes the value of the new random access address for initialization. This new initial value is stored in the address buffer register 36 when the value of the current address is transferred to the address sequencer 40.
Is loaded.

Still referring to FIG. 1, this first embodiment of the present invention will be described.
Other embodiments of the present invention may be advantageous, for example, when implementing zoom special effects. That is, address offset
The address offset value loaded into register 48 is
It may represent the amount of unused pixels that occur between column n of one row and column m of the next row. At the end of each row of the frame, a transfer signal is issued to terminal 44, and the random access address of the next pixel to be used, corresponding to column n of the next row, is automatically calculated and stored in address buffer register 36. Once stored, another series of sequential accesses of the memory circuit 14 is initiated. A video device using the memory circuit 14,
There is no need for components external to the memory circuit 14 to calculate this address, so it is less complicated.

Another second embodiment of the address generators 28a-28b shown in FIG. 2 is shown in FIG. The embodiment of FIG. 4 shows that the random access address can be loaded into the address buffer register 36 in a parallel fashion, which is more compatible with ordinary microprocessor integrated circuits. There are good things. However, the number of integrated circuit pins required to construct this embodiment is greater than in the embodiment described with reference to FIGS. FIG. 4 further shows that in addition to the address buffer register 36, an alternate address buffer register 52 is included. In particular, control data terminal 34 is advantageously provided to an 8-bit microprocessor data bus, which provides a separate 8-bit portion 54a, 54a, of address buffer register 36. It is connected to the data input of 54b and 54c. In addition, a control data terminal 34 is coupled to the data inputs of separate 8-bit portions 56a, 56b, 56c of the alternate address buffer register 52. Data of the individual parts 54a to 54c
The data outputs together form a 24-bit bus, which is coupled to the first data input of multiplexer 58. Similarly, the data output of the individual parts 56a to 56c is a 24-bit data output.
Constitutes a bus, which is coupled to the second data input of multiplexer 58. The data output of multiplexer 58 is
In this second alternative embodiment, it is coupled to the data input of a binary counter which acts as an address sequencer 40. Of course, those skilled in the art will recognize that the address buffer register 36
It will be apparent that the number of sub-registers included in the alternate and alternate address buffer registers 52, and the number of bits in the bus above, can vary significantly depending on the requirements of the particular application.

Further, microprocessor address input terminals 60a, 60b,
60c is coupled to the address input of decoder 62, and address input terminal 60d is coupled to the enabled input of decoder 62. The previously described control strobe terminal 38 is coupled to the enabled input of the decoder 62. The outputs (01 to 06) of the decoder 62 are applied to the clock inputs of the separate portions 54a-54c of the address buffer register and the clock inputs of the separate portions 56a-56c of the alternate address buffer register, respectively. Be combined. The output (07) of decoder 62 is coupled to the clock input of flip-flop 64. The flip-flop is configured to toggle when the clock input is activated.
The output of flip-flop 64 is coupled to a select input of multiplexer 58. Decoder 62 output (08) is a binary counter
Combined with 40 preset inputs. The serial clock 26 is 2
Connected to the clock input of the hex counter 40 and the reset terminal
42 is a clear input of a flip-flop 64 and a binary counter
Coupled to 40 clear inputs. The output of the binary counter 40 is coupled to the output (46) of the address generator 28.

In the address generator 28 of this other second embodiment, 1
One initialization random access address can be stored in address register 36, and the alternate initialization random access address is stored in alternate address buffer register 52. A microprocessor (not shown) storing these addresses in memory circuit 14 through normal memory operations or I / O write operations to the addresses specified by the signals applied to terminals 60a-60c. Can be. The address input bit applied to the terminal 60d corresponds to the write address generator 28a.
And read address generator 28b (see FIG. 1). By applying an activation signal to the reset terminal 42, the flip-flop 64 and the binary counter 40 can be initialized to a clear state.
In this regard, the address generator operates in much the same manner as described above with respect to FIG. However, the alternate random access address stored in the alternate address buffer 52 can selectively preset the binary counter 40. A microprocessor write operation for causing the flip-flop 54 to toggle, followed by a microprocessor write operation for transferring data to the binary counter 40, causes the binary counter 40 to have an alternate random access address. Preset. The flip-flop 64 can perform a toggle operation by performing a write operation to an address that activates the output (07) of the decoder 62. The transfer operation from the selected one of the address buffer registers 36 and 52 is performed by writing to the address which operates the output (08) of the decoder 62.

Alternate address buffer registers 52 can be advantageously used by video equipment to efficiently buffer certain lines in the data frame. Since the memory circuit 14 of the preferred embodiment has a memory large enough to accommodate 2 ¹⁸ , i.e., 262,144 pixels, the memory circuit 14 may have, for example, a column of 480 pixels and 480 pixels. Has an unused memory location when used to store a single data frame with
Thus, random access addresses in this unused portion of memory are replaced with alternate address buffer buffers.
It can be loaded into register 52. This alternate address value is transferred to a binary counter 40, and then the pixels on this line are stored sequentially in an unused portion of the memory circuit 14 to provide one of the frames. Can be efficiently stored in the memory circuit 14.

Further, other embodiments of the address sequencer 40 are contemplated in the present invention. As shown in FIG.
Sequencer 40 may represent a conventional presettable, clearable binary counter. These circuits are well known and need not be described at length here. However, alternatively, the address sequencer 40 may represent a circuit that increments or decrements by a variable step value that may be different from a value of one. Such a circuit is shown in FIG.

That is, in FIG. 5, the data input of the address sequencer is coupled to the first input of the multiplexer 66, and the preset terminal of the address sequencer is coupled to the select input of the multiplexer 66. The output of multiplexer 66 is coupled to the data input of register 68 to provide an address sequencer.
Forty clock inputs are coupled to the clock input of register 68. Similarly, reset terminal 42 is coupled to the clear input of register 68. The data output of register 68 is
It becomes the data output of the sequencer 40 and the first output of the adder 70.
To the input of The output of the adder 70 is a multiplexer
It is coupled to 66 second inputs. The control data terminal 34 described above with reference to FIGS.
Data input. In addition, a control strobe terminal 38 previously described with respect to FIGS. 2-4 is coupled to the clock input of register 72. The data output of register 72 is coupled to a second input of adder 70.

In the address sequencer 40 of the embodiment shown in FIG. 5, the register 72 may be either a parallel or serial load type register as previously described with respect to FIGS. . Further, if register 72 is a serial load register, then register 72 may be one of many coupled into a long chain of serial load registers as previously described with respect to FIG. May be one register. The data loaded into the register 72 is an address sequencer.
Numeral 40 indicates an increment step when an address is generated successively to the output (46) of the address generator 28. The current output of the address sequencer 40 is
At 70, it is added to the increment value of this step,
The data is returned to the register 68 via the multiplexer 66. Thus, the subsequent address generated by address sequencer 40 is equal to the previous address plus the address step increment contained in register 72. This address step increment is 1
Does not need to be equal to, but may be equal to any positive or negative value. Further, if the number of bits entering the bus connecting register 72, adder 70, multiplexer 66 and register 68 to each other is greater than the number of bits appearing at the output of address sequencer 40, the subsequent address will be a fraction of a step. Only can be incremented.

By applying an operation signal to the preset terminal, supplying data to the data input terminal, and outputting a clock signal of the address sequencer 40, the address sequencer 40 presets a random access address. , Or with it. That is, the random access value for the initial setting is directly loaded into the register 68. Further, by applying a reset signal to the clear input terminal, the address sequencer 40 can be cleared or reset.

Further, referring to FIG. 1, the address and address shown in FIG.
The sequencer 40 is useful in implementing a split screen special effect such that the entire frame is displayed on only a small portion of the video screen, as shown in the lower right portion of FIG. In this special effect, when all the pixels 12 of the frame 10 are stored in the memory circuit 14, when forming the reduced screen, only one pixel is provided for each group of a predetermined number of storage pixels. Works. Address sequencer 40 shown in FIG.
Supplies a series of addresses that omit unused pixel addresses so that the memory circuit 14 can supply only valid pixels.

In summary, the present invention has provided a memory circuit that allows a video device to efficiently implement special effects. In particular, by incorporating various limited random access features, memory circuit 14 stores and / or supplies only valid pixels for certain special effects,
Unused pixels can be prevented from being stored or supplied. Thus, valid pixels can be recovered from memory circuit 14 faster than if a conventional frame memory circuit were used.

What has been described above uses preferred embodiments to illustrate the invention. However, those skilled in the art will recognize that various modifications can be made to these embodiments without departing from the scope of the present invention. For example, read address generator 28b need not be exactly the same as write address generator 28a. Further, while the embodiments shown in FIGS. 3-5 have been described above as alternative embodiments, those skilled in the art will recognize that two or more of these alternative embodiments may be incorporated into one embodiment. It does not prevent combination with the memory circuit 14. Furthermore,
Those skilled in the art will appreciate that additional address processing capabilities can be incorporated into the frame memory circuit 14. Such additional address processing capabilities include frame
Signal indicating the end of the frame line, signal indicating the end of the frame,
Automatic transfer of the random access address to the address sequencer when the end of line and end of frame signals occur can be included. In addition, specific frames and memory
While the dimensions of the array have been described above, it should be appreciated that the invention is not limited to any particular dimensions. It is to be understood that all such modifications apparent to those skilled in the art are included within the scope of the present invention.

 In connection with the above description, the following items are further disclosed.

(1) In a memory circuit for storing and supplying data streams, which enables both serial access and random access, address input and data port
A random access memory array having a data port and a data port coupled to a data port of the memory array.
A data buffer for synchronizing the operation of the memory array with the data stream, and an output having a data input and coupled to an address input of the memory array. An address sequencer for generating a series of memory addresses to be applied to the memory array one after the other, and data of the address sequencer.
Has an output coupled to the
An address buffer register for providing a random access address that initializes the series of memory addresses generated by the sequencer.

(2) The memory circuit according to (1), wherein the address buffer register is a serial load shift register.

(3) In the memory circuit described in (1), the data which is further connected to the address sequencer and which is stored in the address buffer register is stored in the address sequencer.
A memory circuit having a terminal adapted to receive a signal to be transmitted to a kensa.

(4) The memory circuit according to (1), wherein the memory array, data buffer, address sequencer, and address buffer register are contained in one integrated circuit.

(5) In the memory circuit described in (1), the address sequencer is a binary counter, the data input is coupled to the output of the address buffer register, and the output is the memory array. Memory circuit coupled to the address input of.

(6) In the memory circuit described in (1), the address sequencer has a data input coupled to a node acting as a data input of the address sequencer, and an address sequencer. The first with an output acting as the output of the
And a second register having an output and storing the value of the increment step, a first input coupled to the output of the first register, and a second input coupled to the second input. A memory circuit comprising: an adder coupled to a register output; and an output coupled to a data input of said first register.

(7) In the memory circuit described in (1), the data
A data buffer synchronizes the operation of the memory array with data streams stored in the memory array, and an address sequencer stores the stored data streams in the memory array. Generating a memory address to be written to the array; and further comprising a memory circuit having a data port coupled to the data port of the memory array for controlling the operation of the memory array. A second data buffer for synchronizing with a data stream supplied from the memory circuit;
A data source having an output and a data input coupled to an address input of the array and provided from a memory array.
A second address generating a series of memory addresses to be applied to the memory array to read the stream;
A randomizer having an output coupled to a data input of a second address sequencer and a second address generator for initializing a series of memory addresses generated by the second address sequencer. Second to supply access address
And an address buffer register.

(8) In the memory circuit described in (1), the memory circuit further has an output and is connected to an address offset register for storing address offset data and an output of the address buffer register. A first input, a second input coupled to the output of the address offset register, and an output coupled to the data input of the address buffer register. A memory circuit having an adder for generating a random access address representing a sum of an address and the address offset data.

(9) In the memory circuit described in (1), the address sequencer has an alternate address buffer register having an output coupled to the data input of the address sequencer. A memory circuit for generating an alternate random access address that initializes an alternate series of memory addresses generated by the memory.

(10) In an integrated memory circuit capable of serial access and limited random access for storing and supplying data streams, address inputs, data input ports and data are provided. A random access memory array having a data output port, and a data port coupled to a data input port of the memory array;
A first data buffer for synchronizing with a data stream for storing the operation of the memory array, and a data port coupled to a data output port of the memory array And data supplied with the operation of the memory array.
A second data buffer for synchronizing with the stream, and a first address generator for generating an address used to write the data stream stored in the memory array; A second address generator having first and second address generators for generating addresses used to read data streams supplied from the memory array; And each of the second address generators has an output and a data input coupled to the address input of the memory array, and the memory address applied to the memory array.
A binary counter for counting addresses, and a serial load having an output coupled to the data input of the binary counter and providing an initial random access memory address to start counting of the binary counter. Integrated memory circuit consisting of an address buffer register.

(11) In the integrated memory circuit described in (10),
Each of the first and second address generators further has an output, an address offset register for storing address offset data, and a first input for an address buffer register. Coupled to the output
Is coupled to the output of the address offset register, and the output is coupled to the data input of the address buffer register, and the sum of the previous random access address and the address offset data is obtained. An adder supplying the address buffer register.

(12) In the integrated memory circuit described in (10),
Each of the first and second address generators has an output coupled to the data input of the binary counter and provides an alternate initial random access memory address for the binary counter to count. An integrated memory circuit having alternate address buffer registers.

(13) In a method of storing and supplying data memory using a random access memory array, a data stream stored and supplied asynchronously to the operation of the memory array. -The data
A stream is streamed into and out of the memory array and a data stream is buffered in and out of the memory array to generate a random access address and a series of addresses initialized by the random access address. And applying the addresses sequentially to the random access memory array.

(14) The method according to (13), wherein the step of generating a random access address includes the step of serially loading the random access address into a register.

(15) In the method described in (13), the step of generating a sequence includes generating an address that is successively applied to the random access memory array by using an address in the data stream. Counting the number of successive data items.

(16) In the method described in (13), the step of generating a sequence includes generating an address for writing a data stream stored in the array, and further comprising the step of: Generating a second series of addresses which are sequentially applied to the random access memory array to read the data stream supplied from the memory array, and generating the second series. Providing a random access address for initializing a series of addresses applied in.

(17) In the method described in (13), the address and
Providing an offset value and adding the address offset value to a random access address to generate a second random access address.

(18) In the method described in the paragraph (13), a second random access address for initializing a series of addresses of a second face to be successively applied to the step of generating the series. Providing a method.

(19) In the method described in (13), the step of generating the sequence includes providing an increment step value;
Adding the increment step value to a current address from the series of addresses to generate a next address in the series of addresses.

(20) The memory circuit 14 has been described with features specifically configured so that the memory circuit 14 can act as a video frame memory. The memory circuit 14 has a dynamic random access memory array 24, with buffers 18 and 20 at its input and output data ports 22 for asynchronous reading, writing and writing to the memory array 24. Allow refresh access. The memory circuits 14 are accessed both serially and randomly. The address generator 28 has an address buffer register 36, which stores a random access address, and has an address sequencer 40, which is a memory
It provides a stream of addresses for array 24. The initial address for the address stream is the random access address stored in address buffer register 36.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a frame of a video display screen in which the present invention can be used, FIG. 2 is a block diagram of a memory circuit constructed according to the present invention, and FIG. 3 is a first diagram according to the present invention. FIG. 4 is a block diagram of an address generator of a memory circuit according to another embodiment, FIG. 4 is a block diagram of an address generator of a memory circuit according to a second alternative embodiment of the present invention, and FIG. FIG. 2 is a block diagram of an address sequencer used in an address generator of a memory circuit according to the present invention. Explanation of main codes 16a: Data input 18a: Serial latch 20a: Register 24: Memory array 36a: Address buffer register 40a: Address sequencer

 ──────────────────────────────────────────────────の Continuation of front page (72) Inventor Gene A. Franz, Point Clear Court, Missouri City, Texas, United States 2027 (72) Inventor John Victor Moravec, Hinlicker Drive, Willows Springs, Illinois, United States 212 (72) Inventor Jean-Pierre Dray, Villeneuve-Loubet, France, De Mein de Saint Andrew, France , 18 (56) References JP-A-59-180871 (JP, A) JP-A-62-146064 (JP, A)

Claims (8)

(57) [Claims] 1. A dynamic random access memory device comprising: A. a single chip integrated circuit; and B. a dynamic random access memory array formed on said chip, said array transmitting parallel data signals to said array. A plurality of array data leads carrying parallel address signals to said array.
An address read, one data signal represents one data bit, one address signal represents one address bit, and the array is configured at a plurality of addressable locations, each location comprising a plurality of addressable locations. And each location is randomly addressable by said address signal to write one word of data bits from said array data read to each addressed location. A dynamic random access memory array; C. a clock signal terminal formed on the chip for receiving a clock signal; D. an address generator formed on the chip;
The address generator includes a predetermined number of address terminals for receiving a parallel address signal from outside the chip, wherein the parallel address signal indicates an address of a random position in the array, and the address generator includes: An address generator, comprising: a register each latching an address bit equal to the number of address terminals; and E. coupled between the register and the array address read and coupled to the clock signal terminal. An address sequencer included in the address generator, the address sequencer receiving an address signal from the register and applying an address signal to the array address read to access an addressable location in the array. Address of a random location in the array supplied and received from the register. F. a data port formed on the chip and coupled to the array data read and the clock signal terminals, i. A plurality of data terminals for receiving a data signal in synchronization with the clock signal;
A plurality of data terminals representing two data words; ii. A write serial latch connected in series between the data terminal and the array data read, the write serial latch comprising: Synchronously latching the data word signal received at the data terminal in series, conveying the received data signal to the array data read, and placing the data signal at a random location indicated by the received address signal A dynamic random access memory device comprising: the write serial latch; and the write serial latch. 2. The memory device of claim 1, wherein the predetermined number of address terminals is eight, and the data port includes four data terminals and one register connected between a write serial latch and an array data lead. . 3. The memory device according to claim 1, wherein said address sequencer is a binary counter preset to an address included in said register. 4. The memory device of claim 1, wherein said address sequencer is a binary counter containing half of the address bits required to address the array and initialized to a clear state. 5. The memory device of claim 1, including a control strobe terminal that is activated as soon as a valid address signal occurs at the address terminal. 6. The memory device according to claim 1, wherein said address sequencer generates continuous addresses in synchronization with a clock signal. 7. A dynamic random access memory device comprising: A. a single chip integrated circuit; and B. a dynamic random access memory array formed on said chip, said array comprising parallel data from said array. A plurality of array data leads carrying signals and a plurality of parallel array address reads carrying parallel address signals to the array, wherein one data signal is one.
One address signal representing one data bit, one address signal representing one address bit, the array being configured at a plurality of addressable locations, each location comprising a data word of a plurality of data bits; Said dynamic random access memory array, wherein each location is randomly addressable by said address signal to read one word of data bits from each addressed location to said array data read; and C. on said chip A clock signal terminal for receiving a clock signal, and D. an address generator formed on the chip,
The address generator includes a predetermined number of address terminals for receiving a parallel address signal from outside the chip, wherein the parallel address signal indicates an address of a random position in the array, and the address generator includes: An address generator, comprising: a register each latching an address bit equal to the number of address terminals; and E. coupled between the register and the array address read and coupled to the clock signal terminal. An address sequencer included in the address generator, the address sequencer receiving an address signal from the register and applying an address signal to the array address read to access an addressable location in the array. Address of a random location in the array supplied and received from the register. And F. a data port formed on the chip and coupled to the array data read and the clock signal terminals, i. A plurality of data terminals for transmitting parallel data signals in synchronization with the clock signal, wherein each set of parallel data signals represents one data word; and ii. The data terminals and the array. A read serial latch connected in series between the data read and the data read, the read serial latch serially latches the data word signal received from the array data read and converts the received data signal The signal is transferred to a data terminal in synchronization with the clock signal, and the array is arranged at a random position indicated by the received address signal. Read data signal from said comprising a reading series latch, a dynamic random access memory device comprising, said data ports. 8. The memory device according to claim 1, wherein said address sequencer generates continuous addresses in synchronization with a clock signal.