JP2000149554A - Dynamic random access memory device, data-transferring system and data write method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain special effects of various kinds in a wide range by setting a plurality of array data signals and a plurality of parallel array address leads, addressing at random according to an address signal and providing an address sequencer between a register for latching an address bit and the array address lead. SOLUTION: A write address generator 28a and a read address generator 28b are constructed and operate in the same way. A random access address sequentially applies addresses to a control data terminal 34a, drives a control strobe signal applied to a terminal 38a when effective data appears to the terminal 34a, and loads the signal in series to an address buffer register 36a. After the signal is input to the address buffer register 36a, a write transfer signal is applied to a terminal 44a and transferred to a data sequencer 40a. External pins for constituting a memory circuit 14 are accordingly saved in number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to digital memory circuits, and more particularly to digital memory circuits that are particularly advantageous when used for video.

[0002]

BACKGROUND OF THE INVENTION Digital TV, VCR and related video applications often utilize a frame or field memory that stores pixels such that the entirety represents the entire video frame. The frame memory is used to generate various special effects such as frame fixation, zoom, pan, split screen monitor operation, and the like. The frame memory can be constructed using ordinary individual integrated circuits.

[0003]

These frame memories are relatively expensive, consume an undesirably large amount of power, and occupy an undesirably large amount of space. This is a major problem if the purpose of such a frame memory is to use it in commercial products. Thus, a single integrated circuit, alone or in combination with as few other integrated circuits as possible, would be an improvement over a frame memory constructed with ordinary discrete integrated circuits. .

Conventional integrated circuit devices have attempted to address this frame memory problem. However, these devices are
It was not possible to create an architecture that would adequately meet the demands for video. For example, in creating a wide variety of special effects, devices that include only the few frame memory functions typically required can be used. However, since it has to be combined with a large number of conventional individual integrated circuits, there is little improvement over a frame memory consisting only of conventional individual integrated circuits.

[0005] On the other hand, conventional frame memory integrated circuits may include random access memory with complete on-chip address calculations. In video applications utilizing such a frame memory, the entire frame memory is accessed serially. In this way, the special effects of frame fixed and split screen monitor operation are supported. However, zoom and pan functions are not possible or practical with such devices.

[0006] Accordingly, there is a need in the industry for a frame memory integrated circuit that optimizes the circuit architecture to provide a wide variety of special effects without requiring a large amount of surrounding integrated circuits.

[0007]

Accordingly, it is an advantage of the present invention to provide a frame memory circuit which allows limited random access. Thus, a device constructed in accordance with the present invention can be efficiently used for a wide variety of special effects video applications.

Another advantage of the present invention is that it provides a memory circuit that includes various address calculation modes. That is, a portion of the address calculation for a particular effect function can be transferred to a memory circuit, and in video applications utilizing this memory circuit, there is no need to allocate processing power to the calculation.

The advantages of the invention described above are, in one form, implemented by a memory circuit for storing and providing a data stream. This memory circuit enables both serial access and random access. The data input of the random access memory array is
Buffer, and this data buffer is
Enables the operation of the array to be synchronized with the data stream. The address input of the random access memory array is coupled to an address sequencer, which generates a series of memory addresses that are applied sequentially to the memory array. An address buffer register is also coupled to the address sequencer. When the address buffer register
Supply a random access address to the sequencer,
A series of memories supplied from the address sequencer
Initialize the address.

The invention will be better understood from the following detailed description of the drawings. Throughout the drawings, the same reference numerals are used for similar parts.

[0011]

FIG. 1 shows a video frame 10 as it appears on a picture tube or other video display terminal. Although frame 10 appears to the viewer as a continuous video image, frame 10 has a large number of digitized pixels 1
2 can be represented electrically. Each pixel 12
Defines parameters such as color and relative intensity for one of a number of very small areas in the image of frame 10. Accordingly, frame 10 may include a relatively large number of pixels 12. For example, a frame having 488 columns of pixels 12 and 488 rows of pixels 12 has a total of 238,144 pixels per frame.

Typically, pixels 12 are transmitted or otherwise processed in a predetermined order to preserve the spatial relationship between pixels 12. For example, in a typical raster scanning application,
Pixels 12 can be transmitted sequentially to a memory device or video display, starting with pixel 12a representing pixel 12 in the first column of the first row of frame 10, which is It continues in order up to pixel 12b representing pixel 12 in the last column. Immediately after transmitting the pixel 12b and the synchronization information (not shown), the pixel 12c representing the pixel 12 in the second row and the first column is transmitted,
Subsequently, the remaining pixels 12 in the second row of the frame 10 can be transmitted in sequence. The transmission of the pixels 12 continues in this manner until a pixel 12d representing the pixel 12 in the last column of the last row of the frame 10 has been transmitted. Therefore, any processing device that knows the timing relationship between pixel 12 and the first pixel 12a will be
Knowing the spatial position of the pixel 12 within the or can be easily calculated.

Digital TV, VCR, etc.
You may have a large frame or field memory that can store all the pixels 12 in zero. The combination of the pixels 12 is a serial data stream to the frame memory. Apart from the special effects, the relative order of the pixels 12 in this serial data stream is framed in order to preserve the spatial relationship of the pixels 12.
Generally must be observed when reading from memory.
However, the various special effects do not require the order to be preserved in this way, and when the pixel 12 is read from the frame memory,
Preserving the order of the pixels 12 can waste valuable computing time.

One such special effect is the zoom effect, which enlarges a small portion of a frame to fill the entire video display. For example, if the frame 10 of FIG. 1 represents the entire video display, the area of the frame 10 delimited by the rows i and j and the columns m and n is enlarged by the zoom special effect to fill the entire frame 10. Can be. Thus, in the zoom special effect, all pixels 12 in the frame 10 that are outside the area delimited by rows i and j and m and n have no effect and can be discarded. In other words, pixel 1 which does not work in this way
2 need not be stored in or read from the frame memory. Therefore, pixel 12 in column m and row i
Is used as the first pixel 12a of the zoom special effect. Valid pixels 12 can be overlapped to complete an entire row of frame 10, and rows can be overlapped to complete the vertical component of the zoom effect.

In the split screen special effect, frame 1
The whole 0 can be reduced to a small area of the screen, such as delimited by row j and last row of frame 10 and column n and last column of frame 10. To achieve this special effect, for each predetermined number of pixels 12 in the entire frame 10 of pixels 12, only one pixel 12 is used, and intermediate inactive pixels 12 are ignored (ie, skip pixels). ). In the example shown in FIG. 1, a reduced frame is formed using only pixels 12 from one for every three columns of the frame 10 and one for every three rows.

The present invention provides a memory circuit which functions as a frame memory and can efficiently implement the above and other special effects. FIG.
Is a block diagram of a memory circuit 14 configured according to the present invention. Generally, the memory circuit 1 of the preferred embodiment
4 represents a single-chip integrated circuit having 2 ²⁰ , or 1,048,576 bits of stored content, organized as 262,144 4-bit wide words. Thus, a sufficient amount of words is provided for buffering or storing the entire 488 × 488 frame of pixels 12 (see FIG. 1). If more than four bits of precision are required to accurately describe each pixel, additional memory circuitry 14 can be used to store such extra bits.

The memory circuit 14 generally has a serial access mode.
Mode, but on a limited scale, the memory circuit 14
It has a special feature that allows for random access. Those skilled in the art will appreciate that serial access refers to a data storage and read mode in which data must be read from memory in the same order as the data was stored in memory. Further, random access refers to the ability to write, read, or otherwise access any location in the memory array by providing a unique address corresponding to that memory location.

Specifically, memory circuit 14 has a serial pixel data input 16a, which in the preferred embodiment, provides four bits of data. Serial pixel data input 1
6a is coupled to the input port of write serial latch 18a, and the output port of write serial latch 18a is coupled to the input port of write register 20a. The output port of write register 20a is coupled to data input port 22a of memory array 24. In the preferred embodiment, memory array 24 is a dynamic random access memory (DRAM) array having 2 ¹⁸ or 262,144 4-bit memory locations. Data output port 22b of memory array 24 is coupled to the data input port of read register 20b, and the data output port of read register 20b is coupled to the data input port of read serial latch 18b. The data output port of read serial latch 18b is coupled to serial pixel data output 16b, which, in the preferred embodiment, provides four bits of data.

A serial write clock terminal 26a is coupled to the write address generator 28a, the arbitration and control circuit 30, and the clock input of the write serial latch 18a. Similarly, the serial read clock terminal 26b is connected to the read address generator 28b, the arbitration and control circuit 30, and the read serial latch 1
8b is coupled to the clock input. The output of the refresh address and timing circuit 32 is coupled to the input of the arbitration and control circuit 30, and the output of the arbitration and control circuit 30 is the clock input of the write register 20a, the clock input of the read register 20b, and the control of the memory array 24. Input and to the address input of the memory array 24.

As shown in FIG. 2, address generators 28a and 28b are structurally similar to each other in the preferred embodiment. That is, the write control data terminal 34a is connected to the address buffer register 3 in the write address generator 28a.
6a is coupled to the serial data input. Read control data terminal 34b is coupled to the serial data input of address buffer register 36b in read address generator 28b. Similarly, write control strobe terminal 38a is coupled to the clock input of address buffer register 36a, and read control strobe terminal 38b is coupled to the clock input of address buffer register 36b. The data output of address buffer register 36a is coupled to the data input of address sequencer 40a, and the data output of address buffer register 36b is coupled to the data input of address sequencer 40b.

A write reset terminal 42a is coupled to a clear input of address sequencer 40a, and a write transfer terminal 44a is coupled to a preset input of address sequencer 40a. The read reset terminal 42b is
The read transfer terminal 44b is coupled to the clear input of the sequencer 40b and the preset transfer input of the address sequencer 40b. Terminal 26a is coupled to the clock input of address sequencer 40a in address generator 28a, and terminal 26b is connected to the address input in address generator 28b.
It is coupled to the clock input of sequencer 40b. The output (46a) of the address sequencer 40a produces an output signal from the address generator 28a, and the arbitration and control circuit 30
To the input of Similarly, address sequencer 4
The output of Ob (46b) provides an output signal from address generator 20b and is coupled to arbitration and control circuit 30. The memory circuit 14 can be provided in a 20-pin integrated circuit package.

As previously mentioned, the memory circuit 14 can operate in either a serial access mode or a limited random access mode. Further, storage or writing of data to the memory circuit 14 is performed by the memory circuit 1
4 can be performed asynchronously with the reading or supply of data. By activating the write reset signal at the terminal 42a to clear the address sequencer 40a, it is possible to write data in the memory circuit 14 in series.

Thereafter, a 4-bit wide serial data stream can be stored in the memory circuit 14 by applying a 4-bit data nibble to the data input 16a while issuing a serial write clock signal at the terminal 26a. . Once the serial write clock signal is issued, write serial latch 18a temporarily stores or buffers one 4-bit data nibble. Write serial latch 18a acts as a 4-bit wide shift register. Thus, the subsequent 4-bit nibble of the serial pixel data stream applied to the data input 16a will cause the serial latch 2
Shift to 8a.

Further, each time a serial write clock signal is issued, the address sequencer 40a of the write address generator 28a supplies a new random access address to the arbitration and control circuit 30. In other words, address sequencer 40a provides a stream of addresses corresponding to the data stream stored in write serial latch 18a to arbitration and control circuit 30.

The arbitration and control circuit 30 uses the address generator 2
8a to 28b and the address is received from the refresh address and timing circuit 32. Circuit 30 monitors these inputs and various timing signals to determine which addresses provided to these inputs should be transferred to memory array 24. The arbitration and control circuit 30
It includes ordinary logic circuits that control the timing operation of the dynamic memories that make up memory array 24. That is, the arbitration and control circuit 30 uses the address generator 28
a to the memory array 24 so that data can be written to the memory array 24, but a delay occurs due to a refresh operation or read access of the memory array 24. There is.

Accordingly, the arbitration and control circuit 30 also has storage, so that when immediate access to the memory array 24 is prevented, the address generators 28a-2
8b so that the address generated by it is not lost. When the arbitration and control circuit 30 determines when serial pixel data can be written to the memory array 24, the data is transferred from the write serial latch 18a to the write register 20a and then written to the memory array 24. It is. Therefore, the combination of the write serial latch 18a and the write register 20a is of a double buffer system, so that the memory array 24 can operate asynchronously with respect to the storage of serial pixel data in the memory circuit 14.

Reading data from memory array 24 is performed in a manner similar to that described above for storing data in memory array 24. That is, the address generator 2
8b is transferred at an appropriate time through the arbitration and control circuit 30 to the memory array 2
4 is read into the read register 20b. This data is then transferred to read serial latch 18b so that it can be generated at data output terminal 16b by applying a serial read clock signal to terminal 26b. The generation of serial data at output terminal 16b is asynchronous with respect to the operation of memory array 24, and is also asynchronous with respect to storing serial pixel data in memory circuit 14 from terminal 16a. .

The limited random access features of the memory circuit 14 are obtained by the address generators 28a-28b. In the memory circuit 14 of the embodiment shown in FIG. 2, the write address generator 28a and the read address generator 28b
Has the same structure and operation except that the write address generator 28a generates a write address while the read address generator 28b generates a read address. Therefore, both address generators 28a-28b
In the following, only the write address generator 28a will be described. Those skilled in the art will recognize that the preferred embodiment operates the read address generator 28b in a similar manner.

As for the random access address, this address is successively applied to the control data terminal 34a, and the terminal 3
When valid data appears on 4a, the address buffer register 36a can be serially loaded by activating the control strobe signal applied to terminal 38a. For this reason, in the embodiment shown in FIG.
Buffer register 36a represents a serial shift register. The use of a serial shift register saves the number of external pins required to configure the memory circuit 14 on an integrated circuit, as compared to a parallel load register. Random access
After the address is input to the address buffer register 36a, it can be transferred to the data sequencer 40a by applying a write transfer signal to terminal 44a.

In the preferred embodiment of the present invention, address sequencer 40a may represent a presettable binary counter or other presettable sequence circuit. That is, the transferred address begins a series of addresses subsequently generated by the address generator 28a. If address sea sensor 40a is a binary counter, subsequent addresses increment or decrement, starting from this preset value.

The memory array 24 2 ¹⁸ pieces of 4-bit
When storing words, address buffer register 36a is advantageously an 18-bit register, and address sequencer 40a may be an 18-bit counter or other sequence circuit. On the other hand, the address buffer register 36a and the address sequencer 40a may have a smaller number of bits, for example, 9 bits. In the case of 9 bits, the random access address supplied from address buffer register 36a accesses the beginning of a memory page or row if each page or row stores 2 ⁹ , or 512 words. be able to.

By providing limited random access characteristics including the address buffer register 36a, the memory circuit 14 can be efficiently used with a special zoom effect. For example, a zoom effect can be achieved by writing an entire memory frame to the memory array 24 using a serial access mode.
A starting pixel address, such as the pixel address in row i column m of FIG. 1, can be loaded into read address buffer register 36b and transferred to address sequencer 40b. The first row, e.g., row i, of the portion of the frame 10 that is to be expanded to the entire frame is stored in serial or sequential mode until the pixel corresponding to, e.g., row i, column n appears at output terminal 16b. It can be read from the array 24. Address buffer register 36b
Is transferred to the address sequencer 40b, so that a certain number of rows can be repeated as many times as necessary to perform the vertical zoom operation.

Thereafter, the address corresponding to the pixel at row (i + 1) and column m is stored in the address buffer register 3.
6b and transferred to the address sequencer 40b. This process is continued until the last pixel of the frame to be enlarged is output from the memory array 24. Due to this feature, the video device may have a pixel 12a
It is not necessary to start accessing the memory circuit 14 from the first address (as shown in FIG. 1) to access the unused pixels described in the memory array 24.
As a result, the operation becomes faster.

In the present invention, another embodiment of the address generators 28a to 28b is also conceivable. In a first alternative embodiment, address generators 28a-28b are shown in FIG. FIG. 3 shows only one address generator 28. FIG.
The address generator 28 shown in FIG.
a or read generator 28b (see FIG. 2).

In the address generator 28 of the first alternative embodiment, the address buffer register 36 can be loaded either serially or in parallel. That is, the control data terminal 34 may represent either the write control data terminal 34a or the read control data terminal 34b as described above with reference to FIG. Is combined with The control strobe terminal 38 is connected to the serial clock input of the address buffer register 36 and the address offset register 48.
To the serial clock input. The parallel data output of address buffer register 36 is coupled to a first input of adder 50 and a data input of address sequencer 40.

The parallel data output of address offset register 46 is coupled to a second input of adder 50.
The output of the adder 50 is the address buffer register 36.
Transfer terminal 44 is coupled to a parallel clock input of address buffer 36 and to a preset input of address sequencer 40. address·
The most significant bit of the parallel data output or serial output bit of buffer register 36 is coupled to the serial data input of address offset register 48. Serial clock terminal 26 is coupled to the clock input of address sequencer 40, and reset terminal 42 is coupled to the clear input of address sequencer 40. The data output of address sequencer 40 is coupled to output 46 of the address generator.

In this alternative first embodiment, the address buffer register 36 and the address sequencer 40
Operates in a manner similar to that described above for address generators 28a-28b in FIG. However, in this first alternative embodiment, using the control data supplied to terminal 34,
Load both address buffer register 36 and address offset register 48. Thus, extra bits of control data are loaded into memory circuit 14 without the need for extra integrated circuit pins. Further, the most significant bit or serial output bit 51 from the address offset register 48 can advantageously be sent to the control data input for the other of the read and write address generators 28a and 28b (see FIG. 1). It is. Further, the control strobe signal applied to terminal 38 can be sent to the other of control strobe terminals 38a and 38b in FIG. This two connection between address generators 28a and 28b eliminates two integrated circuit pins from the structure shown in FIG.

In the first alternative embodiment just described of the present invention, the control data contained in the address offset register 48 is added to the value of the current initial address contained in the address buffer register 36. The new random access address value for initialization. The value for this new initial setting is the address sequencer 40
Is loaded into the address buffer register 36 when the value of the current address is transferred to the address buffer register 36.

Still referring to FIG. 1, this first alternative embodiment of the present invention may be advantageous, for example, when implementing zoom special effects. That is, the address offset value loaded into the address offset register 48 may represent the amount of unused pixels that occur between column n of one row and column m of the next row. At the end of each row of the frame, a transfer signal is output at terminal 44, and the random access address of the next pixel to be used, corresponding to column n of the next row, is automatically calculated and the address buffer
Stored in register 36 to initiate another series of sequential accesses of memory circuit 14. Video devices that use memory circuit 14 are less complicated because components external to memory circuit 14 do not need to calculate this address.

The address generators 28a to 28 shown in FIG.
Another second embodiment of b is shown in FIG. The embodiment of FIG. 4 shows that the random access address can be loaded into the address buffer register 36 in a parallel manner, which is more compatible with ordinary microprocessor integrated circuits. is there. However, the number of integrated circuit pins required to implement this embodiment is different from that of FIG.
3 and the embodiment described with reference to FIG.

FIG. 4 also shows that in addition to the address buffer register 36, an alternate address buffer register 52 is included. In particular, control data terminal 34 advantageously provides an 8-bit microprocessor data bus which provides a separate 8-bit portion 54 of address buffer register 36.
a, 54b, 54c. Furthermore,
Control data terminal 34 is a separate 8-bit portion 56a, 56b, 56 of alternate address buffer register 52.
c to the data input. Individual parts 54a-5
4c together form a 24-bit bus, which is coupled to the first data input of multiplexer 58.

Similarly, the data outputs of the individual portions 56a-56c form a 24-bit bus, which is coupled to the second data input of multiplexer 58. The data output of multiplexer 58 is coupled to the data input of a binary counter that acts as address sequencer 40 in this second alternative embodiment. Of course, those skilled in the art will recognize that the address buffer register 36 and the alternate address
The number of subregisters included in buffer register 52,
It will be apparent that the number of bits in the bus described above can vary significantly depending on the requirements of the particular application.

Further, microprocessor address input terminals 60a, 60b, 60c are coupled to the address input of decoder 62 and address input terminal 60d is connected to decoder 62.
To the impossible input. The previously described control strobe terminal 38 is coupled to the disable input of decoder 62. The outputs 01-06 of the decoder 62 are the clock inputs of the separate portions 54a-54c of the address buffer registers and the separate portions 56a of the alternate address buffer registers.
-56c, respectively. Output 07 of decoder 62 is coupled to the clock input of flip-flop 64.

The flip-flop is configured to toggle when the clock input is activated. The output of flip-flop 64 is coupled to a select input of multiplexer 58. Output 08 of decoder 62 is coupled to a preset input of binary counter 40. Serial clock 26
Is coupled to the clock input of the binary counter 40 and the reset terminal 42 is connected to the clear input of the flip-flop 64 and 2
Tied to the clear input of hex counter 40. The output of the binary counter 40 is coupled to the output 46 of the address generator 28.

In the address generator 28 of the second embodiment, one random access address for initial setting can be stored in the address register 36.
The alternate random access address for initialization is stored in the alternate address buffer register 52. A microprocessor (not shown) storing these addresses in memory circuit 14 through normal memory operations or I / O write operations to the addresses specified by the signals applied to terminals 60a-60c. Can be. Advantageously, the address input bits applied to terminal 60d can distinguish between write address generator 28a and read address generator 28b (see FIG. 1).

By applying an operation signal to the reset terminal 42, the flip-flop 64 and the binary counter 40
Can be initialized to a clear state. In this regard,
Address generator 28 operates in much the same manner as described above with respect to FIG. However, the alternate random access address stored in the alternate address buffer 52 can selectively preset the binary counter 40. An alternate random access address is preset in the binary counter 40 by a microprocessor write operation for causing the flip-flop 54 to perform a toggle operation and a subsequent microprocessor write operation for transferring data to the binary counter 40. You. Flip-flop 64 can perform a toggle operation by performing a write operation to an address that activates output 07 of decoder 62. By writing to the address that activates the output 08 of the decoder 62, a transfer operation from the selected one of the address buffer registers 36, 52 is performed.

Alternate Address Buffer Register 5
2 can be advantageously used by video equipment to efficiently buffer certain lines in a data frame. The memory circuit 14 of the preferred embodiment comprises 2 ¹⁸ ,
That is, because the memory circuit 14 has a memory large enough to accommodate 262,144 pixels, the memory circuit 14 may include, for example, one data frame having a column of 480 pixels and a row of 480 pixels. Has unused memory locations when used to store. Thus, a random access address in this unused portion of memory can be loaded into the alternate address buffer register 52. This alternate address value is transferred to a binary counter 40, and then the pixels on this line are sequentially stored in unused portions of the memory circuit 14 to provide one line for a frame. Can be efficiently stored in the memory circuit 14.

Further, the present invention contemplates other embodiments of the address sequencer 40. As shown in FIG.
The address sequencer 40 is a normal presettable,
It may represent a clear binary counter.
These circuits are well known and need not be described at length here. However, alternatively, the address sequencer 40 may represent a circuit that increments or decrements by a variable step value that may be different from a value of one. Such a circuit is shown in FIG.

That is, in FIG. 5, the data input of the address sequencer is coupled to a first input of a multiplexer 66, and the preset terminal of the address sequencer is coupled to a select input of the multiplexer 66. Multiplexer 6
6 is coupled to the data input of register 68, and the clock input of address sequencer 40 is coupled to the clock input of register 68. Similarly, the reset terminal 42
Is coupled to the clear input of register 68. Register 6
The data output of 8 becomes the data output of address sequencer 40 and is further coupled to a first input of adder 70.
The output of adder 70 is coupled to a second input of multiplexer 66. Control data terminal 34, previously described with respect to FIGS. 2-4, is coupled to the data input of register 72. In addition, the control strobe terminal 38 previously described with respect to FIGS. 2-4 is coupled to the clock input of the register 72. The data output of the register 72 is
To the input of

In the address sequencer 40 of the embodiment shown in FIG. 5, the register 72 may be either a parallel or a serially loaded register as previously described with respect to FIGS. Further, if register 72 is a serially loaded register, then register 72 is one of a number of registers coupled in a long chain of serially loaded registers, as previously described with respect to FIG. good. The data loaded into the register 72 includes an address
This represents an increment step when the sequencer 40 generates successive addresses on the output 46 of the address generator 28.

The current output of the address sequencer 40 is added to the increment value of this step by an adder 70,
Is returned to. Thus, the subsequent address generated by address sequencer 40 is equal to the previous address plus the address step increment contained in register 72. This address step increment need not be equal to a value of one, but may be equal to any positive or negative value. In addition, register 7
2, adder 70, multiplexer 66 and register 68
Are greater than the number of bits at the output of the address sequencer 40, subsequent addresses can be incremented by a fraction of a step.

An operation signal is applied to the preset terminal, data is supplied to the data input terminal, and the address sequencer 4
By issuing a zero clock signal, the address sequencer 40 can preset or initialize a random access address. That is, the random access value for the initial setting is directly loaded into the register 68. Further, by applying a reset signal to the clear input terminal, the address sequencer 4
0 can be cleared or reset.

Still referring to FIG. 1, the address sequencer 40 shown in FIG. 5 has a split screen specialty such that the entire frame is displayed on only a small portion of the video screen, as shown in the lower right portion of FIG. Useful when implementing effects. In this special effect, when all the pixels 12 of the frame 10 are stored in the memory circuit 14, only one pixel acts on each group of a predetermined number of storage pixels when forming a reduced screen. The address shown in FIG.
The sequencer 40 supplies a series of addresses that omit unused pixel addresses so that the memory circuit 14 can supply only valid pixels.

In summary, the present invention has provided a memory circuit that allows a video device to efficiently implement special effects. In particular, by incorporating various limited random access features, the memory circuit 14
Can store and / or supply only valid pixels for certain special effects, and not store or supply unused pixels. Thus, valid pixels can be recovered from memory circuit 14 faster than if a conventional frame memory circuit were used.

What has been described above uses preferred embodiments to illustrate the invention. However, those skilled in the art will recognize that various modifications can be made to these embodiments without departing from the scope of the present invention. For example, read address generator 28b need not be exactly the same as write address generator 28a. Further, while the embodiments shown in FIGS. 3-5 have been described above as alternative embodiments, those skilled in the art will recognize that two or more of these embodiments may be implemented in one frame memory circuit 14. It does not preclude combining with.

Further, those skilled in the art will recognize that additional address processing capabilities can be incorporated into the frame memory circuit 14. Such additional address processing capabilities include a signal indicating the end of a line in a frame, a signal indicating the end of a frame, and automatic generation of a random access address to an address sequencer when an end of line and end of frame signal occurs. Forwarding can be included. Additionally, while specific frame and memory array dimensions have been described above to aid in understanding the invention, it should be understood that the invention is not limited to any particular dimensions. It is to be understood that all such modifications apparent to those skilled in the art are included within the scope of the present invention.

In connection with the above description, the following items are further disclosed. (1) A memory circuit for storing and supplying a data stream capable of performing both serial access and random access, comprising: a random access memory array having an address input and a data port; A data buffer coupled to a data port of the array, the data buffer synchronizing the operation of the memory array with a data stream, and a data input; and an address input to the memory array. An address sequencer having a coupled output for generating a sequence of memory addresses to be sequentially applied to the memory array, and an output coupled to a data input of the address sequencer; The address
An address buffer register that supplies a random access address that initializes the series of memory addresses generated by the sequencer.

(2) The memory circuit according to item (1), wherein the address buffer register is a serial load shift register.

(3) In the memory circuit described in (1), the memory circuit is further connected to an address sequencer.
A memory circuit having a terminal adapted to receive a signal for causing an address sequencer to transfer data contained in an address buffer register.

(4) The memory circuit according to (1), wherein the memory array, the data buffer, the address sequencer and the address buffer register are contained in one integrated circuit.

(5) In the memory circuit described in (1), the address sequencer is a binary counter, the data input is coupled to the output of the address buffer register, and the output is stored in the memory array. Memory circuit coupled to the address input.

(6) In the memory circuit described in (1), the address sequencer acts as a data input coupled to a node acting as a data input of the address sequencer and as an output of the address sequencer. A first register having an output, a second register having an output, and storing a value of an increment step;
An adder having a first input coupled to the output of the first register, a second input coupled to the output of the second register, and an output coupled to a data input of the first register. The configured memory circuit.

(7) In the memory circuit described in (1), the data buffer controls the operation of the memory array.
The address sequencer synchronizes with the data stream stored in the memory array,
Generating a memory address for writing a stream to a memory array; and further comprising a memory circuit having a data port coupled to the data port of the memory array for providing operation of the memory array from the memory circuit. A second data buffer for synchronizing with the data stream to be read, and an output and a data input coupled to the address input of the memory array, for reading the data stream provided by the memory array; A second address sequencer for generating a series of memory addresses to be applied to the memory array; and an output coupled to the data input of the second address generator, the second address sequencer having a second address sequencer. A series of memory generated
A second address buffer register for supplying a random access address for initializing the address.

(8) In the memory circuit described in the item (1), the output further includes an address offset register for storing address offset data and an output of the address buffer register. A random access address having a first input associated therewith, a second input coupled to an output of the address offset register, and an output coupled to a data input of the address buffer register And the address
Random access representing the sum with offset data
A memory circuit having an adder for generating an address.

(9) In the memory circuit described in (1), the memory circuit has an alternate address buffer register having an output coupled to the data input of the address sequencer, and is generated by the address sequencer. A memory circuit for generating an alternate random access address for initializing an alternate series of memory addresses.

(10) In an integrated memory circuit capable of serial access and limited random access and storing and supplying a data stream, a random memory having an address input, a data input port and a data output port. An access memory array;
A first data buffer having a data port coupled to the data input port of the array for synchronizing operation of the memory array with the stored data stream; and a first data buffer coupled to the data output port of the memory array. A second data buffer having a data port for synchronizing operation of the memory array with the supplied data stream, and a first address generator for storing the data stream stored in the memory array. A second address generator generates an address used to write the
First and second address generators for generating addresses used to read the data stream provided by the array, each of the first and second address generators having a memory A binary counter for counting memory addresses applied to the memory array having an output coupled to an address input of the array and having an output coupled to a data input of the binary counter. An integrated memory circuit comprising a serially loaded address buffer register for providing an initial random access memory address that causes the binary counter to start counting.

(11) In the integrated memory circuit as described in the item (10), each of the first and second address generators further has an output and stores the address offset data. An address offset register, a first input coupled to the output of the address buffer register, a second input coupled to the output of the address offset register, and an output coupled to the data input of the address buffer register An integrated memory circuit having an adder coupled and providing a sum of a previous random access address and address offset data to an address buffer register.

(12) In the integrated memory circuit as described in (10), each of the first and second address generators has an output coupled to a data input of a binary counter, and An integrated memory circuit having an alternate address buffer register for providing an alternate initial random access memory address counted by a hexadecimal counter.

(13) In a method of storing and supplying data memory using a random access memory array, the data stream stored and supplied asynchronously with respect to the operation of the memory array is provided. Buffering a data stream into and out of the memory array as it occurs, generating a random access address, and a series of bits initialized by the random access address. Generating an address, said address being sequentially applied to a random access memory array.

(14) In the method described in the above mode (13), the step of generating a random access address includes:
A method comprising serial loading a random access address into a register.

(15) In the method described in (13), the step of generating a sequence includes generating an address to be successively applied to the random access memory array, thereby generating an address to be sequentially applied to the random access memory array. A method comprising counting successive data items.

(16) In the method described in (13), the step of generating a sequence includes generating an address for writing a data stream stored in the array, and further generating the address from the memory array. Generating a second series of addresses that are applied sequentially to the random access memory array to read the data stream to be supplied;
The method of generating a series of steps further comprising: providing a random access address for initializing a series of sequentially applied addresses.

(17) In the method described in (13), the address offset value is supplied, and the address
Adding an offset value to the random access address to generate a second random access address.

(18) In the method described in the item (13), a second address for initializing a series of addresses of the second face to be successively applied to the step of generating the series.
Providing a random access address for the device.

(19) In the method described in (13), the step of generating a sequence includes providing an increment step value, and incrementing the increment step value from the address sequence. Add to the current address,
Generating a next address in said series of addresses.

(20) A description has been given of a memory circuit 14 having features specially configured so that the memory circuit 14 can act as a video frame memory. The memory circuit 14 includes a dynamic random access memory
Having an array 24 and its input and output data ports 2
2 have buffers 18 and 20 and a memory array 24
Allows asynchronous read, write and refresh access to The memory circuit 14 can also be connected in series,
Also accessed randomly. The address generator 28 has an address buffer register 36, which stores the random access address, and has an address sequencer 40, which stores the memory array 24.
To provide a stream of addresses for The initial address for the stream of addresses is the random access address stored in the address buffer register 36.
Address.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a frame of a video display screen in which the present invention can be used.

FIG. 2 is a block diagram of a memory circuit configured according to the present invention.

FIG. 3 is a block diagram of a part of an address generator of a memory circuit according to a first different embodiment of the present invention;

FIG. 4 is a block diagram of a part of an address generator of a memory circuit according to a second different embodiment of the present invention;

FIG. 5 is a block diagram of an address sequencer used in an address generator of a memory circuit according to the present invention.

[Explanation of symbols]

 16a Data input 18a Serial latch 20a Register 24 Memory array 36a Address buffer register 40a Address sequencer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/00 550 H04N 5/907 B H04N 5/907 G06F 15/64 450C (72) Inventor John Victor Moravec Hinlicker Drive, Willow Springs, Illinois, USA 212 (72) Inventor Jean-Pierre Dray Villeneuve-Loubet, France, Domaine de Saint Andrew, 18

Claims (12)

[Claims] 1. A dynamic random access memory device, comprising: B. a single-chip integrated circuit; A dynamic random access memory array formed on the chip, the array comprising a plurality of array data leads carrying parallel data signals to the array;
A plurality of parallel array address reads carrying a parallel address signal to the array, wherein one data signal represents one data bit, one address signal represents one address bit, and the array comprises a plurality of Each address location comprising a data word comprising a plurality of data bits, each location comprising one word of data bits from the array data read; B. said dynamic random access memory array being randomly addressable by said address signal to write to said memory array; D. a clock signal terminal formed on said chip for receiving a clock signal; An address generator formed on the chip, the address generator including a predetermined number of address terminals for receiving a parallel address signal from outside the chip,
The parallel address signal occurs in a plurality of groups separated in time and is received when the clock signal terminal receives a clock signal, the parallel address signal indicating an address of a random location in the array; The address generator includes registers that each latch address bits equal to the number of the predetermined number of address terminals,
E. said address generator; An address sequencer coupled between the register and the array address read and coupled to the clock signal terminal, the address sequencer comprising:
Receiving an address signal from the register and supplying an address signal to the array address read to access an addressable location in the array, starting from an address at a random location in the array received from the register B. said address sequencer for generating a continuous address through the address to be addressed; The array, formed on the chip;
A data port connected to a data lead and the clock signal terminal; A plurality of data terminals for receiving a parallel data signal in synchronization with the clock signal, wherein each set of parallel data signals represents one data word; A write serial latch connected in series between the data terminal and the array data read, the write serial latch serially receives the data word signal received at the data terminal in synchronization with the clock signal; Latching the received data signal to the array data read and writing a data signal to a random location indicated by the received address signal; and a write serial latch. A port; A control data buffer connected to the plurality of address terminals and the address sequencer, the control data buffer receiving an address control data signal from the address terminal to control the address generated from the address sequencer; , Consisting of a dynamic random access memory device. 2. The memory device of claim 1, wherein said control data buffer includes an address offset buffer for receiving an address offset value to be added to an address received at an address generator. 3. The memory device of claim 1, wherein the control data buffer includes a register for receiving an increment step value to be added to a previous address generated by the address sequencer to obtain a next address from the address sequencer. 4. A dynamic random access memory device, comprising: B. a single-chip integrated circuit; A dynamic random access memory array formed on the chip, the array comprising a plurality of array data leads carrying parallel data signals to and from the array, and a plurality of parallel data leads carrying parallel address signals to the array. An array address read, wherein one data signal represents one data bit, one address signal represents one address bit, and the array is configured at a plurality of addressable locations, each location comprising: Contains one data word consisting of a plurality of data bits, and each location has
B. said dynamic random access memory array being randomly addressable by said address signal to read and write one word of data bits from said array data read to each addressed location; D. a first clock signal terminal formed on said chip and receiving a first clock signal; B. a second clock signal terminal formed on said chip for receiving a second clock signal; An address generator formed on the chip, the address generator including a predetermined number of address terminals for receiving a parallel address signal from outside the chip,
The parallel address signals occur in a plurality of temporally separated groups, and are received while the first and second clock signal terminals receive first and second clock signals, wherein the address terminals comprise the array. B. said address generator coupled to an address read, said parallel address signal indicating an address of a random location in said array; G. a plurality of data terminals formed on said chip for transmitting and receiving parallel data signals, wherein each set of parallel data signals represents one data word; An input data port formed on the chip, and coupling the plurality of data terminals to the array data lead, for writing the data signal to the array at random locations indicated by the address signal;
H. said input data port receiving said parallel data signal in synchronization with said first clock signal; The array, formed on the chip;
An output data port for coupling a data read to the plurality of data terminals, wherein the data signal is read from the array at a random position indicated by the address signal, so that the parallel data is synchronized with the second clock signal. The output data port for sending a signal. 5. A data transfer system, comprising: A processor including an address generator, the address generator including a predetermined number of address terminals for sending a parallel address signal outside the processor, wherein the parallel address signal is generated in a plurality of temporally separated groups. B. said processor, wherein said parallel address signal indicates an address of a random location in memory; A dynamic random access memory device;
Wherein the dynamic random access memory device comprises: A single-chip integrated circuit; A dynamic random access memory array formed on the chip, the array comprising a plurality of array data leads carrying parallel data signals to the array and a plurality of array address leads carrying parallel address signals to the array. Wherein one data signal represents one data bit, one address signal represents one address bit, and the array is configured at a plurality of addressable locations, each location comprising a plurality of data bits. A data word consisting of bits and each location is
Said dynamic random access memory array being randomly addressable by said address signal to write one word of data bits from a data read to each addressed location; A clock signal terminal formed on the chip for receiving a clock signal; An address generator formed on the chip,
The address generator is coupled to the predetermined number of address terminals of the processor and includes a predetermined number of address terminals for receiving a parallel address signal from the processor, wherein the parallel address signal is a plurality of temporally separated signals. Occurring in a group and received when the clock signal terminal receives a clock signal, wherein the parallel address signal indicates an address of a random location in the array;
The address generator including registers that each latch address bits equal to the number of the predetermined number of address terminals; An address sequencer coupled between the register and the array address read and coupled to the clock signal terminal, the address sequencer receiving an address signal from the register and addressable in the array. Array to access different locations
Said address sequencer providing an address signal to an address read and generating a continuous address through addresses starting from an address at a random position in said array received from said register; A data port formed on the chip and connected to the array data lead and the clock signal terminal, a. A plurality of data terminals for receiving a parallel data signal in synchronization with the clock signal, wherein each set of parallel data signals represents one data word; b. A write serial latch connected in series between the data terminal and the array data read, the write serial latch serially receives the data word signal received at the data terminal in synchronization with the clock signal; Latching the received data signal to the array data read and writing a data signal to a random location indicated by the received address signal; and a write serial latch. A data transfer system comprising: a port; 6. A data system, comprising: A dynamic random access memory device, comprising: A single-chip integrated circuit; A dynamic random access memory array formed on the chip, the array comprising a plurality of array data leads carrying parallel data signals to the array, and a plurality of parallel arrays carrying parallel address signals to the array.
An address read, one data signal represents one data bit, one address signal represents one address bit, and the array is configured at a plurality of addressable locations, each location comprising a plurality of addressable locations. And each location is randomly addressable by said address signal to write one word of data bits from said array data read to each addressed location. Said dynamic random access memory array; A clock signal terminal formed on the chip for receiving a clock signal; An address generator formed on the chip,
The address generator includes a predetermined number of address terminals for receiving a parallel address signal from outside the chip, wherein the parallel address signal is received when the clock signal terminal receives a clock signal, and wherein the parallel address signal is Indicating the address of a random location in the array,
Said address generator; An address sequencer coupled between the address generator and the array address read and coupled to the clock signal terminal, the address sequencer receiving an address signal from the register and Supplying an address signal to the array address read to access an addressable location, and generating addresses sequentially through addresses starting from random addresses in the array received from the address generator; Said address sequencer; A data port formed on the chip and connected to the array data lead and the clock signal terminal, a. A plurality of data terminals receiving a parallel data signal in synchronization with the clock signal, wherein each set of parallel data signals represents one data word; b. A write serial latch connected in series between the data terminal and the array data read, wherein the write serial latch serially receives the data word signal received at the data terminal in synchronization with the clock signal; Latching the received data signal to the array data read and writing the data signal to a random location indicated by the received address signal; and a write serial latch. When, . A control data buffer connected to the predetermined number of address terminals and the address sequencer, the control data buffer receiving an address control data signal from the address terminals to control the address generated from the address sequencer; B. said dynamic random access memory device, comprising: B. A processor including an address generator, the address generator including a predetermined number of address terminals for sending a parallel address signal outside the processor, wherein the parallel address signal is generated in a plurality of temporally separated groups. The parallel address signal indicates an address of a random position in a memory, and the processor sends an address control data signal for controlling the address generated from the address sequencer to an address terminal of the memory device. , A data system comprising: the processor; 7. A transfer system for transferring a data stream, comprising: A memory device, comprising: A random access memory array storing one data word in each of a plurality of addressable locations; A data port having a plurality of data terminals for directing the data stream, wherein the data terminal is coupled to a data buffer such that the data stream occurs asynchronously with the operation of the memory array; Coupling said data to said memory array; said data port; An address generator having a number of address terminals less than the number of data terminals, the number of address terminals coupled to an address sequencer for receiving address control data including a first random access address; A. A sequencer for coupling data to the memory array for transferring data to and from the memory array, the sequence of addresses beginning with the first random access address to the memory array; and b. B. a processor for supplying said address control data to said memory device; A number of conductors equal to the number of address terminals, the plurality of conductors coupling the address control data from the processor to the memory device and connected to the address terminals. . 8. The address generator according to claim 7, wherein the address generator has another address buffer register for receiving address control data in the form of a new starting random access address while the address sequencer combines the series of addresses into the memory array. System. 9. The address generator according to claim 7, wherein the address generator has an address offset register for receiving address control data in the form of a series of address generating address offset steps while the address sequencer couples the series of addresses to the memory array. The described system. 10. A method for synchronously writing data to a dynamic random access memory array formed on a chip, the array comprising: a plurality of array data reads carrying parallel data signals to the array; A plurality of parallel array address reads carrying a parallel address signal to the array, one data signal representing one data bit, one address signal representing one address bit, and the array comprising a plurality of addresses. Configured at possible locations, each location including one data word of a plurality of data bits, and each location including one word of data bits from the array data read at each addressed location. The method of writing, wherein the address is randomly addressable by the address signal for writing. Applying a clock signal to said chip; Providing a plurality of groups of time-separated parallel address signals to the address terminals on the chip and applying the clock signal to the chip to address one random position in the array; C. L. latching the parallel address signals of each group when they are applied to said chip; Applying said parallel data signal to said data terminal in synchronization with said clock signal, wherein each set of parallel data signals represents one data word; Carrying said parallel data signal on said array data read; F. B. generating a sequence of address signals starting from said latched address signal addressing a random location in said array; Applying the address signal sequence to the array address read to address a location in the array where the data signal is to be written. 11. A write control method for controlling writing to a dynamic random access memory array, wherein the array is formed on a chip and includes a plurality of array data reads for carrying parallel data signals to the array. A plurality of parallel array address reads carrying parallel address signals to the array, wherein one data signal represents one data bit and one address signal is one.
Represents one address bit, wherein the array is arranged in a plurality of addressable locations, each location comprising a data word of a plurality of data bits, and each location comprising a data word from the array data read. Data bit 1
The write control method, wherein one word is randomly addressable by the address signal to write to each addressed location; Applying a clock signal to said chip; Providing a plurality of groups of time-separated parallel address signals to the address terminals on the chip and applying the clock signal to the chip to address one random position in the array; C. L. latching the parallel address signals of each group when they are applied to said chip; Generating an address signal sequence starting from said latched address signal addressing a random location in said array; Applying an address control data signal to the address terminals on the chip, the address control data controlling an address starting from the latched address signal addressing a random location in the array. And F. G. applying said address signal sequence to said array address read to address a location in said array where said data signal is to be written; Writing data from a data terminal on the chip to the array data read. 12. A method of using a dynamic random access memory device, comprising: Carrying a plurality of parallel array data signals between a plurality of array data leads and an array of dynamic random access memory formed on an integrated circuit chip, wherein one data bit is converted to one data signal. Said steps, including saturating; B. Conveying a parallel array address signal to said array on a parallel array address read, comprising representing one address bit with one address signal;
Said steps; C. D. randomly addressing a random location in the array with the array address signal addressing one data word of a plurality of data bits; Writing a word of data bits to each addressed random location from said array data read; Reading a word of data bits from each addressed random location into said array data read; F. G. receiving a first clock signal at a first clock signal terminal; B. receiving a second clock signal at a second clock signal terminal; Receiving a parallel address signal at a plurality of address terminals while the first and second clock signal terminals are receiving the first and second clock signals, wherein the parallel address signals are temporally separated. Said steps occurring in a plurality of said groups. Coupling said received address signal to said array address read, comprising indicating an address of a random location in said array with said received address signal; J. Transmitting and receiving parallel data signals at a plurality of data terminals, including representing one data word in each set of parallel data signals; K. Coupling said plurality of data terminals to said array data leads; Receiving the parallel data signal in synchronism with the first clock signal to write the parallel data signal to the array at a random location indicated by the received address signal; and To read at a random position indicated by the received address signal from
Sending the parallel data signal in synchronization with the second clock signal.