JP4674865B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having a memory block, and further to a technique for improving the throughput of a data read operation in response to a read access request. Technology.

  A storage hierarchy of a storage device in consideration of temporal and spatial locality of information reference is generally configured by a plurality of memories having different access speeds and storage capacities. DRAM (Dynamic Random Access Memory) with a low cost per bit is used for the main memory, and the level close to the processor or CPU (Central Processing Unit) is configured by SRAM (Static Random Access Memory). Cache memory to be used is arranged. The cache memory holds data that is temporally and spatially localized with respect to data recently used by the processor, and makes it possible to improve the throughput as compared with the data read operation from the lower level.

  The inventor was informed of the existence of Japanese Patent Application Laid-Open Nos. Hei 2-297971 and Hei 6-195261 after completing the present invention. These documents describe having a dynamic memory (DRAM) and a static memory (SRAM) on a one-chip semiconductor substrate, and using the DRAM and the SRAM as a cache memory. However, the object of the present invention and its configuration are not described therein.

Japanese Patent Laid-Open No. 2-29791 JP-A-6-195261

  The present inventor has studied to incorporate a large number of DRAM modules having a relatively low access speed together with a logic circuit so that the DRAM module can be used as a cache memory. For example, a DRAM-embedded semiconductor integrated circuit that can be used for a level 3 (L3) cache memory of a microprocessor incorporating level 1 (L1) and level 2 (L2) cache memories was examined.

  According to the study of the present inventor, when trying to shorten the memory read cycle by seemingly shortening the memory read cycle by mounting a large number of DRAM modules in parallel, consideration is given to avoiding competition such as data output operation due to parallel operation. There must be. In this case, when trying to adopt a data buffer to avoid data contention, it was found that it was useless to perform data buffering even when no data contention occurred.

  Considering the data processing efficiency by the processor, the primary improvement is the throughput of the read operation in response to the read access of the processor. At this time, the read operation of the cache memory also includes a read operation for copy back (or write back) accompanying write access by the processor, and such read operation does not require high throughput in most cases. That is, copy back is an operation of saving the data in the main memory in order to replace a dirty cache line in the event of a cache miss. Therefore, when considering the use as a cache memory, the logic scale of the logic circuit should not be increased unnecessarily by adding a light weight difference according to the use of the read data for improving the read data throughput. The need to do so has been clarified by the inventor.

  In addition, for processor write access, it is not as important to speed up the write processing that responds to it, but considering the data processing efficiency of the processor, the write access request is accepted and the processor is put into operation for a short time. It is necessary to release with. In particular, in the case of a DRAM, a refresh operation of stored information is required at each refresh interval, so that reception of a write access request must not be delayed.

  An object of the present invention is to provide a semiconductor integrated circuit capable of improving the throughput of a read operation in a configuration employing a data buffer in order to avoid data contention due to parallel operation of memory blocks.

  Another object of the present invention is to provide a semiconductor integrated circuit capable of improving the throughput of the read operation so that the logic scale of the logic circuit is not increased unnecessarily.

  Another object of the present invention is to provide a semiconductor integrated circuit that can easily accept a write access request regardless of the internal memory operation state.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A read buffer is employed to avoid data contention due to parallel operation of memory blocks, thereby improving the throughput of the read operation. As a configuration for this purpose, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel, and external interface means (I / O) that can input write data from the outside and output read data to the outside. F1), a read buffer (RB0 to RB3) capable of holding read data read from the memory block in response to a state in which it cannot be output to the outside from the external interface means, and the output impossible Selecting means (40, 41) for selecting the read data read from the memory block or the read data read from the read buffer and giving the read data to the external interface means when the state is resolved .

  According to the above means, when one read data of a memory block that can be operated in parallel is output to the outside from the external interface means, if the read operation of another memory block is performed, the read data Since resource contention occurs in this case, the data is temporarily stored in the read buffer, and after the previous data output operation is completed, the data can be output from the read buffer to the outside. Therefore, even if there is a read access request that causes resource contention in the read data output operation, the read operation can be started without waiting for the request, and when there is no risk of resource contention, the read data is immediately read from the buffer. Can be output to the outside, and in this respect, the throughput of the read data output operation can be improved.

  If there is no resource contention when data is read from the memory block, the read data is directly output from the external interface means without going through the read buffer. Therefore, even if no data contention occurs, the data is temporarily stored. Waste such as buffering can be avoided, which contributes to the improvement of the throughput of the read data output operation.

  The read buffer may be constituted by a memory having a small capacity and high speed as compared with the memory block. For example, when the memory block is composed of a DRAM module, the read buffer may be composed of an SRAM module.

  To describe the above configuration from the viewpoint of control, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) that can operate in parallel and a read buffer that can hold read data read from the memory block. (RB0 to RB3), external interface means (I / F1) capable of outputting the read data output from the read buffer and the read data output from the memory block to the outside, and read from the memory block In response to a state in which read data cannot be output from the external interface means to the outside, the read data is held in the read buffer, and read from the memory block when the non-outputable state has been resolved Read data read from the read buffer or the read buffer And a control means for outputting from the interface means (MCNT), the.

  [2] In order to make it possible to easily accept external write access requests regardless of the internal memory operation state, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) capable of operating in parallel, External interface means (I / F1) capable of inputting write data from the outside and the write data inputted to the external interface means are inputted and held, and the write data is stored in the memory block after the memory block is enabled for the write operation. And write buffers (WB0 to WB3) to be supplied to.

  Even if there is a request for write access during a memory block internal operation such as refresh or read operation of stored information, write data can be buffered in the write buffer in advance. It is possible to release the write access operation in a short time. When considering the data processing efficiency of the processor, etc., it is not important to increase the write processing on the memory side in response to the write access of the processor. However, from the above, it is necessary to wait for the write access request of the processor. This contributes to improving the data processing efficiency of the entire system.

  The write buffer may be configured by a memory having a smaller capacity and higher speed than the memory block. For example, when the memory block is configured by a DRAM module, the write buffer may be configured by an SRAM module.

  If the above configuration is mainly described from the viewpoint of control, the semiconductor integrated circuit includes an external interface unit (I / F1) capable of inputting write data from the outside, and a write buffer for inputting the write data input to the external interface unit (WB0 to WB3), a plurality of memory blocks (BNK0 to BNK7) to which write data is supplied from the write buffer, and write data supplied to external interface means in response to an external access request And a control unit (MCNT) that stores the data in the buffer and waits for the memory block to be accessed to be able to perform a write operation, and supplies write data from the write buffer to the memory block.

  [3] The semiconductor integrated circuit having both the read buffer and write buffer configurations is capable of inputting a plurality of memory blocks (BNK0 to BNK7) capable of operating in parallel and inputting write data from the outside and reading to the outside. External interface means (I / F1) capable of outputting data and write data input to the external interface means are input and held, and the write data is supplied to the memory block after the memory block is enabled for write operation. A write buffer (WB0 to WB3) and a read buffer (RB0 to RB3) capable of holding read data read from the memory block in response to a race condition that cannot be output to the outside from the external interface means And when the non-output possible race condition is resolved, the memory block Read read data or select the read data read from the read buffer having a selecting means for giving the outside interface means (40, 41).

  [4] Assume a use as a cache memory that can be connected to both lower and upper level storage hierarchies. At this time, the semiconductor integrated circuit includes a plurality of memory blocks (BNK0 to BNK7) capable of operating in parallel and first external interface means (I) capable of inputting write data from the outside and outputting read data to the outside. / F1) and second external interface means (I / F2) capable of inputting write data from the outside and outputting read data to the outside. Further, the semiconductor integrated circuit inputs and holds the write data input to the first or second external interface means, and supplies the write data to the memory block after the memory block is enabled for the write operation (WB0 to WB3), holding read data to be output from the second external interface means, and read data to be output from the first external interface means, which cannot be output from the first external interface means A read buffer (RB0 to RB3) capable of holding read data in a different race state, and the read data read from the memory block when the non-output race state has been resolved, or The read data read from the read buffer is selected and the first external interface is selected. A selection means providing a means (40, 41), the.

  In this configuration, the first external interface means is connected to the upper storage hierarchy, and the second external interface means is connected to the lower storage hierarchy. The basic operation of the read buffer and the write buffer with respect to the read / write access request of the processor is the same as described above. In particular, the output of read data to the lower storage hierarchy via the second external interface means is only data output via the read buffer. This is because a read operation for copy back (or write back) accompanying write access by the processor is assumed as read data output to the lower storage hierarchy. Copyback is an operation that saves the data to the main memory in order to replace the dirty cache line in the event of a cache miss, so in such a read operation, high throughput is not required in most cases. The data path that enables the read data to be output from the second external interface means and the logic circuit therefor are omitted so that the logic scale of the circuit is not increased unnecessarily.

  Considering application of the semiconductor integrated circuit to a multiprocessor system, another processor is connected to the lower storage hierarchy side, and the semiconductor integrated circuit is operated for accessing the other processor. A case is assumed. In order to cope with this, it is sufficient that the first and second external interface means can individually input an access request and an access address to the memory block from the outside.

  In addition, if resource contention occurs when read data is supplied from the lower storage layer to the upper storage layer through the semiconductor integrated circuit, data is input from the second external interface unit and held. Further, having the memory buffer (54) capable of outputting the held data from the second external interface means to the outside increases the convenience of the semiconductor integrated circuit as the cache memory.

  [5] When the memory block is composed of, for example, a DRAM, the access time of the DRAM can be shortened even in a known page mode or static column mode. Further, in order to shorten the apparent access time in a memory block constituted by a DRAM, serial / parallel conversion is performed on the data input, and parallel / serial conversion is performed on the data output. That is, the semiconductor integrated circuit includes a memory cell array (10), a row selection circuit (11), a column selection circuit (12, 13), a serial / parallel conversion circuit (21), a write amplifier (17W), a main amplifier (17R), It includes a memory block having a parallel / serial conversion circuit (25). The memory cell array has a plurality of memory cells each having a selection terminal connected to a word line and a data input / output terminal connected to a bit line. The row selection circuit responds to the change of the row address strobe signal in synchronization with the clock signal and selects the word line specified by the row address signal. The column selection circuit responds to the change of the column address strobe signal in synchronization with the clock signal and selects a plurality of bit lines specified by the column address signal in parallel. The serial / parallel conversion circuit converts the write data serially input from the write buffer into parallel data in synchronization with the clock signal. The write amplifier outputs the output of the serial / parallel conversion circuit in parallel to a plurality of bit lines selected by the column selection circuit. The main amplifier amplifies parallel data output in parallel from a plurality of bit lines selected by the column selection circuit. The parallel / serial conversion circuit converts the parallel data supplied from the main amplifier into serial data in synchronization with the clock signal, and outputs the serial data to the read buffer and the selection means.

  The memory block receives the column address strobe signal that is changed at a cycle of n (a positive integer greater than or equal to 2) times the clock signal cycle, and reads from the memory cell array every cycle when the column address signal is changed. A plurality of serial data converted in parallel / serial in synchronization with the clock signal cycle is output from the memory block, and the parallel data input in the memory block in synchronization with the clock signal cycle and subjected to serial / parallel conversion is output to the memory cell array. Written on. As described above, it is possible to increase the memory operation speed by the access specification that the column address strobe signal is changed once every n cycles of the clock signal.

  A serial data input path of the serial / parallel converter circuit and a serial data output path of the parallel / serial converter circuit may be provided independently. In the read operation, data is read from the memory cell array in response to the change in the column address strobe signal, and then serial / serial conversion takes time to output serial data from the memory block. In the write operation, the column address strobe signal is output. Before the parallel data is written to the memory cell array in response to the change of the above, the operation for converting the serial data input to the memory block into the parallel data in advance must be completed. At this time, when a write operation is instructed following the read operation, serial data for the write operation is sequentially serially input to the memory block in advance in parallel with the operation of outputting the serial data from the read operation from the memory block. Many operations are expected to be performed. That is, there is a high probability that the serial data output timing from the memory block and the serial data input timing to the memory block overlap. As described above, by having the serial data input path and serial data output path of the memory block independently, it is possible to realize efficient processing by avoiding data collision even for such processing overlap. Become.

  [6] When considering propagation delay of read data, it is preferable to adopt the following layout configuration for the semiconductor integrated circuit. For example, a center pad configuration in which external connection electrodes such as signal input / output bonding pads or bump electrodes are arranged at the center of the chip is assumed. At this time, the memory blocks are arranged opposite to each other on the semiconductor chip. A read buffer capable of holding read data read from the memory block and a write buffer capable of holding write data to be given to the memory block are arranged between the opposing memory blocks. External interface means is disposed in the vicinity of the read buffer and the write buffer. An external connection electrode located in the vicinity of the external interface means; The write buffer receives and holds the write data input to the external interface means, and supplies the write data to the memory block after the memory block is enabled for the write operation. The read buffer can hold the read data read from the memory block in response to a state in which the read data cannot be output from the external interface means to the outside.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the read operation throughput can be improved in a configuration employing a data buffer in order to avoid data contention due to parallel operation of memory blocks.

  The throughput of the read operation can be improved so that the logic scale of the logic circuit does not increase unnecessarily.

  It is possible to realize a semiconductor integrated circuit that can easily accept a write access request regardless of the internal memory operation state.

  FIG. 1 generally shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 shown in FIG. 1 is not particularly limited, but is a semiconductor integrated circuit assumed to be used as an L3 cache memory, and includes eight memory blocks BNK0 to BNK7, four write buffers WB0 to WB3, Four read buffers RB0 to RB3, an upper layer interface block I / F1 connected to an upper storage layer (for example, a processor bus), a lower layer interface block I / F2 connected to a lower storage layer (for example, a memory bus), a memory A control circuit MCNT is included.

  The upper layer interface block I / F1 is connected to a processor bus to which a processor incorporating an upper storage layer, for example, an L1 cache memory and an L2 cache memory is connected, and includes access control information including an access control signal and an access address signal. In addition, for example, data is input / output in parallel with 72 bits.

  The lower layer interface block I / F 2 is connected to a lower storage layer such as a memory bus to which a main memory or an L4 cache memory is connected, and inputs and outputs data in parallel, for example, 72 bits. Although not particularly limited, the lower layer interface block I / F 2 inputs access control information from another processor so that it can be accessed from a processor different from the processor of the upper storage layer, assuming a multiprocessor system. Thus, the memory blocks BNK0 to BNK7 can be accessed.

  The memory control circuit MCNT inputs access control information, decodes a part of address information included in the memory control circuit MCNT, determines an access target memory block, and outputs a local memory address and an access control signal to the access target memory block. To control the operation of the memory block.

  In the memory block BNK0 shown as a representative, write data inputted in series in units of 72 bits (8 bytes) is sequentially latched in four write registers (ILT) 22, and 288 bits (32 bytes) are paralleled. The read data read from the DRAM core 8 in parallel with 288 bits is latched in the read register (OLT) 26 in units of 72 bits, and the selector 27 sequentially outputs the output of the read register 26. The read data can be output serially in units of 72 bits. Therefore, the memory block BNK0 can input / output data at a speed four times the access time of the DRAM core 8. In this specification, one byte includes 8-bit data and 1-bit parity data.

  Write data from the upper storage layer input to the upper layer interface block I / F1 is supplied to the memory block BNK0 (BNK1 to BNK7) via the write buffer WB0 (WB1 to WB3).

  There are three output paths for read data read from the memory block BNK0 (BNK1 to BNK7): an upper through path, an upper buffering path, and a lower buffering path. The upper through route is a route that is output from the upper layer interface block I / F1 to the upper storage layer via the selectors 40 and 41 schematically shown. The upper buffering path is a path for outputting the read data once stored in the read buffer RB0 (RB1 to RB3) from the upper hierarchy interface block I / F1 to the upper storage hierarchy via the selectors 40 and 41. The lower buffering path is a path for outputting the read data once stored in the read buffer RB0 (RB1 to RB3) from the lower hierarchy interface block I / F2 to the lower storage hierarchy via the selector 42. There is no through path to the lower layer.

  The read buffers RB0 to RB3 and the write buffers WB0 to WB3 are constituted by SRAM. Access to these SRAMs is made possible in units of one cycle defined by the system clock signal. The SRAM constituting each of the read buffers RB0 to RB3 and the write buffers WB0 to WB3 can be configured in the same manner as a known SRAM. The SRAM is not particularly limited, but includes a memory array including a plurality of static memory cells, a plurality of word lines, and a plurality of complementary data line pairs, an address decoder that selects a predetermined word line in response to an address signal, and a selection A sense amplifier for amplifying data of the plurality of memory cells and a data output circuit for outputting the amplified data are provided.

  As will be described below, each SRAM has a configuration in which 72 memory cells are simultaneously selected in response to a set of address signals. Each static memory cell includes a pair of CMOS inverters including an N-channel MOSFET and a P-channel MOSFET, and an information storage unit configured by cross-coupling the input and output of the pair of CMOS inverters. And a selection transistor including a plurality of N-channel type transfer MOSFETs for selecting the information storage unit. The gate terminals of the plurality of select transistors are selectively coupled to one to a plurality of word lines, and the source / drain paths of the plurality of select transistors are a pair of complementary data lines. And configured as a memory cell with multiple input ports and multiple output ports. Each of the SRAMs constituting the read buffers RB0 to RB3 and the write buffers WB0 to WB3 is not particularly limited, but has a configuration of 128 words × 72 bits.

  It will be readily appreciated by those skilled in the art that the configuration of the memory cell of the multi-input port / multi-output port can be variously changed.

  FIG. 2 illustrates details of the output path of the read data in the semiconductor integrated circuit 1. The memory blocks BNK0 and BNK4 share the read buffer RB0 and the write buffer WB0. Similarly, the memory blocks BNK1 and BNK5 share the read buffer RB1 and the write buffer WB1, the memory blocks BNK2 and BNK6 share the read buffer RB2 and the write buffer WB2, and the memory blocks BNK3 and BNK7 share the read buffer RB3 and the write buffer WB3. Share. The write buffers WB0 to WB3 and the read buffers RB0 to RB3 are not particularly limited, but have two read ports and two write ports. Each port is an 8-byte parallel access port.

  A selector 41Aa for selecting either read data from one memory block BNK0 and read data from the other memory block BNK4 is provided. Similar selectors 41Ab to 41Ad are provided for the other memory blocks. S10 to S13 are selection control signals for the selectors 41Aa to 41Ad. A selector 40Aa is provided for selecting either the read data output from the read buffer RB0 or the read data selected by the selector 41Aa. Similar selectors 40Ab to 40Ad are provided for the other memory blocks. S20 to S23 are selection control signals for the selectors 40Aa to 40Ad. The outputs of the selectors 40Aa to 40Ad are selected by the selector 41B and given to the upper layer interface block I / F1. The operation of the selector 41B is controlled by 2-bit selection signals S30A and S30B. The selector 42 selects an output from one read port of the read buffers RB0 to RB3 and supplies it to the lower layer interface block I / F2. The operation of the selector 42 is controlled by 2-bit selection signals S31A and S31B.

  FIG. 3 illustrates control signals generated by the memory control circuit MCNT. The memory control circuit MCNT outputs an address signal ADRS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and the like for each of the memory blocks BNK0 to BNK7, and an address signal ADRS and a memory for each of the read buffers RB0 to RB3. Enable signal MS, read / write signal R / W, and port select signal PSL are output, and address signal ADRS, memory enable signal MS, read / write signal R / W, and port select signal PSL are output for each of write buffers WB0 to WB3. The selector selection signals S10 to S13, S20 to S23, S30A, S30B, S31A and S31B are output, and the output enable signals OEP1 and OEP2 for the interface blocks I / F1 and I / F2 are output. To. The memory control circuit MCNT inputs the access control information from both the upper storage hierarchy and the lower storage hierarchy, and sends a necessary control signal from the control signals to a predetermined value so as to realize the operation indicated by the input access control information. Activation control is performed at the timing. In the memory control circuit MCNT, signals MRef0 to MRef7 related to the refresh operation period of the memory blocks BNK0 to BNK7 are input from the memory blocks BNK0 to BNK7.

  The access control information 43 includes an address specifying unit 43A and an operation specifying unit 43B as illustrated in FIG. The address designating unit 43A includes designation information for the memory blocks BNK0 to BNK7 to be read and written, and address information in the memory block. The operation designating unit 43B reads / writes 8-byte data from, for example, an address designated by the address designating unit and reads / writes continuous 16-byte data from the address designated by the address designating unit to the semiconductor integrated circuit 1. The operation such as reading / writing of continuous 32-byte data from the address designated by the address designating unit is designated.

  The memory control circuit MCNT accepts an external access request so that the memory blocks BNK0 to BNK7 are operated in parallel within a range in which resources do not compete within the semiconductor integrated circuit 1. Further, the memory control circuit MCNT converts one memory block selected from the memory blocks BNK0 to BNK7 or one read buffer selected from the read buffers RB0 to RB3 to the interface blocks I / F1 and I / F2. It is turned on to control the external output of read data.

  FIG. 5 representatively shows a main control procedure of the memory control circuit MCNT in response to an access request from the outside.

  In response to a write access request, the memory control circuit MCNT takes in write data in advance in the corresponding write buffer of the write buffers WB0 to WB3 regardless of whether there is an internal operation such as refresh by the write target memory block. Control is performed (T1). Thereafter, it is determined whether the write target memory block is not performing an internal operation such as refresh and the write operation is possible (T2), and data write to the target memory block is performed after waiting for the determination of the write operation possible (T2). T3).

  FIG. 6 shows an example of a write operation when a refresh operation is interposed during the write access. In FIG. 6, the memory block BNK0 is a write target. U1 to U8 mean access units given from the outside of the semiconductor integrated circuit 1, and the data of the access units is 72 bits in parallel. In the operation cycles 4 to 9 of the system, the memory block BNK0 performs a refresh operation and can be read / written before and after that. Write data is sequentially stored in the write buffer WB0 with a delay of one cycle. Once the write data once stored in the write buffer WB0 can be read / written by the write target memory block BNK0, the write data is sequentially supplied to the write register 22 of the memory block BNK0 every cycle. When the data of the access unit U4 is latched in the write register 22, the memory block BNK0 has already entered the refresh operation. The memory control circuit MCNT interrupts the data transfer from the write buffer WB0 to the write register 22 and waits for the end of the refresh operation. Meanwhile, the writing of write data to the write buffer WB0 is continued. When the refresh operation of the memory block BNK0 is completed in the operation cycle 9, the memory control circuit MCNT asserts the strobe signals RAS, CAS, and WE to the memory block BNK0 in cycle 10 to give write addresses, and access units U1 to U4. Is written to the DRAM core 8 over 4 cycles. In parallel with the writing to the DRAM core 8, the write data of the subsequent access units U5 to U8 are sequentially transferred to the write register 22. The memory control circuit MCNT asserts strobe signals RAS, CAS, and WE to the memory block BNK0 in cycle 14 to give a write address, and writes the data of the access units U5 to U8 to the DRAM core 8 in 4 cycles. As a result, the processor on the upper storage hierarchy side instructing the write access of the access units U1 to U8 is released from the current write access processing in cycle 8 and is affected even if the refresh operation is interposed in the memory block BNK0. Absent.

  FIG. 7 shows an example of a write operation when the write buffer WB0 is not provided. In the absence of the write buffer WB0, when the refresh operation is started in the DRAM core 8, the processor on the upper storage hierarchy side instructing write access outputs the write address and write data, that is, issues the write access request in cycle 4. It must be interrupted and wait while detecting that the refresh operation is complete. After cycle 9 when the refresh operation is completed, the processor on the upper storage hierarchy side issues a write access request again and sequentially outputs the addresses and data of the access units U5 to U8 from cycle 10. As a result, the write data write of the access units U1 to U8 to the DRAM core 8 of the memory block BNK0 is completed in cycle 19, but the processor on the upper storage hierarchy side instructing the write access is released from the write access processing until cycle 13. Not. As is clear from comparison with FIG. 6, the semiconductor integrated circuit 1 that is an L3 cache memory has the write buffers WB0 to WB3, so that the data processing efficiency of the upper layer processors can be remarkably improved. .

  On the other hand, when the memory control circuit MCNT controls the operation of outputting the read data read from the memory blocks BNK0 to BNK7 to the outside via the interface blocks I / F1 and I / F2, the output of the read data is performed. Path selection, that is, selection control of the upper through path, upper buffering path, and lower buffering path is performed to improve the throughput of the data read operation.

  Whether the upper through path or the upper buffering path is selected is determined by the memory control circuit MCNT determining whether there is a risk of resource contention.

  That is, as illustrated in FIG. 5, the memory control circuit MCNT reads data from the DRAM core 8 of the memory block to be accessed (T4) in response to a read access request, and reads the read data into the upper layer interface. It is determined whether there is resource contention when outputting from the block I / F1 to the outside (T5). If there is resource contention, that is, it is not possible to output the read data from the upper layer interface block I / F1 to the outside. If it is possible, the read data is held in the corresponding read buffers RB0 to RB3 (T6). When the non-outputable state is resolved, the read data read from the memory blocks BNK0 to BNK7 or the read data read from the read buffers RB0 to RB3 is sent from the upper layer interface block I / F1. Output to the outside (T7).

  FIG. 8 shows an example of a read operation using the read buffers RB0 to RB3. In FIG. 8, the processor on the upper storage hierarchy side issues access requests A to D continuously in units of system operation cycles. The access request A is a read access request for reading continuous 32-byte data A-0, A-1, A-2, A-3 from the address A of the memory block BNK0. Similarly, the access request B is a read access request for reading consecutive 32-byte data B-0, B-1, B-2, and B-3 from the address B of the memory block BNK4, and the access request C is the address of the memory block BNK1. Read access request for reading continuous 32-byte data C-0, C-1, C-2, C-3 from C, access request D is 32-byte data D-0 continuous from address D of memory block BNK3, This is a read access request for reading D-1, D-2, and D-3.

  When there is the access request A, the memory control circuit MCNT reads 288-bit data designated by the address A in parallel from the DRAM core 8 of the memory block BNK0 and latches it in the read register 26. Then, the read register 26 is sequentially selected, and read data A-0, A-1, A-2, A-3 are output from the memory block BNK0 in units of 8 bytes. The read data is output in units of system operation cycles (one cycle unit). At this time, the upper layer interface block I / F1 is not performing an output operation. Accordingly, the memory controller MCNT transmits the output data A-0, A-1, A-2, A-3 from the memory block BNK0 directly to the upper layer interface block I / F1 by the selectors 41Aa, 40Aa, 41B and externally. Output.

  In parallel with this output operation, the next access request B is issued with a delay of one cycle, and read data B-0, B-1, B-2, and B-3 are sequentially output from the memory block BNK4. The output read data is sequentially stored in the read buffer RB0. Similarly, the read data C-0, C-1, C-2, and C-3 are sequentially output from the memory block BNK1 by the subsequent next access request C and stored in the read buffer RB1. In response to the request D, read data D-0, D-1, D-2, and D-3 are sequentially output from the memory block BNK3 and stored in the read buffer RB3. When the data output to the outside by the upper layer interface block I / F1 is finished while the operation of holding the subsequent read data in the read buffer is completed, the read data of the subsequent access request is read from the read buffer this time. Output to the outside. That is, next to the data A-3, the read data B-0, B-1, B-2, B-3 are sequentially output from the read buffer RB0, and this is selected by the selectors 40Aa, 41B, and the upper layer interface block. Data is transmitted from the I / F1 to the outside. Thereafter, data C-0 to D-3 are continuously output to the outside.

  On the other hand, if there is no read buffer as illustrated in FIG. 9, the next access request cannot be accepted until all the read data related to the first access request A is output to the outside. In different memory blocks, at least the output operation of the read register must not conflict.

  As is clear from this, by adopting the read buffers RB0 to RB3, subsequent read access requests can be received in advance and the internal operation of the memory block can be preceded, and the read buffer has an access speed higher than that of the DRAM. By adopting a fast SRAM, the buffered data output operation is not delayed, and the throughput of the data read operation can be improved.

  Further, when there is no resource contention when data is read from the memory blocks BNK0 to BNK7, the read data is directly output from the upper layer interface block I / F1 without going through the read buffers RB0 to RB3. Even when data contention does not occur, it is possible to avoid waste such as temporarily performing data buffering, which contributes to improving the throughput of the read data output operation.

  Next, the case where the semiconductor integrated circuit 1 is applied to a cache memory system will be described.

  FIG. 10 shows a first example of the cache memory system. The semiconductor integrated circuit 1 is used as an L3 cache memory and is disposed between the processor 50 and the main memory 51. A processor bus 52 is connected to the upper layer interface block I / F 1 of the semiconductor integrated circuit 1 to input / output data to / from the processor and input access control information output from the processor 50. A memory bus 53 is connected to the lower layer interface block I / F 2 of the semiconductor integrated circuit 1 to input / output data to / from the main memory 51. The access control information for the main memory 51 is information issued by the processor 50, although not particularly limited.

  The processor 50 incorporates an L1 cache memory 50B and an L2 cache memory 50C together with the CPU 50A, and further includes a tag control logic (TAG) 50D for the L3 cache memory. The semiconductor integrated circuit 1 is positioned as a data memory unit of the L3 cache memory. The tag control logic 50D has information for associating the index address with the tag address of the cache entry for each cache line of the semiconductor integrated circuit 1 as the L3 cache memory. Further, each cache line has a valid bit indicating the validity of the cache line, and a dirty bit indicating the necessity of copy back or write back to the lower storage hierarchy when the cache line is replaced.

  In FIG. 10, the lower storage hierarchy of the semiconductor integrated circuit 1 is not limited to the main memory, but may be an L4 cache memory. The tag control unit of the L4 cache memory may be configured inside the processor 50.

  FIG. 11 shows a data flow focusing on the read access operation of the processor in the cache memory system of FIG. If the semiconductor integrated circuit 1 has a cache hit by the tag control logic 50D when the L1 cache memory 50B and the L2 cache memory 50C built in the processor 50 have a cache miss, the processor 50 performs read access with the semiconductor integrated circuit 1 as a target. Request. The access control information path at this time is P1. As described above, if there is no resource contention, the read data is returned directly from the memory blocks BNK0 to BNK7 to the processor 50 (path P2). When there is resource contention, the read data is temporarily held in one of the read buffers RB0 to RB3, and returned from the read buffers RB0 to RB3 to the processor 50 at a timing that does not cause resource contention (path P2 '). When the semiconductor integrated circuit 1 also becomes a cache miss, the processor 50 gives access control information to the main memory 51 (path P3), and read data of the main memory 51 is returned to the processor 50 (path P4).

  At this time, if a bus conflict occurs in the path P4 due to the influence of another circuit module, the read data cannot be sent from the main memory 51 to the processor 50. Even if the bus contention is resolved, the processor 50 must issue an access request to the main memory 51 again to access again the main memory 51 having a low access speed such as a DRAM. Therefore, as illustrated in FIG. 11, a high-speed accessible memory buffer (MB) 54 made of SRAM or the like may be disposed between the main memory 51 and the processor 50 as in the read buffers RB <b> 0 to RB <b> 3.

  The memory buffer 54 may be built in the semiconductor integrated circuit 1. The memory buffer 54 may be configured to input and hold data from the lower layer interface block I / F2 and to output the held data to the outside from the upper layer interface block I / F1. The read data output of the memory buffer 54 and the read data output of the memory blocks BNK0 to BNK7 may be exclusive. For example, the processor 50 may operate by directly specifying the memory buffer 54.

  FIG. 12 shows a data flow focusing on the operation for the write access of the processor in the cache memory system of FIG. In the write access of the processor 50, if the semiconductor integrated circuit 1 hits the cache by the tag control logic 50D when the L1 cache memory 50B and the L2 cache memory 50C built in the processor 50 have a cache miss, the processor 50 Request write access with 1 as target. The access control information path at this time is P1. As described above, the write data is temporarily stored in one of the write buffers WB0 to WB3, and when the write target memory block becomes ready for write operation, the write data is written from the write buffer to the memory block (path P5). . Since the semiconductor integrated circuit 1 includes the write buffers WB0 to WB3, the write request does not have to be interrupted even if the refresh operation of the memory block is interposed during the write request. Therefore, the processor 50 can be quickly released from the writing process. When the semiconductor integrated circuit 1 also becomes a cache miss, the processor 50 gives access control information to the main memory 51 (path P3) and gives write data to the main memory 51 (path P6).

  FIG. 13 shows a data flow focusing on the replacement of the cache line in the cache memory system of FIG. When replacing a predetermined cache line of the memory blocks BNK0 to BNK7 in response to a cache miss of the semiconductor integrated circuit 1 at the time of write access or read access, if the dirty bit of the cache line is enabled, before the replacement, The cache line entry must be copied back to the area below the corresponding tag address. The data to be copied back may be stored in the read buffers RB0 to RB3 from the memory blocks BNK0 to BNK7, and there is no need to wait for the actual copying back to the main memory 51 composed of a DRAM having a low access speed. The data of the new cache entry to be replaced may be written from the main memory 51 to the write buffers WB0 to W3 without waiting for the data to be copied back to be transferred to the read buffers RB0 to RB3. As a result, the throughput of the final data read by the processor 50 can be improved even when the cache line is replaced.

  As described with reference to FIGS. 1 and 2, the lower layer interface block I / F2 and the memory blocks BNK0 to BNK7 are only connected via the read buffers RB0 to RB3. Not provided. Copyback is an operation that saves the data to the main memory in order to replace the dirty cache line in the event of a cache miss. Therefore, in such a read operation, high throughput is not required in most cases, and the read buffers RB0 to RB3 are bypassed. If the data path that enables direct read data to be output from the lower layer interface block I / F 2 and the logic circuit therefor are omitted, the logic scale of the semiconductor integrated circuit 1 is not increased unnecessarily.

  FIG. 14 shows a second example of the cache memory system. It is also possible to use the semiconductor integrated circuit 1 as a main memory of the processor 50. In this case, it is not necessary to use the lower layer interface block I / F2 of the semiconductor integrated circuit 1.

  FIG. 15 shows a third example of the cache memory system. The cache memory system shown in the figure is an example applied to a multiprocessor system, and is not particularly limited, but includes the processors 50-1 and 50-2, each of which is configured by the semiconductor integrated circuit 1. The L3 cache memories 1-1 and 1-2 are connected, and the L3 cache memories 1-1 and 1-2 are connected to the main memory 51 via the bus switch circuit 55.

  The L3 cache memories 1-1 and 1-2 are coupled to the processors 50-1 and 50-2 via the processor buses 52-1 and 52-2 connected to the upper layer interface block I / F1, and the processor 50-1 , 50-2, and access control information output from the processors 50-1, 50-2. The lower layer interface block I / F2 of the L3 cache memories 1-1 and 1-2 is connected to the bus switch circuit 55 via the memory buses 53-1, 53-2, and the main memory 51 connects the memory bus 53-3. To the bus switch 55.

  The bus switch circuit 55 is not particularly limited, but selectively realizes first to fourth bus connection states. In the first bus connection state, access control information output from the processor 50-1 is transmitted to the main memory 51, and data input / output is performed between the main memory 51 and the L3 cache memory 1-1 or the processor 50-1. enable. In the second bus connection state, access control information output from the processor 50-2 is transmitted to the main memory 51, and data input / output is performed between the main memory 51 and the L3 cache memory 1-2 or the processor 50-2. enable. In the third bus connection state, the access control information output from the processor 50-1 is transmitted to the L3 cache memory 1-2, and between the L3 cache memory 1-2 and the processor 50-1 or the L3 cache memory 1-1. Enables data input / output. In the fourth bus connection state, the access control information output from the processor 50-2 is transmitted to the L3 cache memory 1-1, and between the L3 cache memory 1-1 and the processor 50-2 or L3 cache memory 1-2. Enables data input / output.

  Since the L3 cache memory 1-2 responds to the third bus connection state, the lower layer interface block I / F 2 receives the access control information output from the processor 1-1 and can operate the cache memory. . Similarly, since the L3 cache memory 1-1 responds to the fourth bus connection state, the cache memory can be operated by receiving the access control information output from the processor 1-2 to the lower layer interface block I / F2. It has become.

  FIG. 16 shows a chip layout of the semiconductor integrated circuit 1. A central portion of the main surface of one rectangular semiconductor chip 1A such as single crystal silicon is a logic circuit region 1B, and memory blocks BNK0 to BNK3 and memory blocks BNK4 to BNK7 are separately arranged above and below the region 1B, respectively. The Read buffers RB0 to RB3 and write buffers WB0 to WB3 are separately arranged at the end of the logic circuit region 1B. Interface blocks I / F1 and I / F2 are separately arranged between the read buffers RB0 to RB3 and the write buffers WB0 to WB3. Many external connection electrodes (not shown) such as bonding pads or bump electrodes are arranged in the vicinity of the interface blocks I / F1 and I / F2. Although not particularly limited, the buffer memory (MB) 54 described with reference to FIG. 11 is arranged between the interface blocks I / F1 and I / F2. Although not specifically shown, other logic circuits are also arranged in the logic circuit region 1B.

  By adopting the layout configuration of FIG. 16, the read buffers RB0 to RB3 are located closer to the interface blocks I / F1 and I / F2 and the external connection electrodes than the memory blocks BNK0 to BNK7. As a result, the read data from the read buffers RB0 to RB3 is externally applied to the path operation delay and propagation delay in which the read data is directly output from the read registers of the memory blocks BNK0 to BNK7 without passing through the read buffers RB0 to RB3 It is possible to prevent the operation delay and propagation delay of the path to be output from increasing excessively. Therefore, the layout configuration contributes to an improvement in the throughput of the data read operation.

  FIG. 17 shows a detailed example of the memory block. A memory block BNK0 typically shown in the figure has a memory cell array 10 in which dynamic memory cells (not shown) are arranged in a matrix. The dynamic memory cell includes a capacitive element for storing information and a selection transistor composed of an N-channel type MOSFFT coupled thereto, and a selection terminal which is a gate of the selection transistor is connected to a word line WL. One end of the source / drain path is coupled to the capacitor element, and the other end of the source / drain path, that is, the data input / output terminal is connected to the complementary bit line BL. Although not shown in particular, the complementary bit line has a folded bit line structure centered on the sense amplifier, and a precharge circuit or the like is disposed between the complementary bit lines.

  The row decoder 11 is a row selection circuit that selects the word line WL specified by the dress row address signal RAS ADR in response to the falling change of the row address strobe signal RAS. The complementary bit line BL is selected by the column decoder 13 and the column switch circuit 12. The column decoder 13 generates a column selection signal 14 for selecting a plurality of complementary bit lines specified by the column address signal CASADR in parallel in response to the falling change of the column address strobe signal CAS. Further, the column decoder 13 activates the write signal 15W in response to the write operation instruction by the low level of the write enable signal WE, and activates the read signal 15R in response to the read operation instruction by the high level of the write enable signal WE. Turn into. The column switch circuit 12 performs a switching operation in response to a column selection signal 14 and outputs a 32-byte (288 bits) complementary bit line indicated by the signal 14 to a 32-byte complementary write data line WIO and a 32-byte complementary read. The data lines RIO are respectively passed.

  The complementary write data line WIO is supplied with 32-byte write data output from the write amplifier 17W in parallel. The complementary read data line RIO is supplied with 32-byte read data in parallel to the main amplifier 17R. The write amplifier 17W has 288 write amplification circuits, and in response to activation of the write signal 15W, an amplification signal for the 288-bit write data DIN <0> to DIN <3> input in parallel is provided. The complementary write data line WIO can be operated in parallel with 288 bits. The main amplifier 17R has 288 read amplification circuits, and in response to activation of the read signal, the amplification signal corresponding to the input from the complementary read data line RIO is converted into 288-bit read data MAOUT <0. > To MAOUT <3> to enable parallel output operation. The data DIN <0>,..., DIN <3> are each 8 bytes, and the data MAOUT <0>,..., MAOUT <3> are each 8 bytes.

  A serial / parallel conversion circuit 21 is disposed between the input path 20 of the write data WD and the write amplifier 17W. Although not particularly limited, the write data WD is supplied in 8-byte parallel. The serial / parallel conversion circuit 21 includes the four write registers 22 and the data latch control circuit 23. The input terminals of the write register 22 are commonly connected to the input path 20, and the output terminals are individually coupled to the input terminals of the write amplifier circuit of the write amplifier 17W. The data latch control circuit 23 decodes the 2-bit latch control data DLAT <1: 0> in synchronization with the clock signal CLK to generate a 4-bit latch control signal DINL <3: 0>, and the corresponding write register 22 latch control is performed. By sequentially incrementing and changing the latch control data LATD <1: 0>, the write data WD input in parallel in units of 8 bytes are sequentially latched in the four write registers 22 in synchronization with the clock signal CLK. Write data DIN <0> to DIN <3> are obtained from the outputs of the four write registers 22 in parallel by 32 bytes.

  A parallel / serial conversion circuit 25 is disposed between the output path 29 of the read data MUXOUT and the main amplifier 17R. The parallel / serial conversion circuit 25 includes four read registers 26, an output selector 27, and a selection control circuit 28. Read data MAOUT <0> to MAOUT <3> are input to the input terminals of the read register 26 from the main amplifier 17R, respectively. The latch timing of the read register 26 is controlled by a latch control signal PDOLTT. The latch timing by the latch control signal PDOLTT is controlled by an output control circuit 30 described later so as to be the timing after the read data MAOUT <0> to MAOUT <3> are determined by the data read from the memory cell. .

  The selector 27 selects the output data DOUT <0> to DOUT <3> of the read register 26 by a selection control signal MSEL <3: 0> by 8 bytes and outputs it to the output path 29. The selection control circuit 28 generates a 4-bit selection control signal MSEL <3: 0> by decoding the 2-bit selection control data MUXSEL <1: 0> in synchronization with the clock signal CLK. As the selection control data MUXSEL <1: 0> is sequentially incremented and changed, the output data DOUT <0> to DOUT <3> are sequentially output to the output path 29 in units of 8 bytes in synchronization with the clock signal CLK. Read data MUXOUT is obtained.

  The output control circuit 30 generates the latch control signal PDOLTT according to CAS latency. The CAS latency is a delay time from the next clock cycle until the data input of the parallel / serial conversion circuit 25 is determined when responding to the falling change of the column address strobe signal CAS in a data read operation. This is expressed in terms of the number of cycles of the clock signal CLK. Specifically, when the falling edge of the column address strobe signal CAS is detected at the falling edge of the clock signal CLK (at the fall edge), the fall of the clock signal CLK following the fall edge for detecting the falling edge of the column address strobe signal CAS is detected. The number of cycles of the clock signal CLK from the edge to the first fall edge of the clock signal CLK in a state where the read data DOUT <0> to DOUT <3> are determined is the CAS latency. The data read operation from the memory cell array 10 and the read data amplification operation by the main amplifier 17R are uniquely determined by the circuit configuration, circuit element characteristics, and the like. Therefore, in order to output data to the outside at high speed, it is necessary to set a CAS latency having a delay time that is equal to or greater than the operation delay time. Since the CAS latency is equivalent to the number of cycles of the clock signal CLK as described above, the actual delay time due to the CAS latency depends on the frequency of the clock signal CLK, and even when the same delay time is set, The CAS latency is relatively large when the frequency is high, and the CAS latency is relatively small when the frequency of the clock signal CLK is low. In the example of FIG. 1, the output control circuit 30 receives the latency setting data FRCD <1: 0> to realize a CAS latency control circuit capable of variably controlling the CAS latency. The CAS latency is reflected in the latch timing according to the latch control signal PDOLTT.

The refresh control circuit (RCC) 40 is a control circuit for periodically refreshing the data of each memory cell in the memory cell array, and generates a plurality of internal control signals ref for the internal circuit of the memory block BNK0. Supply. On the other hand, the refresh control circuit 40 outputs to the memory control circuit MCNT a refresh period notification signal MRef0 that activates the memory block BNK0 during the refresh period.

  As is apparent from the above description, the memory blocks BNK0 to BNK7 are supplied with the column address strobe signal CAS which is changed at a multiple of the clock signal CLK, and the column address signal CAS is changed. Each time, a plurality of serial data read out from the memory cell array 10 and converted in parallel and serially in synchronization with the cycle of the clock signal CLK is output from the memory block, and input to the memory block in synchronization with the cycle of the clock signal CLK. The parallel data that has been serial-parallel converted is written into the memory cell array 10. As described above, it is possible to increase the memory operation speed by the access specification that the column address strobe signal CAS is changed at a rate of once per a plurality of cycles of the clock signal CLK.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor integrated circuit of the present invention is not limited to a configuration having both upper and lower interface blocks. For example, a configuration including a memory block and a read buffer as shown in FIG. 11, a configuration including a memory block and a write buffer as shown in FIG. 12, and a configuration including a memory block, a read buffer and a write buffer as shown in FIG. It is possible to grasp the present invention separately.

  Further, a read buffer and a write buffer may be provided for each memory block as long as the chip area is sufficient.

  Further, the number of memory blocks, the number of parallel data input / output bits, the number of stages of read registers and write registers, and the like can be changed as appropriate.

  The memory block is not limited to the DRAM, and the read buffer and the write buffer are not limited to the SRAM, but may be a memory of another storage format. Needless to say, the present invention can be widely applied to cache memories of various levels, main memories, and other logic-embedded semiconductor integrated circuits.

1 is a block diagram generally showing an example of a semiconductor integrated circuit according to the present invention. FIG. 2 is a block diagram illustrating details of an output path of the read data in the semiconductor integrated circuit of FIG. 1. It is explanatory drawing which illustrates the control signal which a memory control circuit produces | generates. It is explanatory drawing which illustrates an information format for access control information. It is a flowchart which shows typically the main control procedure of the memory control circuit with respect to the access request from the outside. 10 is a timing chart illustrating an example of a write operation when a refresh operation is interposed during a write access. 6 is a timing chart illustrating a write operation when a write buffer is not provided as a comparative example. 6 is a timing chart illustrating an example of a read operation using a read buffer. 10 is a timing chart showing a read operation when a read buffer is not provided as a comparative example. 1 is a block diagram of a cache memory system using a semiconductor integrated circuit as an L3 cache memory. FIG. 11 is an explanatory diagram showing a data flow focusing on a read access operation of a processor in the cache memory system of FIG. 10. FIG. 11 is an explanatory diagram showing a data flow focusing on an operation for a write access of a processor in the cache memory system of FIG. 10. FIG. 11 is an explanatory diagram showing a data flow focusing on replacement of a cache line in the cache memory system of FIG. 10. 1 is a block diagram of a memory system using a semiconductor integrated circuit as a main memory of a processor. It is a block diagram which shows the example which applied the semiconductor integrated circuit to the multiprocessor system as L3 cache memory. 1 is a layout diagram illustrating a chip layout of a semiconductor integrated circuit according to the present invention. It is a block diagram which shows a detailed example of a memory block.

Explanation of symbols

1 Semiconductor integrated circuit BNK0 to BNK7 Memory block RB0 to RB3 Read buffer WB0 to WB3 Write buffer MCNT Memory control circuit I / F1 Upper layer interface block I / F2 Lower layer interface block 40 (40Aa, 40Ab, 40Ac, 40Ad) Selector 41 ( 41Aa, 41Ab, 41Ac, 41Ad, 41B) Selector 42 Selector 8 DRAM core 22 Write register 26 Read register 50, 50-1, 50-2 Processor 50A CPU
50B L1 cache memory 50C L2 cache memory 50D Tag control logic 51 Main memory 52, 52-1, 52-2 Processor bus 53, 53-1, 53-2, 53-3 Memory bus 54 Memory buffer 55 Bus switch circuit CLK clock Signal BL Complementary bit line WL Word line RAS Row address strobe signal CAS Column address strobe signal

Claims (4)

A write buffer circuit for sequentially storing input data ;
A plurality of write registers for sequentially storing the input data stored in the write buffer circuit in units of the input data;
A memory block having a plurality of memory cells that require a refresh operation periodically, and holding the input data stored in the plurality of write registers in parallel;
When the refresh period starts, the input of data to the write buffer circuit is continued and the input data to the memory block is waited for the data of the write buffer circuit to be stored in the plurality of write registers. And a control circuit that resumes the operation of writing the input data stored in the write register into the memory block when the refresh period ends. The memory block further includes a plurality of word lines and a plurality of data lines ,
Each of the plurality of memory cells is coupled to the plurality of word lines and the plurality of data lines so that one memory cell is coupled to one word line and one data line. Including a transistor,
2. The semiconductor integrated circuit according to claim 1, wherein said selection transistor has a selection terminal coupled to a corresponding word line and a data input / output terminal coupled to a corresponding data line. Each of the write buffer circuits is
A memory array including a plurality of static memory cells, a plurality of word lines, and a plurality of complementary data line pairs;
An address decoder for selecting a predetermined word line in response to an address signal;
A sense amplifier that amplifies data of a plurality of selected memory cells;
3. The semiconductor integrated circuit according to claim 2, further comprising a data output circuit for outputting the amplified data.   4. The semiconductor integrated circuit according to claim 3, wherein each of the plurality of static memory cells includes a pair of inverters whose input / output terminals are cross-coupled.

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