JPH10210501A - Memory control circuit for digital still camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the memory control circuit for a digital still camera costwise advantageous in which a capacity of a frame memory is reduced. SOLUTION: In Y, U, V data of 4:2:2 sampling outputted from a camera signal processing section 2 or a companding processing section 5 in the case of compression or expansion, the luminance data Y are written as they are and only the color difference data U, V are written in a frame memory 4A while being down-sampled (data thinning) in a form of 4:1:1. In the case of read from the frame memory 4A, only the color difference data U, V are up- sampled (interpolation) so as to give data equivalent to 4:2:2 sampling apparently to the companding processing section 5 or a display device 7 adopting the JPEG or the like. Since a memory control section 30 conducting processing as above is provided, the capacity of the memory 4A is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital still camera having a function of converting a still image into digital compressed image data and recording the data on a recording medium or the like, thereby reducing the frame memory capacity required for compression processing and the like. And a memory control circuit of the digital still camera.

[0002]

2. Description of the Related Art In a digital still camera (hereinafter, DSC) to which image compression technology is applied, an image sensor such as a charge-coupled device (hereinafter, CCD) and a signal processing circuit (DS) are used.
In general, the digital image data obtained from P) is temporarily buffered in a memory such as a DRAM, and then stored and recorded in an internal non-volatile memory or a removable recording medium through an image compression processing process such as JPEG. Has been taken.

FIG. 9 is a block diagram showing a memory control circuit for performing a compression process in a conventional digital still camera.

In FIG. 9, an image pickup signal from a camera unit 1 having an image sensor such as a CCD is signal-processed by a camera signal processing unit 2 and output as a digital video signal. 4 once. A DRAM or the like is used as the memory 4. Thereafter, the data is read out again from the memory 4, subjected to compression processing such as JPEG in the compression / decompression processing section 5, and is recorded on the recording medium 6.

[0005] Considering the case of the JPEG compression method as an example, since the data input format to the compression / decompression processing unit 5 usually needs to be performed by block interleaving, raster / block conversion is performed before the compression / decompression processing unit 5. , A conversion process from line-sequential data to an 8 × 8 pixel block data format is performed.

If the JPEG compression / decompression processing section 5 has a processing speed higher than the video signal data transmission rate, so-called real-time compression becomes possible. In this case, the capacity of the memory 4 is limited to the raster / block conversion. It is sufficient if there is a capacity for eight horizontal lines, which is the minimum memory capacity for this.

However, considering the use of the DSC, the real-time property is rarely required, and the JPEG compression (expansion) processing speed is reduced from the viewpoint of reducing power consumption and reducing the circuit scale by suppressing the circuit speed. ,
It is often less than a fraction of the video signal data rate.

In such a case, the video signal needs to be once captured in the memory 4 in units of one screen (frame or field), and read out while sequentially converting the data into block data in accordance with the compression processing speed. Therefore, a frame memory for one screen is required as the memory 4.

In particular, if the memory 4 has a frame memory capacity, it can also be used as a display buffer memory for displaying a captured still image on a main body liquid crystal monitor or the like. A DRAM having a corresponding frame memory capacity is mounted.

In the data interface between the process circuits, Y (luminance signal), U (color difference; BY signal), V (color difference; BY signal) are used from the viewpoint of ease of processing and reduction of bus width.
Digital data is often handled in the form of a so-called Y / color difference signal (color difference; RY signal).

On the other hand, recently, 640 has been used as an image sensor because of its affinity with a personal computer and emphasis on image quality.
A DSC equipped with a sensor having a so-called VGA square pixel configuration having an effective pixel number of (horizontal) × 480 (vertical) is becoming mainstream.

In a DSC equipped with such a VGA image sensor, a so-called 4: 2: 2 (that is, 2: 1: :) is used as a sampling ratio of internal Y, U, and V data.
Although the data format of 1) is adopted, conventionally, from the camera signal processing section (YUV output section) 2 to the compression / decompression processing section 5, processing is performed while maintaining this sampling ratio.

This is because even in the JPEG compression method,
The data format of 4: 2: 2 (that is, 2: 1: 1) is generally used to avoid problems such as compatibility between a compressed image file recorded on the recording medium 6 and image viewer software on a personal computer. It also has meaning.

Therefore, the capacity of the memory 4, for example, which is composed of a DRAM, is selected in accordance with the number of pixels (size) handled by the DSC without changing the ratio of 4: 2: 2 (ie, 2: 1: 1). Was.

By the way, 4: 2: 2 (ie, 2: 1: 1)
In the case of, the capacity of the frame memory required for compressing one VGA (Video Graphics Array) size image data is 640 × 480 × 2 × 8 [bit] = 4.9.
[Mbit], but the general DRAM capacity is 4Mbit
In this case, two 4 Mbit products are inevitably used (indicated by reference numerals 4A and 4B in FIG. 7), resulting in an increase in cost.

[0016]

As described above, 4:
In the case of 2: 2 (that is, 2: 1: 1), the capacity of the frame memory required for compressing one VGA size image data is 4.9 Mbit, which means that two 4 Mbit products are used. This has led to an increase in cost. Accordingly, an object of the present invention is to provide a memory control circuit of a digital still camera which can reduce the capacity of a frame memory and is advantageous in cost in view of the above problems.

[0017]

According to the first aspect of the present invention,
In a digital still camera having an image compression / expansion processing function, a memory, memory write means for storing the digital image data before compression or after expansion in the memory while thinning the digital image data, and the thinning digital image data stored in the memory. Memory reading means for reading out from the memory while interpolating the amount and sending it to the compression / decompression processing unit or the display device.

According to the first aspect of the present invention, the memory temporarily stores the digital image data from the camera signal processing unit,
While it is necessary to match the operation speed of the compression processing by the compression / decompression processing unit, the compressed data read from the recording medium is decompressed by the compression / decompression processing unit and stored for display processing. Needed to supply. On the other hand, the compression / decompression processing unit generally determines a data format for compression.
There is a number of display dots as specified by. Therefore, in the present invention, when the digital image data is thinned out and stored in the memory under the control of the memory writing means, and thereafter read out from the memory for compression processing or display processing,
Under the control of the memory read means, the thinned-out portion is read out while interpolating, thereby reducing the memory capacity.

According to a second aspect of the present invention, there is provided a digital still camera having an image compression / decompression processing function, wherein a luminance signal of a memory and digital image data composed of a luminance signal and a color difference signal before or after compression are unchanged. Memory write means for storing in the memory while thinning out only the color difference signal, and among the digital image data stored in the memory, reading out only the color difference signal from the memory while interpolating the thinning amount; Memory reading means for sending the data to the display device.

According to the second aspect of the present invention, when storing image data in the memory, the luminance signal is stored as it is while thinning out only the color difference signal. This is because the band of the color difference signal is relatively narrower than that of the luminance signal, so that even if the color difference signal is reduced, there is almost no perceived deterioration in resolution and unnaturalness.

According to a third aspect of the present invention, there is provided a digital still camera having an image compression / expansion processing function, wherein a Y, U, 4: 2: 2 sampling Y, U, Of the V data, only the color difference signals (U, V) are
A memory write means for writing to the frame memory in a 4: 1: 1 format while downsampling the data to the frame memory; and performing a raster / block conversion while upsampling only the color difference signals (U, V). And read the data from the
Memory reading means for sending sampling data matching the number of data in 4: 2: 2 format.

According to a fourth aspect of the present invention, there is provided a digital still camera having an image compression / expansion processing function, wherein Y, 4: 2: 2 sampling format decompressed by a frame memory and a compression / expansion processing unit at the time of expansion. U,
At the same time as block / raster conversion of compressed image data composed of V data, color difference signals (U,
V) while writing down to the frame memory in a 4: 1: 1 format while down-sampling only V), and up-sampling only the color difference signals (U, V) when reading out the frame memory. A memory reading means for reading data from the frame memory and sending sampling data corresponding to the apparent number of 4: 2: 2 data to the display device is provided.

According to a fifth aspect of the present invention, there is provided a digital still camera having an image compression / decompression processing function.
A memory writing means and a memory reading means according to the present invention, and a memory writing means and a memory reading means according to a fourth aspect are provided.

According to the third to fifth aspects of the present invention, at the time of compression or decompression, the Y data of the 4: 2: 2 sampling Y, U, V data output from the camera signal processing unit or the compression / decompression processing unit is used. Is DR while downsampling (data thinning) of only the color difference signals (U, V) as it is
When writing to a frame memory such as AM in the 4: 1: 1 format, and reading out the frame memory, only the color difference signals (U, V) are up-sampled (interpolated (including double reading)) to apparently make JPEG or the like. And a digital still camera having memory control means (memory write means and memory read means) for sending 4: 2: 2 sampling equivalent data to a compression / decompression processing unit or a display device.

Data processing in the circuit section other than the memory section is as follows.
Processed as general 4: 2: 2 array data, DRAM
Only the writing format to the frame memory such as 4:
For example, in the case of a VGA size image sensor, the amount of image data in the memory is 640 ×
480 × 1.5 × 8 = 3.69 Mbit, 4 Mbit
DRAM capacity of 4Mbit DR
Only one AM needs to be used, and because of the visual characteristics of human beings, only color information data that has a relatively narrow band compared to Y (luminance signal) is reduced, so that visual resolution degradation and discomfort are almost eliminated. VGA size image data can be handled without feeling.

The compressed data recorded on a recording medium such as a built-in non-volatile memory has a general 4: 2: 2 format, so that the versatility and compatibility as a file are maintained. Dependency on application software (such as an image viewer) on a personal computer can be minimized.

[0027]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a digital still camera according to one embodiment of the present invention. FIG.
Portions having the same functions as those described above will be described with the same reference numerals.

In FIG. 1, an image pickup signal from a camera unit 1 having an image sensor such as a CCD is signal-processed by a camera signal processing unit 2 and output as a digital video signal. Store temporarily in 4A. At the time of writing to the memory, the memory control unit 30
Of the digital image data composed of the luminance signal Y and the color difference signals (U, V), one frame of the image data is stored in the memory 4A while thinning out only the color difference signals (U, V) without changing the luminance signal Y. Thereafter, the data is read out again from the memory 4A and supplied to the compression / decompression processing unit 5. At the time of memory reading, of the digital image data stored in the memory 4A, only the color difference signals (U, V) are read from the memory 4A while interpolating the thinning amount, and supplied to the compression / decompression processing unit 5.

The compression / decompression processing unit 5 performs a compression process such as JPEG on the image data read out while interpolating, and outputs it to the recording medium 6 as compressed digital image data. Digital image compression data is recorded on the recording medium 6. As the recording medium 6, in addition to a built-in nonvolatile memory, a removable disk or the like is used.

When reading from the recording medium 6 and displaying it on the display device 7, the compressed image data recorded on the recording medium 6 is decompressed by the compression / decompression processing unit 5, and then stored in the memory under the control of the memory control unit 30. Store temporarily in 4A. At the time of writing to the memory, the memory control unit 30 controls the color difference signals (U, V) without changing the luminance signal Y among the digital image data including the luminance signal Y and the color difference signals (U, V).
One frame of the image data is stored in the memory 4A while thinning only the data. After that, it is read out again from the memory 4A and displayed on the display device 7. At the time of memory reading, only the color difference signals (U, V) of the digital image data stored in the memory 4A are read from the memory 4A while interpolating the thinning amount, and supplied to the display device 7.

The interpolation in the above description includes a method of interpolating by reading digital image data (sampling data) twice.

FIG. 2 is a block diagram showing compression processing in the digital still camera of FIG.

In FIG. 2, a portion surrounded by a rectangular broken line is
3 shows functional blocks of the memory control unit 30 involved in the compression processing. In the drawing, solid arrows indicate the flow of image data.

The video signal to the memory control unit 30 is a total of 16 bits of 8 bits for Y (luminance) and 8 bits for U / V (color difference).
The data transfer rate ratio as Y: U: V is assumed to be so-called 4: 2: 2 (that is, 2: 1: 1). Also, the number of data transfers in one horizontal period is 16 bits × 780, ie, one horizontal period (1H) is 780 fH (fH is a horizontal frequency).
And the number of effective pixels (image size) in the image data is set to horizontal (number of pixels) 640 and vertical (number of lines)
The following description will be made assuming that the VGA size is 480.

Further, as a memory to be accessed, 1
It is assumed that a DRAM (word name: 16 Mbit) × 256 K = 4.096 Mbit (commonly called 4 Mbit product) is used and a mode (for example, a first page mode) in consideration of a processing speed is used.

FIG. 3 is a diagram showing image data timing at the time of compression. FIG. 3A shows the image data timing from the camera signal processing unit 2 to the memory control unit 30, and FIG. 3B shows the image data timing from the memory control unit 30 to the memory 4A.

First, at the time of compression, a video signal obtained from an image pickup device such as a CCD passes through a camera signal processing section 2 including A / D conversion processing and the like, and then a memory control section 30 which is a characteristic part of the present invention. Is entered.

The sequence of the image data is as shown in FIG. 3. Here, for the sake of simplicity, the description will be made by dividing four words into one unit for convenience.

FIG. 3A shows a 780 fH clock (= 12.2) in the image data transfer to the memory control unit 30.
7 MHz), Y data (8 bits) and UV data (8 bits) are shown as image data to be transferred.

First, among the Y data, the Y0 data is
One word (16 bits) together with the next Y1 data input via the one-clock delay latch circuit in the memory control unit 30
The data is converted from byte to word as data and written into the memory 4A such as a DRAM at the timing of W1 in FIG.

On the other hand, the U0 data and the V0 data are similarly converted from byte to word on the color difference bus side, respectively, via the two-clock delay latch circuit and the one-clock delay latch circuit in the memory control unit 30, and at the timing of W2. Is written to.

Here, suppose that Y0 (U0) is the lower byte and Y1 (V0) is the upper byte. However, in the present invention, the upper / lower order and the write address to the memory 4A are limited. Not to mention that it is not.

Next, the Y2 and Y3 data are similarly written into the memory 4A as word data at the timing of W3.

That is, in the transfer unit of four words of interest, what is written to the memory 4A is from Y0 to Y0.
Y3, U0, and V0 are three words. That is, U1
, V1 data will be thinned out.

Of course, the same sequence is repeated in the next 4-word unit, and the memory 4A is actually stored in the effective pixel data transfer (640 words) for one line.
Is written in 320 words of Y data, U / V
The data is 160 words, for a total of 480 words.

When a DRAM is used as the memory 4A, since one page of the DRAM is 512 words,
The image data for the line (1H) is contained within one page, and there is also an advantage that the address control circuit can be relatively easily formed.

In this manner, the next line data is written to the next page, and finally the data for 480 vertical lines is written to 480 pages.
If the overall data number ratio of Y: U: V is 4: 1: 1.

FIG. 4 shows an example of 4: 1: 1 format data mapping to the DRAM which is the memory 4A.

FIG. 4A shows the entire memory area.
(b) shows an example of a state in which data for one line is written, but the present invention is not limited to addressing as described above.

In this way, the VGA (640 × 480)
Of the 4: 2: 2 size data, all the Y data are written to the DRAM without being thinned out, and the color difference signals (U, V) are down-sampled (data thinned out) by そ れ ぞ れ, respectively. Memory mapping is performed on the DRAM in a 1: 1 ratio. In FIG. 4 (b),
An arrangement state of one line of data, that is, data mapped in one page of the DRAM is shown. For Y data, Y0, Y1, Y2, Y3,... Are stored as they are, while for U and V data, U0, V0
, U2, V2,..., U1, V1, U3, V3
, ... will be thinned out.

Next, the data is sent to the compression / decompression processing unit 5.
As the G compression method, the data transmission format must be block interleaved data in units of 8 × 8 pixels.

As a JPEG compressed file, 4: 1:
There are color space sampling formats such as 1: 4: 2: 0, 4: 2: 2, etc. Among them, 4: 2: 2 format files are common, and image viewer (software compression / decompression) application software Most software also supports 4: 2: 2 format data.

Therefore, it is considered that the versatility is increased when the data is transferred as 4: 2: 2 format data to the JPEG compression / decompression processing unit 5.

However, in this system, since the data is 4: 1: 1 when the data is written into the DRAM, only the color difference information (U / V) is read twice or the interpolation calculated from the preceding and succeeding data is performed. Adding data, apparently,
It is necessary to pass the pseudo 4: 2: 2 data format to the compression / decompression processing unit 5.

FIG. 5 is a diagram showing the block interleaved data transfer timing during compression.

The transfer bus width is 1 byte (8 bits), and data transfer in block interleave (pseudo 4: 2: 2 (1 pseudo 2: 1: 1) with 1 MCU = 4 blocks) is shown. is there. Here, for the sake of simplicity, upsampling by double reading is shown, but of course, an interpolation method by an arithmetic method may be used. That is, in the first block B1, the data of Y0 (B1) to Y63 (B1) is stored in the DRAM 4A.
, And in the next block B2, Y0 (B2) to Y63
The data of (B2) is read.

Next, the color difference data is read out twice every other byte, and U0 (B1, B2), U0 (B1, B2), U2 (B1, B2), U2
(B1, B2),... U62 (B1, B2), U62 (B1, B2), and V0 (B1,
B2), V0 (B1, B2), V2 (B1, B2), V2 (B1, B2),.
(B1, B2), V62 (B1, B2), U block, and V block are read in this order. (1 MCU = 4 block units) Thereafter, processing in the next MCU unit is continuously performed.

In this way, the pseudo 4: 2: 2 (pseudo 2:
By performing the compression processing at 1: 1), it is apparently 4: 2:
The two data compression codes are output to the compression / decompression processing unit 5.

FIG. 6 is a diagram showing the block interleaved data transfer timing at the time of decompression.

The operation at the time of decompression is completely opposite to the operation at the time of compression, and the 4: 2: 2 format block data output from the compression / decompression processing unit 5 (in this case, decompression operation) to the memory control side is performed. FIG. 6 shows that when writing to the DRAM 4A, the data must be stored in the 4: 1: 1 format, so that the block data U0 to U63 and V0 to V63
It is necessary to write data to the DRAM 4A by thinning out the data in units of bytes. Of course, it goes without saying that the mapping of the Y and U data stored on the DRAM 4A is performed in exactly the same manner as in FIG.

FIG. 7 is a block diagram showing a decompression process in the digital still camera of FIG.

In FIG. 7, a portion surrounded by a rectangular broken line is
3 shows functional blocks of the memory control unit 30 associated with the decompression process. In the drawing, solid arrows indicate the flow of image data.

The image data from the compression / decompression processing unit 5 to the memory control unit 30 is Y (luminance) 8 bits, U / V (color difference) 8b
It is 16 bits in total, and the data transfer rate ratio as Y: U: V is so-called 4: 2: 2 (that is, 2: 1: 1).

The color difference data of the image data is thinned out from the memory controller 30 to the memory 4A, and the data transfer rate ratio of Y: U: V is 4: 1: 1. Similarly, the data transfer rate ratio from the memory 4A to the memory control unit 30 is 4: 1: 1.

The thinning amount is interpolated by passing the image data from the memory 4A through the memory control unit 30 and sent to the display device 7 at a data transfer rate ratio of Y: U: V = 4: 2: 2. Is done.

FIG. 8 is a diagram showing image data timing at the time of decompression. FIG. 8A shows the image data timing read from the memory 4A through the memory control unit 30, and FIG. 8B shows the image data timing from the memory control unit 30 to the display device 7.

First, at the time of decompression, the recording medium 6
The compressed image data obtained from is input to the memory control unit 30, which is a characteristic part of the present invention, through the A compression / decompression processing unit 5.

The sequence of the image data is as shown in FIG. 8 (similar to the case of the compression in FIG. 3). For example, four words will be divided into one unit for convenience.

The data obtained by decompressing the compressed image data from the recording medium 6 by the compression / decompression processing unit 5 is transmitted to the memory control unit 30.
Through the memory 4A. From the memory control unit 5 to the memory 4A, only the color difference data (U, V) of the image data is thinned out and stored in the memory 4A under the control of the memory writing means, while the luminance data Y of the image data remains unchanged.

In the case of displaying an image, FIG.
As shown in (a), the data in the memory 4A is controlled by the memory reading means in the memory control unit 30, and Y0, Y1 and U0
, V0 are word-to-byte converted, and each is Y8 bit
, U, V8 bits. Next, after the Y2 and Y3 data have been transferred from the memory 4A, the color difference signals are again output to U0 and V0 under the control of the memory reading means.
The data is read, word-byte converted, and read. Then, the memory control unit 30 uses the two-clock delay latch circuit and the one-clock delay latch circuit in the memory control unit 30 to display the display device 7 as shown in FIG.
Is converted and output. In this manner, the image data stored in the memory 4A in a state where the color difference data (U, V) is thinned out is interpolated by the thinning amount and the display device 7 is interpolated.
Is output to the display device 7, so that the display device 7 looks like 4:
It can be treated and displayed as 2: 2 data.

As described above, according to the embodiment of the present invention, at the time of compression, for example, the Y data of the 4: 2: 2 sampling Y, U, V data output from the camera signal processing unit 2 is used. DRA while downsampling (data thinning) only the color difference signals (U, V)
M is written in the frame memory 4A such as M in the 4: 1: 1 format, and when reading out the DRAM, only the color difference signals (U, V) are up-sampled (interpolated or read twice), so that the compression and decompression of JPEG or the like are apparently performed. Processing unit 5f4:
Since the memory control unit 30 that transmits data equivalent to 2: 2 sampling can be realized, for example, in the case of a VGA size image sensor, the image data amount to the memory 4A is 64.
0 × 480 × 1.5 × 8 = 3.69Mbit, 4M
Since the capacity of the DRAM is smaller than the capacity of the DRAM, only one 4Mbit DRAM needs to be used as the memory 4A.
Also, because of the visual characteristics of human beings, only data of color information, which has a relatively narrow band compared to Y (luminance signal), is reduced.
VG with almost no reduction in visual resolution or discomfort
A-size image data can be handled.

The compressed data recorded on the recording medium 6 such as a built-in non-volatile memory or a disk has a general 4: 2: 2 format, so that the versatility and compatibility as a file are maintained. In addition, the dependence on application software (such as an image purer) on a computer can be minimized.

[0073]

As described above, according to the present invention, in a digital still camera having an image compression / expansion processing function, digital image data from a camera signal processing section or a compression / expansion processing section is thinned out and stored in a memory. Thereafter, when reading from the memory for compression or display processing, by reading out the thinned-out portion while interpolating, the memory capacity can be reduced and a digital still camera which is advantageous in cost can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a digital still camera according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a compression process in the digital still camera of FIG. 1;

FIG. 3 is a diagram showing image data timing of each unit during compression.

FIG. 4 is a diagram showing an example of data mapping in a 4: 1: 1 format to a DRAM.

FIG. 5 is a diagram showing block interleaved data transfer timing during compression.

FIG. 6 is a diagram showing block interleaved data transfer timing at the time of decompression.

FIG. 7 is a block diagram showing a decompression process in the digital still camera of FIG. 1;

FIG. 8 is a diagram showing image data timing of each unit at the time of decompression.

FIG. 9 is a block diagram of a conventional digital still camera in compression processing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Camera part 2 ... Camera signal control part 4A ... Memory 5 ... Compression / decompression processing part 6 ... Recording medium 7 ... Display device 30 ... Memory control part

Claims (5)

[Claims] 1. A digital still camera having an image compression / expansion processing function, comprising: a memory; memory write means for storing digital image data before or after compression in the memory while thinning the digital image data; A memory control circuit for a digital still camera, comprising: memory read means for reading data from the memory while interpolating the thinning amount and sending the data to a compression / decompression processing unit or a display device. 2. A digital still camera having an image compression / expansion processing function, wherein, of a digital image data composed of a memory and a luminance signal and a color difference signal before or after compression, only a color difference signal is decimated without changing a luminance signal. A memory write unit that stores the color difference signal in the digital image data stored in the memory while interpolating the thinning amount from the memory, and sends the color difference signal to a compression / expansion processing unit or a display device. A memory control circuit for a digital still camera, comprising: a read unit. 3. A digital still camera having an image compression / decompression processing function, comprising: a frame memory;
Of the 2: 2 sampling Y, U, and V data, the color data (U, V) alone is down-sampled by で while the Y data is kept as it is, and the 4: 1 ::
Memory write means for writing in one format, and a color difference signal (U,
Memory reading means for reading data from the frame memory while up-sampling only V) and sending to the compression / decompression processing section apparently sampling data corresponding to the number of data in the 4: 2: 2 format. A memory control circuit for a digital still camera. 4. A digital still camera having an image compression / decompression processing function, comprising a frame memory and, at the time of decompression, Y, U, and V data of 4: 2: 2 sampling format decompressed by a compression / decompression processing unit. Memory writing means for writing compressed image data to the frame memory in a 4: 1: 1 format while performing block / raster conversion and down-sampling only the color difference signals (U, V) by で without changing the Y data. When reading the frame memory, the color difference signals (U, V)
Data is read out from the frame memory while only up-sampling is performed.
2. A memory control circuit for a digital still camera, comprising: memory read means for sending sampling data matching the number of data in the 2: 2 format. 5. A digital still camera having an image compression / decompression processing function, comprising: a memory writing unit and a memory reading unit according to claim 3; and a memory writing unit and a memory reading unit according to claim 4. Memory control circuit of a digital still camera.