JPH04355793A - Television display interface device - Google Patents

Abstract

PURPOSE:To offer the television display interface device which easily realizes functions similar to those of an oscilloscope at low cost by using a home color television set, etc. CONSTITUTION:Input/output interface storage devices 1 and 2 detect and store an electric signal from a body to be measured and convert them into signal conforming to a video signal. Color specifying circuits 4 and 5 convert the signals outputted by the input/output interface devices into RGB signals. A composing circuit 6 composes one group of signals of the two groups of RGB signals outputted by the two color specifying circuits and a video encoder 7 converts the signals into a color video signal, which is outputted. A control circuit 3 controls the input/output interface devices 1 and 2, color specifying circuits 4 and 5, composing circuit 6, and video encoder 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television display interface device, and more particularly, to an improvement of a television display interface device that realizes the function of an oscilloscope when combined with a home television receiver, for example.

0002

2. Description of the Related Art Conventionally, it has been common to use an oscilloscope to observe the operating waveforms of various parts of an electronic circuit. However, oscilloscopes are large and heavy, making them inconvenient to carry, and in addition, they are expensive, making them unsuitable for easy use at home.

[0003] In order to solve the above-mentioned problems, a means described in Japanese Patent Application Laid-open No. 159270/1983 has been proposed. This allows any time-varying arbitrary signal to be
Converts to a signal that can be displayed on TV using various storage elements,
This converted signal is modulated so that the arbitrary signal can be observed on a television receiver.

0004

[Problems to be Solved by the Invention] However, although the above-mentioned Japanese Patent Application Laid-Open No. 54-159270 describes in detail the method of converting the signal into a signal that can be displayed on a television, it is difficult to know how to convert the signal that can be displayed on a television. There is no description at all of how to display the text, or especially how to display it in color. Therefore, in order to display in color, a new color display means is required. In addition, in the case of black and white display,
Using the method described in Publication No. 4-159270 as is,
TV display can be realized. However, in the case of multi-channel black-and-white display, many black-and-white curves for multiple channels are displayed on one television screen, and it is difficult to distinguish and view the many curves individually.

The present invention has been made to solve the above problems, and provides an oscilloscope that can easily and inexpensively display a color display that is easy to view even with multiple channels using a home color television or the like. An object of the present invention is to provide a television display interface device capable of realizing functions.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the present invention detects an output signal from an object to be measured, stores the detected signal, and generates a predetermined video signal based on the stored signal. a plurality of input/output interface storage devices for generating input/output interface storage devices; and a plurality of color specification circuits for generating signals that can be displayed in color based on the output video signals outputted from the input/output interface storage devices; Consists of a synthesis circuit that synthesizes multiple output signals output from the circuit into a set of signals, and a video encoder that converts this synthesized set of signals into a colorized video signal and outputs it. did.

[0007]

According to the present invention, the input/output interface storage device detects an electrical signal from the object to be measured, stores the detected electrical signal, and converts the stored electrical signal into a signal conforming to a video signal. The color designation circuit divides the signal output from the input/output interface storage device into, for example, three, sets each to a predetermined level, and converts it into a set of R, G, and B signals that separately represent red, green, and blue. . R like this,
A plurality of sets of G and B signals are output from the color designation circuit. The plurality of R, G, and B signals are combined into a set of signals in a combining circuit and output. This set of R, G, and B signals is converted into a colored video signal by a video encoder, output, and sent to a television receiver, where the figures (curves) for each electrical signal are displayed in multiple colors. do.

[0008]

Embodiments Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. FIG. 1 shows a basic block diagram of the entire television display interface device I. As shown in FIG. The block diagram of this principle is
This is the case of a television display interface device that has two input channels and is compatible with an interlaced television receiver.

As shown in FIG. 1, the display interface device I detects and stores a first electrical signal S1 and a second electrical signal S2, which are output signals from an object to be measured (not shown). R
, G, and B signals and output them, and a synthesis circuit 6 that synthesizes the output R, G, and B signals from the color specification circuits 4 and 5 to form one set of R, G, and B signals. , a video encoder 7 that encodes a composite set of R, G, and B signals into a composite video signal, and each of the circuits 1, 2, 4--
and a control circuit 3 that controls the control circuit 7.

FIG. 2 shows a specific configuration of a television display interface device I1 compatible with an interlaced television having one input channel. As shown in FIG. 2, an input detection section 10 that detects a first electrical signal S1 from an object to be measured (not shown) and adjusts the input level, an LPF 11 for preventing aliasing distortion during sampling, and an A/ D converter 12, high speed memory section 13, and comparator 14
, an inversion/non-inversion circuit 15 , a counter 16 , level designation circuits 17 , 18 , 19 , a synthesis circuit 20 , a video encoder 21 , and a control circuit 22 .

Next, the television display interface device I1
Explain the operation. The first electrical signal S1 detected from the object to be measured is detected as an electrical signal by an input detection section 10 such as a probe, where it is amplified or attenuated and converted to an optimal level for signal processing. The electrical signal adjusted to the optimum level is band-limited in the LPF 11 to prevent aliasing distortion during sampling, and the band-limited electrical signal is converted into a digital signal by the A/D converter 12 and stored in the high-speed memory 13. Ru. The signals stored in the high-speed memory 13 cannot be displayed on the television as they are. However, the magnitude of the signal indicates the horizontal scanning order on the television screen, and the larger the signal, the lower the horizontal scanning order. By utilizing such characteristics, the comparator 14 and the inverting/non-inverting circuit 1
5 and a counter 16 convert the signal into a signal that can be displayed on a television.

This conversion method will be explained based on the flowchart shown in FIG. First, it is determined whether or not the (L0+i) line of the first field is being scanned on the television screen shown in FIG. 4(A) (step S1), and in the case of the first field, "1" is output ( Step S2), if it is not the first field, output "0" (Step S2).
3). Here, the L0 line refers to the start line of horizontal scanning.

If the scanning is within the effective horizontal scanning line period (step S4: Yes), it is determined whether or not it is the first pixel displayed in the horizontal direction on the television screen (step S5).
), if it is the first pixel (step S5: Yes),
It is determined whether it is the L0th line (step S6), and the L0
If it is a line (step S6: Yes), the counter 16 is reset by a counter reset signal (see FIG. 5) (step S7). If it is not the L0 line (step S6: No), the counter up signal (Figure 5
), the count 16 is incremented by "1" (step S16). As the output of steps S7 and S16, the "binary number of i" of the i-th line is output. This binary number is normally inverted by the inverting/non-inverting circuit 15 (step S
8). Moreover, in step S5, if it is not the first pixel (step S5: No), the process advances to step S8. By doing so, the horizontal line to be displayed for data display on the television screen and the pixels to be displayed on this line are specified.

On the other hand, the signal (data) from the high-speed memory 13
is read out (step S9), and it is determined whether it is the lowest data (step S10). Here, the lowest data is
It is used to determine whether it is the first field or the second field. In the case of the lowest data (step S10: Yes)
), the output of step S10 and step S2 or S3
is compared with the output in the comparator 14 (step S11). In this case, the signal read out from the high-speed memory 13 has the least significant bit as "" in the first field.
1" and "0" in the second field. Here, the output of step S10 and the output of step S2 or S3 are compared.
(Step S11: Yes)
, means that the field in which the data should be displayed has been confirmed.

On the other hand, the bits other than the lowest data that are the display image data (step S10: No) and the output signal of the inverting/non-inverting circuit 15 in step S8 are
The data are compared in order from the lowest to the lowest (step S12). A match in the comparison results means that the line to be displayed has been determined, and a mismatch means that the line has not been determined. Here, the resolution of the A/D converter 12 is N, and the counter 1
6 outputs in order from the lowest to Q0, Q1 to QN-2
Then, the output of the memory 13 is sequentially D0, D1 from the lowest
When ~DN-1, comparison of data other than the lowest data is Q0 and D1, Q1 and D2, ~QN-2
and DN-1. Y in step S11
If the es output and the Yes output of step S12 match in all bits (step S13: Yes)
, the field, line, pixel position, and display data to be displayed are specified, and VH is output as the output signal VC (step S13: Yes). If they do not match in step S13, one of the specified items is missing, and VL is output (step S15).

If it is outside the effective horizontal scanning line period (step S4: No), the above operation is not performed and the data is kept in the memory (step S17), and the signal VL that is not displayed is used as the output signal VC. Output. This output signal VC corresponds to a signal based on the i-th line video signal (video signal excluding color information and synchronization signal). The waveform of the data read from the memory 13 in this manner is displayed on the television screen as shown in FIG. 4(B). However, it is displayed in black and white.

Furthermore, the resolution of the A/D converter 12 is N
Then, by performing the above operation from the LOth horizontal scanning position over 2 (N-1) times and over 2 fields, it is possible to display a waveform with a vertical resolution of 2 to the N power on the TV screen. It becomes like this. However, the resolution can be easily changed by controlling both the horizontal and vertical directions as long as it is lowered. Furthermore, when inverting the waveform on the television screen, the inversion/non-inversion circuit 15 may be used to non-invert the signal.

The signal VC obtained by the above operation is
Since it corresponds only to the luminance signal, which is a black and white signal, it is converted into a color signal by the following operation. First, the signal VC is 3
are divided into R, R, and sent to level specifying circuits 17, 18, and 19, and their levels are adjusted to produce a predetermined color.
It is output as G and B signals. These R, G, B signals are
A synchronizing signal is added in a synthesis circuit 20, and a video encoder 21 separates the signal into a luminance signal and a chroma signal, which are encoded into a composite NTSC video signal and converted into a signal that can be displayed in color on a television. In this case, A/D converter 12, high speed memory 13 and counter 1
6, level designation circuits 17, 18, 19, synthesis circuit 20, and video encoder 21 are controlled by a control circuit 22.

Next, the specific structure and operation of the control circuit 22 will be explained with reference to FIG. First, the configuration of the control circuit 22 includes a reference clock generator 30, a reference synchronization signal generator 31, a write clock generator 32, a read clock generator 33, an instruction circuit 34, and a range setting section 35. has been done. Next, the operation of the control circuit 22 will be explained.

A reference system clock CK is generated in a reference clock generator 30, and in response to this system clock CK, a reference synchronization signal generator 31 mainly generates a system clock CK and a color subcarrier signal FS.
, horizontal synchronization signal HD, and composite synchronization signal CS
and a vertical synchronization signal VD. The write clock generator 32 uses the system clock CK and the instruction circuit 3.
4, the sampling clock CKS is supplied to the A/D converter 12, and the write control signal CW is supplied to the high speed memory 13. The read signal generator 33 uses the system clock CK and the instruction circuit 34.
In response to the read instruction signal SR, the read control signal CR is supplied to the high speed memory 13. The range setting section 35 is
The display mode etc. are selected and the instruction signal S is sent to the instruction circuit 34.
Output to. The instruction circuit 34 receives the instruction signal S, the horizontal synchronization signal HD, the composite synchronization signal CS, the vertical synchronization signal VD, and the color subcarrier signal FS.
In response to this, it generates a horizontal synchronizing signal HD and a counter reset signal RC to control the counter 16. The instruction circuit 34 provides instruction signals SW and SR to the write clock generator 32 and read clock generator 33, and provides an instruction signal SL for instructing level adjustment to the level designation circuits 17, 18, and 19. The instruction circuit 34 sends a composite synchronization signal CS to the synthesis circuit 20 and the video encoder 21
, a composite synchronization signal CS, a blanking signal,
Control signals CE such as burst gate pulses and hue control signals
and color subcarrier signal FS. The color subcarrier signal FS is used for chroma modulation and color burst signal addition by the video encoder 21.

In this embodiment, the output of the counter 16 is passed through the inverting/non-inverting circuit 15 to control whether or not the waveform is inverted, but the output of the high-speed memory 13 is passed through the inverting/non-inverting circuit. , inversion/non-inversion control may be performed. In addition, the input/output interface storage devices 1 and 2 used in this embodiment are merely examples, and are manufactured by Japanese Patent Laid-Open No. 54-1
The input/output interface storage device described in Japanese Patent No. 59270 may be used.

Furthermore, although the present embodiment shows the case of the NTSC system, it can also be applied to the cases of the PAL system and the SECAM system.

[0023]

As explained above, according to the present invention, there are plural sets of input/output interface storage devices and color specifying circuits, and the outputs of the plurality of color specifying circuits are combined and output as one set of signals to the video encoder. Even if multiple channels of graphics are drawn on the TV screen, they can be separated by color, making it easy to distinguish between the graphics.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a specific configuration diagram of the present invention.

FIG. 3 is a flowchart showing the operation of the electric circuit shown in FIG. 2;

FIG. 4 (A) is a diagram showing scanning on a television screen, (B)
) is a diagram when data read from memory is displayed on a television screen.

FIG. 5 is a diagram illustrating resetting a counter and incrementing the counter by "1".

FIG. 6 is a diagram showing a specific configuration of the control circuit shown in FIG. 2;

[Explanation of symbols]

1, 2...I/O interface storage device 3...Control circuit 4, 5...Color specification circuit 6...Synthesis circuit 7...Video encoder

Claims (1)

[Claims] 1. An input/output interface storage device that detects an output signal from an object to be measured, stores the detected signal, and generates a predetermined video signal based on the stored signal, and the input/output interface storage device. and a plurality of color designation circuits that generate signals that can be displayed in color based on the output video signals output from the plurality of color designation circuits, and combine the plurality of output signals output from the plurality of color designation circuits into one set of signals. A television display interface device comprising: a combining circuit that performs combining; and a video encoder that converts the combined set of signals into a colored video signal and outputs the converted signal.