JP2670200B2 - Thinning circuit in image data reproducing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data reproducing apparatus for supplying thinned-out data for displaying a reduced screen on a TV monitor or the like, and more particularly, for reading out the reduced data from an image memory accumulating the image data. The present invention relates to a thinning-out circuit in an image data reproducing device for generating the address.

[0002]

2. Description of the Related Art For example, when an image is picked up by an image pickup device such as an electronic still camera, image data obtained from this device is YC composed of a luminance signal (Y) and a color difference signal (C).
It is stored in the frame memory as data. The color difference signal includes a signal CR that is the difference between the luminance signal and the red component (RY) and a signal CB that is the difference between the luminance signal and the blue component (BY), and the point where the Y: CR: CB ratio is 4: 2: 2. The data is sequentially developed in the frame memory as data. Specifically, as shown in FIG. 7, (Y0, CR0), (Y1, C
B0), (Y2, CR2), (Y3, CB2) ..., a combination of an odd pixel luminance signal and its color difference signal CR, an even pixel luminance signal and the preceding odd pixel color difference signal CB. Pairs are alternately stored as YC data.

Conventionally, in order to obtain a reduced screen by thinning out the data developed in the frame memory in this manner in the 4: 2: 2 color difference point sequence at an arbitrary reduction ratio, the YC data is divided into R, G and B colors. It was converted to RGB data consisting of component data, and pixel data in multiples of 2 was thinned out from the RGB data to obtain reduced data.

[0004]

However, in the prior art, although it is good to display reduced data as RGB data on a monitor, when transferring as YC data, for example, when transferring image data via a communication line, It was troublesome to convert the RGB data back to YC data for transfer. Also, with RGB data, thinning out by a multiple of 2 was essential due to the characteristics of YC data before conversion, but when thinning out at an arbitrary reduction ratio, there was a possibility that resolution would be compromised.

As shown in FIG. 10, it is conceivable to thin the color difference signals CR and CB in the same space as a reference to create reduced YC data. In this case, the color difference signals are thinned at equal intervals. Since the luminance signals are not evenly spaced, there is a problem that the screen is jagged and the resolution is lowered.

The present invention solves the above-mentioned drawbacks of the prior art, YC data can be thinned out at an arbitrary reduction ratio without causing a breakdown in resolution or the like to obtain YC reduced data, and RGB data can be obtained without a breakdown. It is an object of the present invention to provide a thinning circuit in an image data reproducing device that can be converted into

[0007]

In order to solve the above-mentioned problem, a thinning circuit in an image data reproducing apparatus according to the present invention uses dot-sequential YC data obtained by developing a luminance signal and two color difference signals at a predetermined ratio. In a thinning circuit in an image data reproducing apparatus which reads out reduced data by thinning out data from this image memory, this circuit counts the number of horizontal areas of reduced data in YC data expanded in the image memory. A horizontal area counting means, a vertical area counting means for counting the number of vertical areas of reduced data among the YC data expanded in the same image memory, and a number of horizontal steps of reduced data among the YC data expanded in the image memory And the horizontal step counting means for setting the horizontal address, and the vertical step number of the reduced data of the YC data expanded in the image memory. For selecting a luminance signal or a color difference signal among the data read by the number of steps counted by the horizontal step counting means, and a vertical step counting means for counting to obtain a vertical address, and for selecting either of the two color difference signals. Data selecting means for outputting the selected address of the image memory. The image memory is accessed by an address consisting of a horizontal address from the horizontal step counting means, a vertical address from the vertical step counting means, and a selected address from the data selecting means. It is characterized by

In this case, the horizontal step counting means and the vertical step counting means are counting means each capable of setting the number of steps and the offset value of the address in a programmable manner, and the total number of steps up to the previous time and the number of set steps are set. , An address setting means for outputting an added value from the adding means as an address, an address setting means capable of setting an address offset value in a programmable manner, and an address value from the address setting means. Latch means for latching and outputting and for supplying the address value to the adding means as the total number of steps may be provided.

Further, the data selecting means includes the lower 2 bits of the count value of the horizontal area counting means, the lower 1 bit of the count value of the horizontal step counting means, and the lower 1 bit of the number of steps set in the horizontal step counting means. It may be configured to input and output a selection address for selecting either the luminance signal or the color difference signal and the color difference signal.

In this case, the data selecting means outputs the selection address for selecting either the luminance signal or the color difference signal based on the lower 1 bit of the count value of the horizontal area counting means, and the horizontal area counting. A first AND circuit that ANDs the lower 1 bit and the lower 2 bits of the count value of the means, the inverted value of the output of the first AND circuit and the lower 1 bit of the number of steps set in the horizontal step counter. And a third AND circuit for taking the logical product of the lower 1 bit of the same number of steps and the lower 1 bit of the count value of the horizontal step counting means, the second AND circuit and the It is preferable to include an OR circuit which outputs a logical sum of the AND circuit of No. 3 and the selected AND circuit for outputting any one of the color difference signals.

[0011]

According to the thinning circuit in the image data reproducing apparatus according to the present invention, an image accumulated as dot sequential YC data in which the luminance signal (Y) and the color difference signals (CR, CB) are expanded at a predetermined ratio. When thinning data from the memory to obtain reduced data, the number of areas of the reduced data is counted by both horizontal and vertical area counting means, and an upper address and a luminance signal based on the horizontal and vertical step values from the reduced data. Alternatively, the reduced data is read with a combination of lower addresses for selecting one of the color difference signals.

In this case, the horizontal and vertical step numbers and the address offset value are programmable in the horizontal and vertical step counting means to obtain an arbitrary reduction rate. Furthermore, the lower 2 bits of the count value of the horizontal area counting means, the lower 1 bit of the count value of the horizontal step counting means, and the lower 1 bit of the number of steps set in the horizontal step counting means are input to the data selection circuit. As a result, a selection address for selecting either the luminance signal or the color difference signal and the color difference signal that does not damage the image is obtained. Therefore, the YC data is thinned based on the luminance signal, and the color difference signal suitable for the reduced image can be selected based on the lower bits of the number of thinning steps.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thinning circuit in an image data reproducing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to the schematic block diagram of the reproducing apparatus shown in FIG. 4, the image data reproducing apparatus in the present embodiment is such that the selection addresses A0, A1 and horizontal addresses sent from the thinning circuit 10 are transmitted.
A YC data is sequentially read from the frame memory 20 by a combination of three addresses of A2 to A10 and vertical addresses A11 to A21, and the YC data is converted into RGB data by the data conversion circuit 30 as necessary, and the display device is displayed. It is applied to the data reproduction board which supplies the data. Particularly, in this embodiment, YC data is thinned based on the luminance signal (Y),
The color difference signals CR and CB suitable for the reduced image are selected based on the lower bits of the number of thinning steps.

The YC frame memory 20 stores image data representing an image taken by an image pickup device such as an electronic still camera as 4: 2: 2 dot-sequential data. The dot-sequential YC data is (Y0, CR0), (Y1, CB0),
8-bit luminance signals or color difference signals are alternately stored at each address like (Y2, CR2), (Y3, CB2) .... In this embodiment, as shown in FIG. 8, image data stored in the frame memory 20 is expanded into a bit map of, for example, a horizontal address of 2048 bits and a vertical address of 1028 bits. Decimate YC data sequentially.

Therefore, the control circuit 40 for controlling the thinning circuit 10
Supplies the horizontal area data X and the vertical area data Y to the thinning circuit 10 as shown in FIG. 5, and also outputs the number of horizontal steps, the number of vertical steps, the horizontal (H) offset value, and the vertical (V) offset value. Are respectively supplied to the thinning circuit 10.
These data are input / output in response to the address strobe signal AS and the area setting strobe signal ASET.

The data conversion circuit 30 is provided with an interpolation filter 32, a 3 × 3 matrix operation circuit 34, a shift register 36, etc., as shown in FIG. The interpolation filter 32 interpolates the color difference signals CR and CB of even-numbered pixels of the YC data read from the frame memory 20 to obtain 8-bit Y,
This is an interpolation circuit that generates C and C data. The matrix operation circuit 34 has predetermined coefficients set in a 3 × 3 determinant,
This is an arithmetic circuit that outputs Y, C, C data as 12-bit R, G, B data obtained from them. The shift register 36 is a correction circuit that shifts 12-bit R, G, B data into 8-bit data and outputs the shifted data.

Next, referring to FIGS. 1 to 3, the thinning circuit
10 will be described in detail. The thinning circuit 10 includes a horizontal area counter 100 and a vertical area counter 110 as shown in FIG.
A horizontal step counter 120, a vertical step counter 130, and a data selection circuit 140.

The horizontal area counter 100 calculates the H of the image data.
By setting the direction area data X and counting the strobe signal AS, the carry signal CH is generated at the horizontal end.
Are the counters that respectively output. The horizontal area counter 100 is provided with a clock terminal to which an address strobe signal AS is supplied, an enable terminal (EN) to which an enable voltage of + 5V is supplied, a data terminal to which the horizontal area data X is supplied, and a data read terminal. A load terminal (LD) to which an area setting strobe signal ASET for supplying a count signal, a count output terminal for outputting the lower 1 bit Q0 and lower 2 bits Q1 of the count value, and a carry signal CH
And a carry terminal for outputting the same.

The vertical area counter 110 is used for the V of image data.
The counter is a counter for sending the carry signal CV, which is the end signal when the direction area data Y is set. The vertical area counter 110 is supplied with a clock terminal to which an address strobe signal AS is supplied, an enable terminal (EN) to which a carry signal CH from the horizontal area counter 100 is supplied as an enable signal, and vertical area data Y. And a load terminal (LD) to which the area setting strobe signal ASET is supplied, and a carry terminal for outputting the end signal CV on the output side. The end signal CV is supplied to the control circuit 40 to notify the end of reading the reduced data of one image.

The horizontal step counter 120 is a counter which sequentially adds the number of steps to the set offset value and outputs horizontal address signals A2 to A10. The horizontal step counter 120 receives the address strobe signal
A clock terminal to which AS is supplied and an enable terminal (E to which the enable signal HEN from the data selection circuit 140 is supplied
N), each data terminal to which the horizontal step number and horizontal offset value are supplied, and the area setting strobe signal
With a load terminal (LD) to which ASET is supplied,
Equipped with output terminals for sending count values H0 to H9. The lower one bit H0 of the count value of the counter 120 is supplied to the data selection circuit 140, and the remaining nine bits H1 to H9 are supplied to the frame memory 20 as horizontal addresses A2 to A10.

The vertical step counter 130 is a counter which sequentially adds the number of steps to the set offset value and outputs the vertical address signals A11 to A21. The vertical step counter 130 has a clock terminal to which the address strobe signal AS is supplied, an enable terminal (EN) to which the carry signal CH from the horizontal area counter 100 is supplied as an enable signal, a vertical step number and a vertical offset value. Each data terminal supplied, and a load terminal LD to which the area setting strobe signal ASET is supplied,
It has output terminals for outputting the count values V0 to V9 as vertical addresses A11 to A21.

In this embodiment, each of the horizontal step counter 120 and the vertical step counter 130 is composed of a circuit as shown in FIG. This circuit is
Decoder 200, adder circuit 210, and address generation circuit 23
0 and a latch circuit 240. Decoder 200
Is an enable signal supplied to the enable terminal EN,
The load signal supplied to the load terminal LD and the clear terminal CL
R Input the clear signal supplied and the address generation circuit
The control circuit outputs a status signal for controlling the output status of the 230. Specifically, when the clear terminal CLR becomes "LOW", the first status signal "00" is output, and the clear terminal CLR becomes "H".
When the load terminal LD becomes "Low" at "igh", the second status signal "01" is output, and the clear terminal CLR and load terminal
When both LD are "High" and enable terminal EN is "Low", third status signal "10" is output and clear terminal CLR
, Load terminal LD and enable terminal EN are both "Hig"
When it is "h", the fourth state signal "11" is output.

The address generation circuit 230 includes an adder 21 and an input terminal C0 to which a 10-bit address offset value is supplied.
The input terminal C1 to which the output value of 0 is supplied and the latch circuit 240
The input terminal C2 to which the output value is supplied and the grounded input terminal C3 are selected in response to the four state signals from the decoder 200, and are selected from the output Y to be supplied to the latch circuit 240. Circuit. Specifically, when the status signal is "00", the data is cleared. When the status signal is "01", the address offset value supplied to the input terminal C0 is set, and the status signal is set to "10". In this case, the output value of the latch circuit 240 supplied to the input terminal C2 is read, and when the status signal is "11", the output value of the adder circuit 210 supplied to the input terminal C1 is read and output.

The adder circuit 210 is a circuit that adds the value supplied to the input terminal A and the value supplied to the input terminal B and outputs the result. Specifically, it is an address adding circuit which adds one step number to the output address from the latch circuit 240, that is, the total number of steps, and supplies it to the address generating circuit 230. The latch circuit 240 outputs the output signal of the address generation circuit 230, which is set by the status signal, to the strobe signal.
It is an output circuit that latches based on AS and outputs at that timing. The output of the latch circuit 240 is supplied to the frame memory 20 as a horizontal address or a vertical address.

Returning to FIG. 1 again, the data selection circuit 140
Is a selection address A0 indicating whether the data read from the frame memory 20 is a luminance signal or a color difference signal,
An address generation circuit that outputs selection addresses A0 and A1 indicating whether the color difference signal CR is a red component color difference signal or the blue component color difference signal CB when the color difference signal is a color difference signal. More specifically, as shown in FIG. 3, an output line 300 that outputs the lower 1 bit Q0 of the count value from the horizontal area counter 100 as the selected address A0.
And a first AND circuit 310 that ANDs the nut circuit 360 that inverts and outputs the count value Q0 on the output line 300 and the count values Q0 and Q1 from the horizontal area counter 100.
And a nut circuit that inverts the lower 1 bit HSTEP0 of the number of horizontal steps supplied to the horizontal step counter 120.
320, and the second AND circuit 330 that takes the logical product of the output of this nut circuit 320 and the output of the AND circuit 310, and the logical product of the lower 1 bit H0 of the count value of the horizontal step counter 120 and the number of steps HSTEP0. Third AND circuit 340 to be taken
And the output of the second AND circuit 330 and the third AND circuit 34.
An OR circuit 350 is provided for ORing the output of 0 and outputting the selected address A1. The output HEN branched from the output line 300 is supplied as an enable signal for the horizontal step counter 120 shown in FIG.

Next, the operation of the image data reproducing apparatus having the above configuration will be described. First, the control circuit 40 includes the thinning circuit 10.
, Horizontal area data X and vertical area data Y,
The horizontal address offset data and the vertical address offset data are supplied together with the area setting strobe signal ASET. As a result, the horizontal area data X is set in the horizontal area counter 100, the vertical area data Y is set in the vertical area counter 110, the horizontal offset value is set in the horizontal step counter 120, and the vertical step counter 130 is set in the vertical direction. Offset values are set respectively. Further, the number of horizontal steps and the number of vertical steps are supplied from the control circuit 40, and the number of steps is set in the horizontal step counter 120 and the vertical step counter 130, respectively.

Next, when the address strobe signal AS is supplied from the control circuit 40 to the thinning circuit 10, the horizontal area counter 100 sets the first count values Q0 and Q1 to the data selection circuit 140.
Send to Upon receiving the strobe signal AS, the horizontal step counter 120 latches the horizontal offset value set in the address generation circuit 230 by the latch circuit 240, and supplies the lower one bit H0 to the data selection circuit 140, and outputs the remaining 9 bits.
The bits are output as horizontal addresses A2 to A10. Similarly, the vertical step counter 130 outputs the vertical offset value as vertical addresses A11 to A21. Data selection circuit 14
The value 0 is an odd number because the count value Q0 from the horizontal area counter 100 is read and in this case, it is the first count value, and the address is "0" for selecting the luminance signal. As a result, the address for reading the first Y data, for example, the luminance signal Y0 shown in FIG. 9, is supplied to the frame memory 20.

Next, when the next address strobe signal AS is supplied to the thinning circuit 10, the count value of the horizontal area counter 100 advances by "1", the count value Q0 becomes "0", and the data selection The output address A0 of the circuit 140 becomes the address "1" for selecting the color difference signal. In this case, assuming that the number of steps is halved, the lower 1 bit HSTEP0 of the number of steps is "0". Therefore, the output of the AND circuit 340 shown in FIG. In this case, the color difference signal becomes the AND value of the count values Q0 and Q1 of the horizontal area counter 100, and "0" is set in the selection address A1.
Is output. At this time, since the count value Q0 is "0", the enable signal supplied to the horizontal step counter 120 becomes "Low", and the count value of the horizontal step counter 120, that is, the horizontal address is held. Similarly, the output address of the vertical step counter 130 is held.
Therefore, the upper addresses A2 to A21 are held, and the color difference signal CR0 which is advanced by "1" is read from the address of the luminance signal Y0.

Then, when the next strobe signal AS is output, the count value Q0 from the horizontal area counter 100 becomes "0", and the selection address output from the data selection circuit 140 selects the luminance signal. The address becomes "0". In addition, the enable signal HEN output from the data selection circuit 140
Becomes "High", the horizontal step counter 120 counts up, that is, adds the number of one step to the previous offset value and outputs it. Further, the vertical address of the vertical step counter 130 is held. As a result, shown in FIG.
In the case of 1/2 decimation, the luminance signal Y2 is read.

When the next strobe signal AS is further supplied, the count value Q0 from the horizontal area counter 100 becomes "0", and the selection address A0 becomes the address "1" for selecting the color difference signal. In this case, the logical product of the count values Q0 and Q1 is "
It becomes "0" and "0" is output to the selected address A1.At this time, the enable signal supplied to the horizontal step counter 120 becomes "Low" as described above, and the output address of the horizontal step counter 120 is retained. Then, the color difference signal CB2 which is 4 bits ahead of the luminance signal Y2 is selected.

Similarly, the steps of the horizontal step counter 120 are stepped in the first line to read out the luminance signal first, and subsequently, when the count values Q0 and Q1 of the horizontal area counter 100 are even, the color difference signal is obtained. The color difference signal CB is read when CR is read or when it is an odd number. This operation is repeated in response to the strobe signal AS, and when the horizontal area counter 100 finishes counting the number of horizontal areas X,
The horizontal area counter 100 supplies the carry signal CH to the vertical area counter 110 and the vertical step counter 130, and to its own load terminal LD as a set signal. This allows
The vertical area counter 110 is incremented, and one step is added by the vertical step counter 130 to obtain vertical addresses A11 to A2.
1 is updated. Then, in response to the strobe signal AS, the luminance signal and the two color difference signals are sequentially selected and read in the same manner as above. This is repeated for Y lines, the vertical area counter 110 counts the number of vertical areas, and when the final position of the line is reached, the vertical area counter 110
An end signal is output to the control circuit 40 from the output terminal of.

Also, in the case of the 1/3 thinning shown in FIG. 9, the above 1 /
2 Same operation as decimation, but when selecting a color difference signal, the lower 1 bit HSTEP0 of the horizontal step number is "1", so the output value of AND circuit 330 becomes "0", and therefore the selected address A1 is determined according to the output value H0 of the horizontal step counter 120.

Similarly, in the case of odd-order thinning, the color difference signals CR and CB are determined according to the output value H0 of the horizontal step counter 120, and in the case of even-order thinning, the count values QO and Q1 of the horizontal area counter 100 are determined. The color difference signals CR and CB are determined according to the product of In this case, as shown in FIG. 9, in the even-numbered thinning-out such as 1/2 thinning-out, the color-difference signal CB paired with the next luminance signal in the original data is selected as the even-numbered color-difference signal, and In the case of subtraction, the color difference signal C that becomes the luminance signal
R, CB is selected. Therefore, as shown in FIG. 9, the luminance signal and the color difference signals are arranged at equal intervals in both the case of odd-numbered thinning-out and the case of even-timed thinning, and the display screen does not suffer a decrease in resolution or the like. .

Referring to FIG. 10 for comparison, this FIG.
Shows the case where the thinning-out is performed based on the color difference signals CR and CB. In this case, the color difference signals CR and CB are arranged at equal intervals, but there are variations in the luminance signal, and irregularities such as jaggedness on the display screen have become apparent.

[0036]

As described above, according to the thinning circuit in the image data reproducing apparatus of the present invention, when the image data expanded by the dot-sequential YC data is read from the image memory as the reduced data, the reduced data is The number of areas is counted by both the horizontal and vertical counting means, and from the image memory, a combination of an address and a luminance signal indicated by the number of horizontal and vertical steps or a selected address for selecting one of the color difference signals is used. Since the reduced data is accessed, the luminance signal and the two color difference signals can be arranged according to the reduced data.

In this case, by setting the number of horizontal or vertical steps and the address offset value in the horizontal and vertical step counting means in a programmable manner, an arbitrary reduction rate as required can be obtained.

Further, in the data selection circuit, the lower 2 bits of the count value of the horizontal area counting means, the lower 1 bit of the count value of the horizontal step counting means, and the lower 1 bit of the number of steps set in the horizontal step coefficient means are set. An input address value for selecting either the luminance signal or the color difference signal is obtained, and an appropriate one of the two color difference signals is selected so as not to cause an image failure according to the reduction rate. can do.

Therefore, the YC data is thinned out on the basis of the luminance signal, and the excellent effect that the color difference signal suitable for the reduced image can be selected based on the lower bits of the number of thinning steps is exerted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a thinning circuit in an image data reproducing device according to the present invention.

FIG. 2 is a block diagram showing an example of step counters 120 and 130 in FIG.

3 is a circuit diagram showing an example of a data selection circuit 140 in FIG.

FIG. 4 is a block diagram showing a schematic configuration of an image data reproducing device to which a thinning circuit of this embodiment is applied.

FIG. 5 is a block diagram showing a control circuit in the embodiment.

FIG. 6 is a block diagram showing an internal configuration of a data conversion circuit in the embodiment.

FIG. 7 is a diagram showing a data structure of a frame memory in the embodiment.

FIG. 8 is a diagram showing data development of a frame memory in the embodiment.

FIG. 9 is a diagram showing an example of thinning out data in the embodiment.

FIG. 10 is a diagram showing an example of conventional data thinning.

[Explanation of symbols]

 10 Decimation circuit 20 YC frame memory 30 Data conversion circuit 100 Horizontal area counter 110 Vertical area counter 120 Horizontal step counter 130 Vertical step counter 140 Data selection circuit 150 Data conversion circuit

Claims (4)

(57) [Claims] 1. A thinning-out method in an image data reproducing apparatus, wherein dot-sequential YC data obtained by expanding a luminance signal and two color difference signals at a predetermined ratio is stored in an image memory, and the data is thinned out from the image memory to read out reduced data. In the circuit
The circuit includes a horizontal area counting means for counting the number of horizontal areas of reduced data in the YC data expanded in the image memory, and a number of vertical areas of reduced data in the YC data expanded in the image memory. Vertical area counting means, horizontal step counting means for counting the number of horizontal steps of reduced data of the YC data expanded in the image memory to obtain a horizontal address, and reduced data of the YC data expanded in the image memory Vertical step counting means for counting the number of vertical steps to obtain a vertical address, a selection of a luminance signal or a color difference signal from the data read at the number of steps counted by the horizontal step counting means, and two color difference signals And a data selection unit for outputting a selection address for selecting one of the horizontal step meters. Horizontal address from the means, thinning circuit in the image data reproduction apparatus characterized by accessing the image memory in vertical address and the address consisting of selected address from the data selection means from said vertical step counting means. 2. The thinning circuit in the image data reproducing apparatus according to claim 1, wherein the horizontal step counting means and the vertical step counting means are capable of programmable setting of respective step numbers and address offset values. In addition, the adder means for sequentially adding the total number of steps up to the previous time and the set number of steps, and the address setting means for outputting the added value from the adder means as an address, the address offset value being programmable Image data comprising a settable address setting means and a latch means for latching and outputting the address value from the address setting means and supplying the address value as the total number of steps to the adding means. Thinning circuit in the playback device. 3. The thinning circuit in the image data reproducing apparatus according to claim 1, wherein the data selecting means includes the lower 2 bits of the count value of the horizontal area counting means and the lower order of the count value of the horizontal step counting means. 1 bit,
Further, the lower 1 bit of the number of steps set in the horizontal step counting means is input to output a selection address for selecting either the luminance signal or the color difference signal and the two color difference signals. A thinning-out circuit in an image data reproducing apparatus. 4. The thinning circuit in the image data reproducing device according to claim 3, wherein said data selecting means is configured to output one of a luminance signal and a color difference signal based on lower one bit of a count value of said horizontal area counting means. Of an output line for outputting a selection address for selecting, a first AND circuit for ANDing the lower 1 bit and the lower 2 bits of the count value of the horizontal region counting means, and the first AND circuit of the first AND circuit. A second AND circuit that ANDs the output and the inverted value of the lower 1 bit of the step number set in the horizontal step counter, the lower 1 bit of the same step number and the lower 1 of the count value of the horizontal step counting means. The third to AND the bits
And an OR circuit for calculating a logical sum of the second AND circuit and the third AND circuit and outputting the selected OR as a selection address for selecting one of the color difference signals. Thinning circuit in the data reproducing device.