KR100517367B1 - Error Diffusion Processing Circuit of Plasma Display Panel - Google Patents

Abstract

The present invention converts an n-bit original pixel video signal into an m (= n-1) bit output video signal, removes data in a section where the horizontal sync or vertical sync signal is "0", and removes the original pixel video signal and the output video. An error diffusion processing circuit of a PDP in which a pseudo halftone display is performed by distributing an error amount between signals to adjacent pixels.

In the present invention, when the n-bit original pixel video signal is error spread output, the horizontal invalid data removal circuit 110 removes data in a section where the horizontal sync signal is "0", and a vertical sync signal is output from the error spread output. A vertical invalid data removal circuit 111 for removing data of the section " 0 ", an LSB detection circuit 102 for detecting an LSB from an image signal from which the invalid data has been removed, and one line past the original pixel An upper line LSB delay circuit 103 that weights an LSB value to the detected LSB value, and a left dot LSB delay circuit 104 that weights an LSB value generated one dot earlier than the original pixel to the detected LSB value; OR gate 105 for outputting an error signal by performing an OR operation on the output signals of the upper line and the left dot LSB delay circuits 104 and 104, and the error signal of the OR gate 105 as the source signal. Is diffused by adding to pixels Consists of a circuit 107, to remove the LSB value in the error diffusion output signal of the addition circuit 107 is m (= n-1) bit, LSB removal circuit 108 that converts the output.

Description

Error Diffusion Processing Circuit of Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error diffusion processing circuit of a plasma display panel (hereinafter referred to as " PDP "). In particular, an n-bit original pixel video signal is converted into an m (= n-1) bit output video signal and horizontal synchronization ( Data in the section where the HSYNC) signal or the VSYNC signal is "0" is removed, and the pseudo halftone display is performed by distributing the error amount between the original pixel image signal and the output image signal to adjacent pixels that have not yet been processed. Therefore, the present invention relates to an error diffusion processing circuit of a PDP that compensates for deterioration in image quality.

As is well known, the PDP obtains a discharge by adjusting a voltage applied between vertical and horizontal electrodes of a cell constituting a pixel, and the amount of light discharged is adjusted by changing the length of the discharge time in the cell.

The full screen includes a write pulse for inputting a digital image signal to the vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining the discharge, and a stop for discharging the discharged cell. It is obtained by driving a matrix type by applying an escape pulse.

In addition, the gray level required for displaying an image is realized by varying the length of time that individual cells are discharged within a given time required to display the entire image.

At this time, the brightness of the screen is determined by the brightness when each cell is driven to the maximum, and in order to increase the brightness, the discharge time of the cell must be kept as long as possible within a given time for configuring a screen.

In addition, the contrast, which is a difference in contrast, is determined by the brightness and the brightness of the background. In order to increase the contrast, it is necessary to not only darken the background but also increase the brightness.

For example, an image digital signal required for displaying an image of 256 gray levels requires an 8-bit signal for each of RGB, and a cell discharge time should be kept as long as possible in order to obtain required luminance and contrast.

On the other hand, the sub-field scanning method which is currently attracting the most attention as a gray scale implementation method of the AC PDP is that the 8-bit digital video signal has the same weight bit between the MSB (highest bit) to LSB (lowest bit). After collecting, the MSB scans for the time T and the lower bits in order of bit closest to the MSB for T / 2, T / 4, ..., T / 128, respectively, to form a sub picture, and is emitted from each sub picture. By using the integrated effect of the eye on light, 256 gray levels are realized.

Here, since the PDP must be driven in a matrix manner, there is a limitation in that a write pulse cannot be applied to one or more scan electrodes at a time for a given address electrode, and thus the scan electrodes must be driven at different times.

Therefore, in order to construct each subscreen, a time (address period) for scanning all scan electrodes is required, and each cell discharges only during a time (sustain period) reduced by the scanning time from the time allocated to the average subscreen. It can be maintained. The address period increases as the number of scan electrodes increases. During this time, since the discharge cannot be maintained, the sustain period decreases, which causes a decrease in luminance and contrast of the PDP. Therefore, the address period needs to be reduced as much as possible. have.

Accordingly, in recent years, even when an original pixel video signal quantized with n bits is input, a driving method of converting an output video signal into m (≤ n-1) bits and displaying only m bits in the PDP without displaying all bits is used.

However, such a bit conversion driving method has a disadvantage in that the image quality is degraded because the luminance is increased by reducing the number of bits of the handling signal but the gray scale display is reduced.

To compensate for this drawback, Japanese Patent Application Laid-Open No. 7-64501 distributes an error amount between an original pixel image signal and an output image signal to adjacent pixels that have not yet been processed to compensate for image degradation by performing pseudo halftone display. One error diffusion processing circuit has been proposed.

Hereinafter, the operation and effect of the error diffusion processing circuit proposed in Japanese Patent Laid-Open No. 7-64501 will be described with reference to FIGS. 1, 2, and 4.

When the pixel in the jth column of the i-th line (row) of the PDP is called the original pixel Ai, j, Ai, j-h is a pixel higher than the original pixel by h lines, and Ai, j-d is a pixel on the left side of the d column than the original pixel.

First, an n-bit video signal of the original pixels Ai and j is input to the video input terminal 1, and the error detection circuit 2 detects error amounts Kd and Kh for a predetermined weight.

Then, the h line delay circuit 3 outputs the reproduction error Ej-h generated in the h line past than the original pixel Ai, j to the error amount Kh and outputs the output signal in the vertical addition circuit 4. It adds to the pixel Ai, j.

Then, the d dot delay circuit 5 outputs the reproduction error Ei-d generated in the past d dots from the original pixels Ai, j to the error amount Kd, and outputs the output signal by the horizontal addition circuit 6 to the original. The pixel is added to Ai, j.

Next, the n-bit quantized spread output signal spread by adding the error in the h line delay circuit 3 and the d dot delay circuit 5 is converted into m (≤ n-1) bits in the bit conversion circuit 7. And output to the video output terminal 8.

Therefore, even if the error is weighted and diffused to the video signal inputted to the video input terminal 1, and the gray scale is implemented with fewer bits than the original video signal, the pseudo halftone display is performed by the error diffusion to compensate for the deterioration in image quality.

However, such a conventional error diffusion processing circuit has the following problems.

first; If the bit difference between the n-bit original pixel video signal input to the video input terminal 1 and the m-bit output video signal output to the video output terminal 8 is two or more bits, halftone display is performed through error diffusion. Even if it is done, there is a problem that the image is displayed unnaturally and the gradation display decreases, so that the image quality deteriorates.

second; As shown in FIG. 1, the use of two adding circuits, namely, a vertical adding circuit 4 and a horizontal adding circuit 6, has a problem that the calculation speed is slow and the cost is high.

third; Gradation that can realize the original pixel video signal even when the bit difference between the n-bit original pixel video signal input to the video input terminal 1 and the m-bit output video signal output to the video output terminal 8 is 1 bit. In the case of the peak value of, the error amount of the adjacent pixels is weighted and diffused, thereby causing a bit overflow.

For example, in a PDP implementing 256 gray scales (0 to 255), as shown in FIG. When the reproduction error occurred in the d dot past is implemented at the level 254, when the error amount of the video signal Ai, j is weighted to the adjacent video signals Ai, j + h and Ai + d, j as shown in FIG. This is because 256 levels that cannot be implemented are calculated.

fourth; Since the error spreads to invalid data in the section where the HYNC signal is "0" and the section where the VSYNC signal is "0", the image quality deterioration is caused when the error of the pixel located at the top line is spread. there was.

Therefore, the present invention has been proposed to solve the above-described problems of the prior art, and the circuit can be simplified by using only one addition circuit by limiting the bit difference between the original pixel video signal and the output video signal to 1 bit. Enables high-speed calculations, reduces cost, and installs an overflow prediction circuit to prevent bit overflow that may occur when the input video signal is at peak gradation, and the HYNC signal is "0." The purpose of the present invention is to prevent deterioration of image quality by removing invalid data in a section in which the " in " and the VSYNC signal are " 0 ".

The technical means of the present invention for achieving this purpose is to remove the horizontal invalid data for removing the data of the section where the horizontal synchronization signal is "0" from the signal in which the n-bit original pixel video signal is error-diffused through the backward addition circuit Circuit; A vertical invalid data removal circuit for removing data in a section where the vertical synchronization signal is "0" from the error spread signal; An LSB detection circuit for detecting a least significant bit LSB in an image signal from which invalid data is removed through horizontal and vertical invalid data removal circuits; an upper line LSB delay circuit that weights an LSB value generated one line past the original pixel to an n-bit original pixel video signal; a left dot LSB delay circuit that weights an LSB value generated one dot past the original pixel to an n-bit original pixel video signal; A logic element for ORing the output signals of the upper line and left dot LSB delay circuits to output an error signal; An addition circuit for adding and diffusing an error signal of the logic element to the n-bit original pixel video signal; LSB elimination circuit which removes LSB value from error diffusion output signal of this addition circuit and converts it into m (= n-1) bits and outputs it.

Preferably, the method further includes an overflow estimating circuit that blocks an error signal of a logic element by anticipating a bit overflow when the original pixel is a peak value represented by n bits.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an error diffusion processing circuit according to the present invention. When the error diffusion of an n-bit original pixel image signal input to the image input terminal 101 through the addition circuit 107 is performed, horizontal synchronization is performed. A horizontal invalid data removal circuit 110 for removing data in a section in which a (HSYNC) signal is "0" and a vertical synchronization (VSYNC) signal receiving the n-bit original pixel video signal through the addition circuit 107; The least significant bit LSB in the video signal from which invalid data is removed through the vertical invalid data removal circuit 111 and the horizontal and vertical invalid data removal circuits 110 and 111. A LSB detection circuit 102 for detecting a signal, an upper line LSB delay circuit 103 for weighting an LSB value generated one line past the original pixel to the n-bit original pixel image signal, and the n-bit original pixel image 1 dot past than the original pixel in the signal OR gate 105 for outputting an error signal by performing an OR operation on the left dot LSB delay circuit 104 that weights the generated LSB value and the output signals of the upper line and left dot LSB delay circuits 103 and 104. And an overflow predicting circuit 106 for blocking an error signal of the OR gate 105 in anticipation of a bit overflow when the original pixel is a peak value represented by n bits, and an error signal of the OR gate 105. Is added to the n-bit original pixel video signal and diffused, and the LSB value is removed from the error diffusion output signal of the addition circuit 107 and converted into m (= n-1) bits to convert the image output terminal. It consists of the LSB removal circuit 108 which outputs to (109).

The operation and effect of the present invention configured as described above will be described with reference to FIGS. 2 to 4 as follows.

First, when the n-bit video signal of the original pixel Ai, j is input to the video input terminal 101 and error-produced through the addition circuit 107, the horizontal invalid data removal circuit 110 generates a horizontal synchronizing (HSYNC) signal. The data of the section where "0" is removed is removed, and the vertical invalid data removal circuit 111 removes the data of the section where the VSYNC signal is "0".

The LSB detection circuit 102 detects the LSB for predetermined weighting from the video signal from which invalid data is removed through the horizontal and vertical invalid data removal circuits 110 and 111.

Then, the upper line delay circuit 103 weights the LSB value generated one line past the original pixel Ai, j to the OR gate 105 by weighting the LSB detected by the LSB detection circuit 102, and outputs a left dot delay. The circuit 104 weights the LSB value generated one dot past the original pixel Ai, j to the LSB detected by the LSB detection circuit 102 and outputs it to the OR gate 105.

Next, the OR gate 105 performs an OR operation on the output signals of the upper line delay circuit 103 and the left dot LSB delay circuit 104 and outputs an error signal based on a past LSB value to the overflow prediction circuit 106. do.

In this case, the overflow prediction circuit 106 predicts a bit overflow when the original pixel input from the image input terminal 101 to the addition circuit 107 is a peak value represented by n bits, and the error prediction signal of the OR gate 105 is estimated. Block it.

For example, in a PDP that implements 256 gradations (0 to 255), as shown in FIG. 4A, when all four adjacent pixel video signals have 255 levels, LSB values generated in the past of one line in the video signal Ai, j and When the LSB value generated in the past of one dot is weighted and implemented at 254 levels, as shown in FIG. 4 (C), the overflow prediction circuit 106 causes the video signal Ai to be adjacent to the adjacent video signals Ai, j + h and Ai + d, j. Do not weight the LSB of, j.

That is, if the original pixel video signals Ai, j + h and Ai + d, j are " 255 ", and the error signal output from the OR gate 105 is " 1, " Since 256 "is calculated, the overflow prediction circuit 106 makes the error signal output from the OR gate 105" 0 "to prevent bit overflow when the original pixel image signal is" 255 ".

On the other hand, the addition circuit 107 adds and diffuses the error signal of the OR gate 105 which has passed through the overflow predicting circuit 106 to the original pixel, and the error diffusion output signal of the addition circuit 107 is horizontal and When output through the vertical invalid data removal circuits 110 and 111, the LSB removal circuit 108 removes the LSB value, converts it into m (= n-1) bits, and outputs it to the image output terminal 109.

Therefore, even if the error is weighted and diffused to the input n-bit video signal, and the gray scale is implemented with m (= n-1) bits smaller than the original video signal, pseudo image halftone display is performed by the error diffusion to compensate for the deterioration in image quality.

As described above, according to the present invention, the bit difference between the original pixel image signal and the output image signal is limited to 1 bit so that only one addition circuit is used, thereby simplifying the circuit, enabling high-speed calculation, and reducing the cost. By installing an overflow prediction circuit, it is possible to prevent bit overflow that may occur when the input image signal is a peak value of the gradation that can be implemented, and the section where the horizontal synchronization signal is "0" and the vertical synchronization signal is "0". By removing the invalid data of the interval, there is an effect of preventing the deterioration of the image quality that may be caused when the error of the pixel located in the top line.

1 is a block diagram of an error diffusion processing circuit of a conventional plasma display panel.

2 is an explanatory diagram of coordinate positions of pixels.

3 is a block diagram of an error diffusion processing circuit of the plasma display panel according to the present invention;

4 is an error diffusion processing state diagram according to the prior art and the present invention.

*** Explanation of symbols for the main parts of the drawing ***

101: video input terminal 102: LSB detection circuit

103: upper line LSB delay circuit 104: left dot LSB delay circuit

105: OR gate 106: overflow prediction circuit

107: addition circuit 108: LSB removal circuit

109: video output terminal 110: horizontal invalid data removal circuit

111: vertical invalid data removal circuit

Claims (2)

a horizontal invalid data removal circuit for removing data in a section where the horizontal synchronization signal is "0" from a signal in which an n-bit original pixel video signal is error-diffused through a subsequent addition circuit; A vertical invalid data removal circuit for removing data in a section in which a vertical synchronization signal is "0" from the error spread signal; An LSB detection circuit for detecting a least significant bit (LSB) in an image signal from which invalid data is removed through the horizontal and vertical invalid data removal circuits; An upper line LSB delay circuit which weights the LSB value generated one line past the original pixel to the n-bit original pixel video signal; A left dot LSB delay circuit for weighting the n-bit original pixel video signal with LSB values generated one dot past the original pixel; A logic element configured to OR the output signals of the upper line and left dot LSB delay circuits to output an error signal; An addition circuit for adding and diffusing an error signal of the logic element to the n-bit original pixel image signal; And an LSB elimination circuit for removing the LSB value from the error spreading output signal of the addition circuit and converting the LSB value into m (= n-1) bits to output the LSB value. The method of claim 1, And an overflow estimating circuit for blocking an error signal of the logic element in anticipation of a bit overflow when the original pixel is at a peak value represented by n bits.