JPH05323913A - Image data processor - Google Patents

Abstract

PURPOSE:To enable display without the deterioration of a signal with a simple circuit constitution in an LCD display device having a signal source of a digital RGB signal. CONSTITUTION:The data compression part of an image data processor is provided with a decoder part 51 decoding respective R,G and B to outputs of four kinds and a decoder part 52 decoding so as to select adequate colors (gradation) of sixteen kinds from the outputs of R, G and B decoded by the decoder part 51, and converts one image element twelve bits data of (2<4>)<3>=4096 colors into display data of 2<4>=16 gradation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing device used in a liquid crystal television, a liquid crystal projector and the like, and more particularly to an image data processing device for converting a digital RGB signal into a black and white gradation signal.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal television, an analog video signal amplified by a video amplifier circuit is converted into, for example, 3-bit digital data by an A / D conversion circuit, and the liquid crystal panel is driven to display by this digital data. There is. Then, the color video signal may be displayed on the monochrome liquid crystal display device. Therefore, when a color image is displayed on a monochrome liquid crystal display device, when the signal source is an analog video signal, it can be displayed with the configuration of FIG.
FIG. 10 shows a liquid crystal display device 1 for displaying a video signal of a signal source.
It is a figure which shows 0. As shown in this figure, the luminance signal (Y) of the video signal is separated by the trap circuit 11 and the LCD
It is input to the controller 12. LCD controller 1
The reference numeral 2 A / D-converts the separated luminance signal and outputs a control signal for controlling the liquid crystal panel (LCD) 15 to the LCD drivers 13 and 14. LCD driver 13, 1
Reference numeral 4 drives the liquid crystal panel 15 for gradation display according to a control signal from the LCD controller 12. 11 is a diagram showing the liquid crystal display device 20 when the signal source is a digital RGB signal. When the signal source is a digital RGB signal,
Since the luminance signal (Y) has to be generated from the digital RGB signal, the digital RGB signal is first input to the DA converter 21 and is D / A converted into an analog RGB signal by the DA converter 21 as shown in FIG. Then, from the analog RGB signal that has been D / A converted to RGB
The encoder 22 extracts the luminance signal and inputs it to the LCD controller 12.

[0003]

However, in such a conventional image display device, when a color image is displayed on a monochrome LCD, when the signal source is an analog video signal, it is displayed by the configuration of FIG. Is possible, but
If the signal source is a digital RGB signal, the signal is once D / A converted by a DA converter 21 into an analog RGB signal as shown in FIG.
The encoder 22 must generate the luminance signal. In this case, in the LCD controller 12, the luminance signal once converted into an analog signal is A / D converted again to drive the LCD driver with a digital signal. Therefore, RGB
Since the luminance signal conversion is performed in analog, not only signal deterioration is unavoidable, but also a circuit for D / A conversion and A / D conversion is required, which complicates the circuit configuration. Therefore, it is an object of the present invention to provide an image data processing device which enables display without signal deterioration with a simple circuit configuration in a liquid crystal display device using digital RGB signals as a signal source.

[0004]

The invention according to claim 1 is
In order to achieve the above object, in an image data processing device for generating a luminance signal from a digital RGB signal and displaying the data, a first RGB data signal is divided into a predetermined combination for each of R, G, B, and data is compressed. A compression means and a second compression means for compressing the data by selecting a predetermined combination of RGB from the R, G, B compression data compressed by the first compression means.

[0005]

According to the first aspect of the invention, first, the digital RG is used.
The B signal is data-compressed by the first compression means by dividing it into R, G, B divided into a predetermined kind of combination, and then by the second compression means, from the compressed R, G, B compressed data to RG.
Data compression is performed by selecting a predetermined type as the combination of B. Therefore, in a liquid crystal display device using a digital RGB signal as a signal source, it is possible to perform display without signal deterioration with a simple circuit configuration.

[0006]

EXAMPLES Examples will be described below with reference to FIGS. 1 to 9 are views showing an embodiment of the present invention, in which R
This is an example applied to an image data processing device for converting data from 4-bit GB digital display data into 4-bit monochrome display data. FIG. 1 is an overall configuration diagram of the image data processing device 30. In FIG. 1, the image data processing device 30 is
4-bit RGB signal for R, G, B 1 pixel (pixel)
The register unit 31 which stores the minutes and converts it into the 12-bit display data, and the 12-bit data that is grouped by RGB by the register unit 31 (here, there are 3 combinations of 4 bits for RGB, so (2 ⁴ ) ³ colors are selected. (Which can be expressed) data compression unit 32 for compressing data into 2 ⁴ gradations, and data compression unit 3
Black and white 4-bit display data compressed by 2
Further, it is composed of a gradation circuit 33 for reducing display data of 3 bits.

FIG. 2 shows RGB signals of 4 bits for each of R, G and B signals.
FIG. 3 is a circuit configuration diagram of a register unit 31 that stores one pixel.
In FIG. 2, the register unit 31 uses the clock 1 to output the display data of each RGB 4 bits input through the data bus A.
Register 41 that shifts at the timing of (FIG. 3), register 42 that shifts 4-bit output from register 41 at the timing of clock 1, and 4bi from register 42
A register 42 that shifts the t output at the timing of clock 1, a register 43 and a register 43 that shifts the 4-bit output from the register 42 at the timing of the clock 1
4 bit output from the register 44 that outputs the 4 bit output from the register 42 as a 4 bit R signal output R ₀ , R ₁ , R ₂ , R ₃ at the timing of the clock 2 (FIG. 3) and the 4 bit output from the register 42 at the timing of the clock 2 G signal output G ₀ , G ₁ , G ₂ ,
It is composed of a register 45 for outputting as G ₃ , and a register 46 for outputting the 4-bit output from the register 41 as B signal outputs B ₀ , B ₁ , B ₂ , and B ₃ at the timing of clock 2.

By this register unit 31, each RGB 4bi
The display data of t is stored in one set of R, G, B and converted into 12-bit data. For example, as shown in FIG. 3, 4-bit display data R1, G1, B1 are shifted from the data bus A at clock 1 and output as 12-bit data for one pixel on the data bus B at the timing of clock 2.

FIGS. 4 and 5 are circuit configuration diagrams of a data compression unit 32 for compressing 1-bit 12-bit data into display data of 2 ⁴ = 16 gradations, and FIG. 4 is input from the data bus B ( 2 ⁴ ) ³ = 4096 color data is 2 ⁴ = 16
FIG. 5 is a circuit diagram showing a matrix circuit 50 which converts the display data of gradations and outputs it from the data bus C. FIG.
FIG. 6 is a circuit diagram showing a 4-bit decoding circuit 60 which converts 16-bit data input therein into a 4-bit code and outputs the 4-bit code from a data bus D. This 4-bit code becomes 4-bit display data.

In FIG. 4, the matrix circuit 50 is
Decoder unit 51 that decodes each of R, G, and B so as to drop each to four types of outputs, and 16 types of appropriate colors (gradations) from the outputs of R, G, and B decoded by the decoder unit 51 Decoder unit 52 for decoding to select
(See FIG. 4).

The decoder section 51 includes R (red) and G
(Green) and B (blue) are constituted by the same circuit of three systems. Here, only the circuit for R 4-bit data of the three systems is shown as a representative. The decoder unit 51 includes an AND array (see FIG. 4) that outputs the R signal inputs R ₀ , R ₁ , R ₂ , and R ₃ input from the data bus B and their inverted signals in an arbitrary combination, and an AND array. It is composed of OR gates 53, 54, 55 and 56 which take the OR logic of the output from and output as decoded outputs r ₀ , r ₁ , r ₂ and r ₃ .

FIG. 6 is a truth table showing the operation function of the decoder section 51. As shown in this table, 4-bit data R ₀ , R ₁ , R ₂ , R from the data bus B to the decoder unit 51
_{When 3} is input, it is decoded by the matrix in the decoder unit 51 and R decode outputs r ₀ , r ₁ , r ₂ and r ₃ are output. That is, the decoder unit 51 inputs 2 ⁴ = 16 as the R 4-bit data R ₀ , R ₁ , R ₂ , and R _3.
Inputs of various types are output in four stages r ₀ shown in FIGS.
The data is dropped to r ₁ , r ₂ , r ₃ . Here, in the present embodiment, the R decoded outputs r ₀ , r ₁ , r ₂ , r ₃ are fine in the brightest and darkest areas and coarse in other areas (II and III are better than I and IV in FIG. 6). However, it is possible to freely set the combination of the above matrix, for example, R 4 bit data R ₀ ,
R decode outputs r ₀ , r ₁ , r ₂ , for R ₁ , R ₂ , R ₃ ,
the r ₃ may be equal four stages.

The decoder unit 52 is the decoder unit 5
The R, G, and B respectively decoded outputs r ₀ , r ₁ , r ₂ , r ₃ , g ₀ , which are compressed in four stages (4 types) by ₁ ,
It is composed of an AND array (see FIG. 4) which outputs a combination of g ₁ , g ₂ , g ₃ , b ₀ , b ₁ , b ₂ and b ₃ with an arbitrary logical product. The decoder unit 52 converts the R, G, B4 ³ color data into 4 ² = 16 gradation display data according to the following procedure. That is, as shown in the upper L ₉ ~L ₁₅ as one, colors always required and the array of 16bit code output line L ₀ ~L ₁₅ as shown in FIG. 4 R
When GB is full (that is, when there are 8 colors of the darkest R, G, B, and the combination thereof) and when the lowest L ₀ is true black, it is first output, and from the remaining L ₉ to LR ₀ The color of is output until it becomes 16 bits. That is, in this embodiment, L _{9 to} L ₁₅ that display so-called multi-colors composed of primary colors such as red, blue, and yellow, and L _{0 of} true black are first selected, and the rest are selected to be arbitrary intermediate values. I am trying to drop it to 16 bits. By changing the matrix of the decoder unit 51 and the decoder unit 52 (FIG. 4), it is possible to easily add a function for selecting the primary color priority mode, the halftone priority mode, each color priority mode, or the like.

As described above, the matrix circuit 50 allows one
The data of 12 bits of pixels can be converted into the data of 4 bits, whereby the data of 2 ⁴ (R) × 2 ⁴ (G) × 2 ⁴ (B) = 4096 colors can be converted into the display data of 2 ⁴ = 16 gradations.

FIG. 5 shows 16bi input from the data bus C.
The decoding circuit 60 converts t data into a 4-bit code and outputs it as display data to the data bus D. FIG. 7 is a truth table of the decoding circuit 60.

In FIG. 5, the decoding circuit 60 has 16
register 61 for converting bit input to 4 bit code,
62 and OR gates 63, 64 and 65.
From the data bus C to the decoding circuit 60, for example, L ₁₅
When the data of [1] is input, the 4-bit code of [1111] is output by being encoded by the decoding circuit 60. For example, when the data of L ₁₄ is [1] is input,
The decoding circuit 60 outputs a 4-bit code of [1110] (see FIG. 7). An inverter (not shown) is provided for each bit on the data bus C, and the data input from the data bus C to the decoding circuit 60 is
It is assumed that the data obtained by inverting the data L _{0 to} L ₁₅ is input (the truth table of FIG. 7 shows the data L _{0 to} L ₁₅ not passing through the inverter).

As described above, the data compression section 32 including the matrix circuit 50 and the decoding circuit 60 causes R, G, B (2
⁴ ) Data of ³ = 4096 colors is converted into display data of 2 ⁴ = 16 gradations.

By the way, if the LCD driver is capable of displaying 16 gradations, the gradation circuit 33 (FIG. 8) described below is not necessary, and the output of the data compression section 32 is L level.
Although it can be input to the CD driver, when the LCD driver performs 8-gradation display, the gradation circuit 33 is used to perform pseudo 16-gradation display.

FIG. 8 is a circuit diagram of the gradation circuit 33, and FIG. 9 is an operation function diagram of the gradation circuit 33. In FIG. 8, the gradation circuit 33 further reduces the compressed 4-bit display data D ₀ , D ₁ , D ₂ , D ₃ to 3-bit data Y ₁ , Y ₂ , Y ₃ without reducing the image quality as much as possible. It is a circuit for doing. The gradation circuit 33 includes NAND gates 71, 72, 73, an inverter 74, an OR gate 75,
EX-NOR gates 76 and 77 and EX-OR gate 7
The NAND gate 72 receives a signal FLM which is inverted every frame.

When the frame inversion signal FLM supplied to the gradation circuit 3 is [0], 4-bit input data D ₁ ,
D _2, D _3, D upper bits of the data D ₂ of the _4, D _3, D ₄ respectively as output data Y _1, Y output as _2, Y ₃ (deleted data D ₁ of the least significant bit), the When the signal FLM is [1], the input data is "+1" as shown in FIG.
After that, the upper 3 bits of data are output as Y ₁ , Y ₂ , and Y ₃ . Since the number of gradations is small when gradation display is performed with 3-bit digital data, the gradation circuit 33 changes the level of A / D conversion, and when viewed from the average value of 2 frames, gradation equivalent to 4 bits is obtained. I am trying to get it.

As described above, the data compression unit 32 of the image data processing apparatus 30 of this embodiment decodes each of R, G and B so as to drop into four types of outputs, and the decoder unit 51 and the decoder unit 51. R, G, decoded by
A decoder unit 52 that decodes so as to select 16 kinds of appropriate colors (gradations) from the output of B is provided.
Since 2-bit (2 ⁴ ) ³ = 4096 color data is converted to display data with 2 ⁴ = 16 gradations, it is possible to convert a signal as a digital signal without passing through an analog circuit. Therefore, since the color / monochrome data conversion is performed only by the digital circuit without passing through the analog circuit, the circuit configuration can be simplified to about one chip of the gate array. Further, since only the digital signal is processed without converting the digital signal into the analog signal, it is possible to display without deterioration of the signal.

In this embodiment, RGB of 4 bit parallel is used.
Although an example of data compression of a signal is shown, it is needless to say that the data compression can be performed by a similar method even for an RGB signal having a larger number of bits.

In the present embodiment, the decoder unit 51 drops R, G, and B into four types of output, and the decoder unit 52 drops the data into 16 gradations. Of course, the number of stages is not limited. Further, the data compression in the decoder unit 52 may be performed first, and then the data compression in the decoder unit 51 may be performed.

The register section 31 and the matrix circuit 5 are also provided.
It is needless to say that the circuit, matrix, the number of gates, and the type of 0, the decoding circuit, etc. are not limited to those in the above-described embodiments.

[0025]

According to the first aspect of the present invention, the first RGB compression means divides the digital RGB signals into R, G, and B combinations of a predetermined type, and compresses the data, and the first compression means. The color / monochrome data conversion is performed only by the digital circuit without using the analog circuit, since the second compression means for selecting a predetermined combination of RGB from the compressed R, G, B compressed data and compressing the data is provided. Can be done
The circuit configuration can be greatly simplified, and since only digital signals are converted, signal deterioration can be prevented.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an image data processing device.

FIG. 2 is a circuit diagram of a register unit of the image data processing device.

FIG. 3 is a timing chart of a register unit of the image data processing device.

FIG. 4 is a circuit diagram of a matrix circuit of the image data processing device.

FIG. 5 is a circuit diagram of a decoding circuit of the image data processing device.

FIG. 6 is a truth table of a decoding unit of the image data processing device.

FIG. 7 is a truth table of a decoding circuit of the image data processing device.

FIG. 8 is a circuit diagram of a gradation circuit of the image data processing device.

FIG. 9 is a diagram showing an operation of a gradation circuit of the image data processing device.

FIG. 10 is a block configuration diagram of an image data processing device for displaying image data on an LCD by a video signal.

FIG. 11: LC image data by digital RGB signals
It is a block block diagram of the image data processing apparatus displayed on D.

[Explanation of symbols]

 30 image data processing device 31 register unit 32 data compression unit 33 gradation circuit 50 matrix circuit 51, 52 decoder unit 60 decoding circuit

Claims (1)

[Claims] 1. An image data processing apparatus for generating a luminance signal from a digital RGB signal and displaying the data, wherein the digital RGB signal is divided into a predetermined combination for each of R, G and B, and the data is compressed. Image data comprising: a second compression unit that selects a predetermined combination of RGB from the R, G, and B compressed data compressed by the first compression unit and compresses the data. Processing equipment.