JPH06105263A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To cancel a phase deviation between a picture signal and a sampling clock in a display driving circuit by adjusting the phase of the clock signal corresponding to the transfer delay of a video signal on a video signal line. CONSTITUTION:A shift register 17 supplies a signal for sampling the video signal transmitted on a video signal line 11 being a signal line which transmits the video signal to the signal line of an active matrix part. A clock signal line 20 is the signal line which transmits a clock signal for driving the shift register 17 to the shift register 17, and more than one delay means 21 are provided on the clock signal line 20, and the phase of the clock signal transmitted on the clock signal line is delayed in a prescribed time. The delay time of the delay means 21 is adjusted corresponding to the transfer delay of the video signal on the video signal line 11, and the phase deviation between the video signal and the sampling signal outputted from the shift register can be canceled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which eliminates the phase shift of a drive circuit in an active matrix driven liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display drive circuit as shown in FIG. 6 is known as a liquid crystal display drive circuit for displaying a television image using liquid crystal. Figure 6
In the figure, 10 is an input signal terminal, 11 is a video input signal line, 12 is a video input signal sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a sync separation circuit, 16 is a clock generation circuit, and 17 is Horizontal scan shift register, 18 is vertical scan shift register, 1
Reference numeral 9 is a vertical pixel line signal line.

Next, the outline of the operation will be described. When the video input signal including the sync signal is supplied from the input signal terminal 10, the sync separation circuit 15 separates the sync signal from the video input signal and supplies the sync signal to the clock generation circuit 16. The clock generation circuit 16 multiplies the supplied synchronization signal to generate a sample clock of the video input signal and inputs it to the horizontal scanning shift register 17. A shift pulse SP is added to the horizontal scanning shift register 17, the sample clock of the video input signal is shifted according to the shift pulse SP, and the sampling switch element 12 is moved.
To be supplied in sequence. During this period, the video input signal from the input signal terminal 10 is propagated through the video input signal line 11, and the sampling switch element 12 is turned on by the sample clock from the horizontal scanning shift register 17, and each vertical pixel line signal line is turned on. Taken in 19. The pixel signal taken into the vertical pixel line signal line 19 is controlled by the vertical scanning signal supplied from the vertical scanning shift register 18
3 is taken into each liquid crystal cell 14 and the pixel of the liquid crystal display at the corresponding position is displayed according to the pixel signal of the video signal.

By the way, according to the description of Japanese Patent Application Laid-Open No. 2-309773, a liquid crystal display drive circuit as shown in FIG. 6 is used for displaying an image of a computer or the like.
It has been proposed that the phase shift of the sampling drive signal with respect to each pixel signal lowers the resolution of the image, and a solution therefor is proposed. That is, pixels forming a television image have a certain degree of correlation between adjacent pixels, and even if a video signal is captured and displayed in a liquid crystal cell at a pixel position where the video signal is displaced, the phase difference between the video signal and the drive signal causes Although the deterioration of resolution is not so problematic, when such a liquid crystal display device is used as a display device for displaying a display image from a computer, the computer image has no correlation between pixels such as a character image and a sampling drive signal. The phase shift of 1 reduces the resolution of the image and is not practical. Therefore, JP-A-2-3097
In the "Liquid Crystal Display Device" described in Japanese Patent Publication No. 73, a proposal has been made to provide a liquid crystal display drive circuit with a phase adjustment circuit for adjusting the phase of a drive clock signal of a shift register used for sampling an input signal.

FIG. 7 is a circuit diagram showing a liquid crystal display drive circuit provided with a phase adjustment circuit for a drive clock signal for sampling. In FIG. 7, 10 is an input signal terminal, 11 is a video input signal line, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell,
Reference numeral 15 is a sync separation circuit, 16 is a clock generation circuit, 17 is a horizontal scanning shift register, 18 is a vertical scanning shift register, 19 is a vertical pixel line signal line, 71 is a switching control terminal, 72 is a multiplexer, and 73 is a delay circuit. is there.
These circuit elements 10 to 19 are circuit elements similar to those described with reference to FIG. 6, and the operation by each circuit element is also similar.

Here, as shown in FIG. 7, in addition to the circuit elements of the liquid crystal display drive circuit shown in FIG. 6, a phase adjusting circuit for synchronizing signals, which is composed of a plurality of stages of delay circuits 73 and multiplexers 72, is further provided. With this phase adjustment circuit, the delay time given to the driving clock signal for sampling is selected by the signal given from the switching control terminal 71 in the multiplexer 72 in which the number of stages of the delay circuits 73 connected in series is switched. Adjust the phase. As a result, the phase of the clock signal is adjusted, the phase shift with the pixel can be matched, and the image signal from the computer or the like can be displayed well.

[0007]

By the way, in the liquid crystal display drive circuit as shown in FIG. 6 and FIG. 7, as is clear from the circuit configuration, the video input signal line 11 has a large number of pixels in the horizontal direction. The sampling switch element 12 is connected in parallel. Therefore, the input capacitance (source-gate capacitance or the like) of each sampling switching element 12 is directly added to the input signal line 11 as a distributed capacitance. As a result, as shown in FIG. 8, the video input signal line 11 becomes a distributed constant circuit composed of distributed capacitance (input capacitance C of the switching element 12) and distributed resistance (wiring resistance R between the switching elements 12), and The resulting propagation delay of the video input signal occurs. Therefore, when the number of pixels in the horizontal direction is increased in order to increase the resolution of an image as in a liquid crystal display device that displays a computer image, the distribution capacitance further increases and the effect of signal propagation delay in the video input signal line is affected. growing.

For this reason, a sequential transmission delay occurs in each pixel signal transmitted through the input signal line 11 depending on the position of the sampling switching element 12, and a phase error with the sampling signal occurs depending on the position. Become. Therefore, as described with reference to FIG. 7, it is not sufficient to provide the phase adjustment circuit in the liquid crystal display drive circuit and adjust the phase of the sampling clock signal separated by the sync separation circuit at the input point of the image signal. There is a problem that the sampling clock and the image input signal are out of phase with each other in accordance with the arrangement position of the sampling switching element 12 that takes in the video input signal in the video input signal line 11 to the vertical pixel line signal line 19.

The influence of the signal propagation delay in the video input signal line 11 is caused by the horizontal pixel read control line for propagating the control signal output from the vertical scanning shift register 18 for vertical scanning. 70a-7
The same occurs at 0 m (FIG. 7). For this reason,
The video signal from the vertical pixel line signal line 19 is taken in and the pixel signal is written in the liquid crystal cell 14, a phase shift occurs in the operation timing of the pixel switch element 13, and the video signal is not written in the liquid crystal cell at a predetermined pixel position. The problem arises.

A detailed description will be given with reference to FIG. Figure 4
FIG. 6 is a circuit diagram of a liquid crystal display drive circuit for explaining a phase shift due to a signal propagation delay due to a control signal line in vertical scanning. In FIG. 4, 10 is an input signal terminal, 11 is a video input signal line, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a sync separation circuit, 17 is a horizontal scanning shift register, and 18 is vertical. The scan shift register 19 is a vertical pixel line signal line. 40a to 40m are horizontal pixel read control lines, 41 is a horizontal scanning clock generation circuit, 4
2 is a vertical scanning clock generation circuit.

FIG. 5 is a timing chart for explaining the operations of vertical scanning and horizontal scanning in the liquid crystal display drive circuit. The operation will be described with reference to the timing chart shown in FIG. When a video input signal including a sync signal is supplied from the input signal terminal 10, the sync separation circuit 15
Separates the horizontal synchronizing signal and the vertical synchronizing signal from the video input signal and supplies them to the horizontal scanning clock generating circuit 41 and the vertical scanning clock generating circuit 42. The horizontal scanning clock generation circuit 41 generates a horizontal scanning start pulse IDD and a horizontal scanning clock φ _D. The vertical scanning clock generation circuit 42 generates a vertical scanning start pulse IDS and a vertical scanning clock φ _S. The vertical scanning start pulse IDS from the vertical scanning clock generation circuit 42 instructs the start of vertical scanning, and the clock φ _S causes the vertical scanning shift register 18 to perform vertical scanning. While the i-th line is selected by the output QS _i of the vertical scanning shift register 18, the horizontal scanning start pulse IDD is used to instruct the start of horizontal scanning, and the horizontal scanning clock φ _D
To perform horizontal scanning. The output QD _j of the horizontal scanning shift register 17 samples the pixel signal of the video input signal at the j-th pixel.

In this case, in the pixel read control lines 40a to 40m, which are the control lines in the horizontal direction of the active matrix portion, as described in FIG. Read control line 40a
The input capacitance C of the pixel switch element 13 in the horizontal direction connected to ˜40 m and the wiring resistance R between the pixel switch elements form a distributed constant circuit similar to that of FIG. Therefore, the output QS _i of the control signal from the vertical scanning shift register 18 causes a propagation delay in the horizontal pixel read control line 40 _i . For example, in the timing chart of FIG. 5, the output QS _{1 of} vertical scanning is the same as QS ₁ at the first pixel in the horizontal direction, but is the same as QS _{11 at the first} pixel in the horizontal direction. during incorporation of the pixels, the QS _1N and propagation delay with respect to QS _1. When the number of pixels in the horizontal direction increases and the number of pixel switch elements 13 in the horizontal direction increases, the propagation delay due to this increases further and the pixel signal of the video input signal is not written in the pixel cell at the predetermined pixel position, resulting in missing pixels. The problem that occurs occurs.

The present invention has been made to solve such a problem, and a first object of the present invention is to achieve a phase shift depending on a signal due to a distributed resistance and a distributed capacitance of a video input signal line. Another object of the present invention is to provide a liquid crystal display device in which the phase of the sampling clock signal is adjusted and the pixel signal of the input signal is accurately displayed at the original display position at each pixel position.

A second object of the present invention is to provide a vertical scanning output Q in a liquid crystal display device having a large number of horizontal pixels.
Even if the propagation delay due to the distributed resistance and the distributed capacitance occurs in the control signal line of S _i , the influence is eliminated, and the pixel signal of the video signal is written in the liquid crystal cell at the correct display position corresponding to the pixel position. Another object of the present invention is to provide a liquid crystal display device according to the above.

[0015]

In order to achieve the above-mentioned object, a liquid crystal display device according to the first aspect of the present invention is a liquid crystal display device of active matrix driving, wherein a video signal line for transmitting a video signal ( 11: FIG. 1) and a shift register (17) for supplying a signal for sampling the video signal transmitted by the video signal line to the signal line of the active matrix section.
And a clock signal line (20) for transmitting a clock signal for driving the shift register to the shift register, and one or more clock signal lines provided on the clock signal line for determining the phase of the clock signal transmitted by the clock signal line. And a delay means (22) for delaying for a fixed time.

In the liquid crystal display device according to the second aspect of the present invention, in the active matrix drive liquid crystal display device, a video signal line (31: FIG. 3) for transmitting a video signal and the video signal line for transmitting the video signal. A shift register (17) for supplying a signal for sampling a video signal to the signal line of the active matrix portion, a scan start signal line (32) for transmitting a scan start signal for instructing the scan of the shift register, and the scan A first signal provided on a start signal line and delaying a scan start signal transmitted from the scan start signal line for a predetermined time
A delay means (33) and a second delay means (34) provided on the video signal line and delaying the video signal transmitted by the video signal line by the same time as the delay time delayed by the first delay means. It is characterized by having.

[0017]

In the liquid crystal display device according to the first aspect of the present invention, the shift register (17) is provided for the video signal transmitted by the video signal line (11: FIG. 1) which is a signal line for transmitting the video signal. A signal for sampling the video signal is supplied to the signal line of the active matrix portion. The clock signal line (20) is a signal line for transmitting a clock signal for driving the shift register (17) to the shift register, and one or more delay means (21) are provided in the clock signal line (20), The phase of the clock signal transmitted by the clock signal line is delayed by time. The delay time by the delay means (21) is adjusted corresponding to the propagation delay of the video signal in the video signal line (11), and the phase shift between the propagation delay of the video signal and the sampling signal output from the shift register. To eliminate. As a result, the phase of the clock signal is adjusted according to the propagation delay of the video signal in the video signal line (11), the phase with the pixel can be matched, and the image signal from the computer or the like can be displayed. It can be done well.

Further, in the liquid crystal display device according to the second aspect of the present invention, the shift register (17) is provided for the video signal transmitted by the video signal line (31: FIG. 3) of the signal line transmitting the video signal. ) Supplies a signal for sampling the video signal line to the signal line of the active matrix section. The scan start signal line (32) transmits a scan start signal for instructing to start scanning by the shift register (17). The scanning start signal line (32) is provided with a first delay means (33), and the first delay means (3)
0) delays the scan start signal transmitted from the scan start signal line by a predetermined time. The second delay means (3
4) is provided on the video signal line (31), and the second delay means (34) delays the video signal transmitted by the video signal line by the same delay time as the delay time by the first delay means. Let

In this way, the video signal line (3) is formed by the first delay means (33) and the second delay means (34).
The video input signal of 1) and the scan start signal of the scan start signal line (32) are delayed by the same time. As a result, due to the delay time delayed here, the signal (scan control signal) supplied to the signal line of the active matrix portion is first generated and then propagated through the signal line to read the pixel signal into the liquid crystal cell. The delay time until the pixel switch element is turned on is secured (guaranteed), and the influence of the propagation delay of the signal of the vertical scanning output propagated in the horizontal direction by the vertical scanning control signal line can be eliminated. , No pixel omission occurs.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a first embodiment of the present invention. In FIG. 1, 10 is an input signal terminal, 11
Is a video input signal line, 12 is a video input signal sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a sync separation circuit, 16 is a clock generation circuit, 17 is a horizontal scanning shift register, and 18 is vertical scanning. The shift register 19 is a vertical pixel line signal line. Further, 20 is a clock signal line, 21 is a first delay circuit, 22 is a second delay circuit, and 23 is a flip-flop that constitutes a shift register.

In the configuration of the liquid crystal display drive circuit of FIG. 1, the flip-flops 23 forming each shift stage of the horizontal scanning shift register 17 are shown for each stage.
A second delay circuit 22 is provided for each of the flip-flops 23 in each stage. Input signal terminal 10
When the video input signal including the sync signal is supplied from the sync input circuit, the sync separation circuit 15 separates the sync signal from the video input signal and supplies the sync signal to the clock generation circuit 16. The clock generation circuit 16 multiplies the supplied sync signal to generate a sample clock of the video input signal. The phase of the sample clock generated from the clock generation circuit 16 is adjusted by the first delay circuit 21 at the input point of the horizontal scanning shift register 17. After the sample clock is adjusted by the first delay circuit 21, the clock signal line 2
Propagated through 0.

The clock signal line 20 is provided with a plurality of stages of second delay circuits 22, and the plurality of stages of the second delay circuits 22 adjust the phase of the sample clock with respect to the propagation delay of the video input signal. It That is, the influence of the phase shift due to the propagation delay of the video input signal caused by the distributed resistance and the distributed capacitance in the video input signal line 11, the second delay circuit 22 provided for the flip-flop 23 of each stage of the horizontal scanning shift register 17. Adjusted by. As a result, the phase of the clock signal is adjusted for each position of the flip-flop of each stage of the horizontal scanning shift register 17 which transmits the sample clock, with respect to the propagation delay of the video input signal on the video input signal line 11. The position of the pixel signal of the video input signal and the phase of the sample clock are accurately adjusted, and the pixel signal is written in the liquid crystal cell 14 at the correct corresponding position.

The subsequent operation is similar to that of the circuit example described above. That is, the sample clock from the clock generation circuit 16 is the first delay circuit 21 and the second delay circuit 2
3, the phase is adjusted, added to the horizontal scanning shift register 17 and shifted, and sequentially supplied to the sampling switch element 12. During this period, the video input signal from the input signal terminal 10 is propagated through the video input signal line 11, and the sampling switch element 1 is driven by the sample clock from the horizontal scanning shift register 17.
2 are sequentially turned on and are taken into the respective vertical pixel line signal lines 19. The pixel signal taken in by the vertical pixel line signal line 19 is taken in by each liquid crystal cell 14 through the image switch element 13 controlled by the vertical scanning signal supplied from the vertical scanning shift register 18, and the pixel signal of the corresponding position is read. The pixels of the liquid crystal display are displayed according to the pixel signals of the video signal.

FIG. 2 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention. As in the drive circuit described in FIG. 1, in FIG. 2, 10 is an input signal terminal, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, and 15 is a liquid crystal cell.
Is a sync separation circuit, 16 is a clock generation circuit, 17 is a horizontal scanning shift register, 18 is a vertical scanning shift register,
Reference numeral 19 is a vertical pixel line signal line, 20 is a clock signal line, 21 is a first delay circuit, and 23 is a flip-flop forming a shift register. Also, 2
Reference numeral 5 is a video input signal line, and 26 is a second delay circuit. In the liquid crystal display drive circuit here, when the propagation delay in the video input signal line 25 is not so large and small, the delay is not necessarily provided for each stage corresponding to the flip-flops 23 of each stage of the horizontal scanning shift register 17. No circuit needed. Therefore, for example, as shown in the circuit diagram of FIG. 2, the phase shift can be sufficiently adjusted even with the configuration in which the second delay circuits 26 are provided every other stage.

In this way, the video input signal line (1
1 and 25), the phase shift depending on the position of the sampling switch element is appropriately provided along the clock signal line 20 for the phase shift depending on the position of the sampling switch element, thereby capturing the pixel signal. Adjust the phase of the sample clock and the video input signal. As a result, the liquid crystal display device can match the phases of the pixel signals and can properly display the computer image.

FIG. 3 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention. In FIG. 3, 10 is an input signal terminal, 12 is a sampling switch element, 13 is a pixel switch element, 1
4 is a liquid crystal cell, 15 is a sync separation circuit, 17 is a horizontal scanning shift register, 18 is a vertical scanning shift register, and 19 is a vertical pixel line signal line. Also, 30a to 30
m is a horizontal pixel read control line, 31 is a video input signal line, 32 is a horizontal scanning start signal line, 33 is a third delay circuit, 34 is a fourth delay circuit, 35 is a horizontal scanning clock generation circuit, and 36 is a vertical line. This is a scanning clock generation circuit.

The operation will be described with reference to the timing chart shown in FIG. When a video input signal including a sync signal is supplied from the input signal terminal 10, the sync separation circuit 15
Separates the horizontal synchronizing signal and the vertical synchronizing signal from the video input signal and supplies them to the horizontal scanning clock generating circuit 35 and the vertical scanning clock generating circuit 36. The horizontal scanning clock generation circuit 35 generates a horizontal scanning start pulse IDD and a horizontal scanning clock φ _D. The vertical scanning clock generation circuit 36 also generates a vertical scanning start pulse IDS and a vertical scanning clock φ _S. The vertical scanning start pulse IDS from the vertical scanning clock generation circuit 36 instructs the start of vertical scanning, and the clock φ _S causes the vertical scanning shift register 18 to perform vertical scanning.

While the i-th line is selected by the output QS _i of the vertical scanning shift register 18, the horizontal scanning clock generation circuit 35 generates a horizontal scanning start pulse IDD to start horizontal scanning. Be instructed. According to the instruction to start the horizontal scanning, the horizontal scanning clock φ _D is supplied to the horizontal scanning shift register 17,
Horizontal scanning is performed by the sample clock output from the output. In this case, the horizontal scanning start pulse IDD generated from the horizontal scanning clock generation circuit 35 is supplied to the horizontal scanning shift register 17 after being delayed by the third delay circuit 33 for a predetermined time through the horizontal scanning start signal line 32. As a result, the instruction to start horizontal scanning by the horizontal scanning start pulse IDD is delayed for a fixed time.

On the other hand, the fourth delay circuit 3 delays the video input signal line 31 by the same delay time as the third delay circuit 33.
4 is provided, the video input signal is delayed by a fourth delay circuit 34 for a predetermined time, propagated to the video input signal line, and supplied to the signal input terminal of the sampling switch element 12. Output QD _j ′ from the horizontal scanning shift register 17 delayed by the third delay circuit 33 for a fixed time
Are respectively added to the control ends of the corresponding sampling switch elements 12, sample the pixel signals of the video input signal 31 that are delayed by the same delay time and are supplied, and input the video signals to the liquid crystal cell of the corresponding j-th pixel. The pixel signal of the signal is taken in.

As described above, in the liquid crystal display drive circuit here, the sync separation circuit 1 from the video input signal is used.
5, the vertical scanning clock circuit 36 and the horizontal scanning clock circuit 35 take out the synchronizing signal, and the vertical scanning start pulse IDS and the vertical scanning clock φ _S for the vertical synchronization, and the horizontal scanning start pulse IDD and the horizontal scanning start pulse IDD for the horizontal scanning. The scan clock φ _D is generated respectively.
At this time, if the propagation delay of the signal QS _i output from the vertical scanning shift register 18 is large, as described with reference to the timing chart of FIG. 5, QS ₁ is QS _{11 in the first} and Nth pixels in the horizontal direction. And QS _1N ,
Therefore, when QS _1N lags behind the QD _N, video signal sampled at QD _N and timing clock,
It will not be written to the pixel. Therefore, the third delay circuit 33 and the fourth delay circuit 3 which delay the horizontal scanning start pulse IDD and the video input signal by the delay time (td).
4 is provided. The third delay circuit 33 delays the horizontal scanning start pulse IDD by td to perform IDD ', and
The fourth delay circuit 34 delays the signal on the video input signal line 31 by td.

As a result, the horizontal scanning shift register 17
The start of the horizontal scan of is delayed by td. Therefore,
Delayed output QD ₁ ~QD _N also sequentially td from the horizontal scanning shift register 17, the output QD ₁ of each of the sampling clock '~QD _N'. At this time, the fourth delay circuit 34
Since the video input signal is also delayed by td, the pixel signal of the corresponding video input signal is sampled at the time of the 1st to Nth sampling tines of horizontal scanning. As a result, the propagation delayed Q
The pixel signal is written in the liquid crystal cell at D _ij . Thus, in the third embodiment, the delay circuit (third delay circuit) delays the horizontal scanning by the delay time corresponding to the propagation delay of the vertical scanning signal QS _i propagating through the pixel reading control line 30 _{i in} the horizontal direction. 33 and a fourth delay circuit 34) are provided on the video input signal line 31 and the horizontal scanning start signal line 32 for transmitting the horizontal scanning start pulse IDD to adjust the timing of QD _j with respect to QS _i .

[0032]

As described above, according to the liquid crystal display device of the present invention, the phase of the clock signal is adjusted corresponding to the propagation delay of the video signal in the video signal line, and the active matrix driving is performed. The phase shift between the pixel signal and its sampling clock in the display drive circuit in the liquid crystal display device can be accurately eliminated, and the pixel signal of the video input signal can be written in the liquid crystal cell at an appropriate pixel position. Further, the influence of the propagation delay of the signal of the vertical scanning output propagated in the horizontal direction by the control signal line of the vertical scanning can be eliminated, and the pixel omission does not occur, whereby the image signal from the computer or the like is displayed. Can be satisfactorily performed, and the resolution of the display image is improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a first embodiment of the present invention,

FIG. 2 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention,

FIG. 3 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention,

FIG. 4 is a circuit diagram of a liquid crystal display drive circuit for explaining a phase shift due to an influence of a signal propagation delay due to a write control signal line in vertical scanning.

FIG. 5 is a timing chart for explaining operations of vertical scanning and horizontal scanning in the liquid crystal display drive circuit,

FIG. 6 is a circuit diagram illustrating a configuration of a conventional liquid crystal display drive circuit,

FIG. 7 is a circuit diagram showing a liquid crystal display drive circuit provided with a phase adjustment circuit for a drive clock signal for sampling.

FIG. 8 is a diagram illustrating a propagation delay of a video input signal line in a liquid crystal display drive circuit.

[Explanation of symbols]

10 ... Input signal terminals 11, 25, 31 ... Video input signal lines, 12 ... Sampling switch element, 13 ... Pixel switch element, 14 ... Liquid crystal cell, 15 ... Sync separation circuit, 1
6 ... Clock generating circuit, 17 ... Horizontal scanning shift register, 18 ... Vertical scanning shift register, 19 ... Vertical pixel line signal line, 20 ... Clock signal line, 21 ... First delay circuit, 22 ... Second delay circuit, 23 ... flip-flop, 26 ... second delay circuit, 30a to 30m, 40a to 4
0m, 70a to 70m ... Horizontal pixel reading control line,
32 ... Horizontal scan start signal line, 33 ... Third delay circuit, 34
... fourth delay circuit, 35, 41 ... horizontal scanning clock generation circuit, 36, 42 ... vertical scanning clock generation circuit, 71 ... switching control terminal, 72 ... multiplexer, 73 ... delay circuit.

Claims (2)

[Claims] 1. In an active matrix driving liquid crystal display device, a video signal line for transmitting a video signal, and a shift register for supplying a signal for sampling the video signal transmitted by the video signal line to a signal line of an active matrix section. A clock signal line for transmitting a clock signal for driving the shift register to the shift register; and one or more clock signal lines provided for the clock signal line, delaying the phase of the clock signal transmitted by the clock signal line for a predetermined time. A liquid crystal display device comprising: 2. In an active matrix driving liquid crystal display device, a video signal line for transmitting a video signal, and a shift register for supplying a signal for sampling the video signal transmitted by the video signal line to a signal line of an active matrix section. A scan start signal line for transmitting a scan start signal for instructing to start scanning of the shift register; and a scan start signal provided on the scan start signal line and transmitted from the scan start signal line for a predetermined time. A first delay means, and a second delay means provided on the video signal line and delaying the video signal transmitted by the video signal line by the same delay time as the delay time delayed by the first delay means. A liquid crystal display device characterized by the above.