JP3314421B2 - Display device and its driving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and
It relates to a driving apparatus, particularly to a de Isupurei and a driving device to eliminate the phase deviation of the drive circuit in de Isupurei device of an active matrix drive.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display driving circuit as shown in FIG. 6 has been known as a liquid crystal display driving circuit for displaying a television image using liquid crystal. FIG.
, 10 is an input signal terminal, 11 is a video input signal line, 12 is a video input signal sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a synchronization separation circuit, 16 is a clock generation circuit, and 17 is a clock generation circuit. Horizontal scan shift register, 18 is a vertical scan shift register, 1
Reference numeral 9 denotes a vertical pixel line signal line.

Next, an outline of the operation will be described. When a video input signal including a synchronization signal is supplied from the input signal terminal 10, the synchronization separation circuit 15 separates the synchronization signal from the video input signal and supplies the synchronization signal to the clock generation circuit 16. The clock generation circuit 16 multiplies the supplied synchronization signal to generate a sample clock of the video input signal, and inputs the sample clock to the horizontal scanning shift register 17. A shift pulse SP is applied to the horizontal scan shift register 17, and the sampling clock of the video input signal is shifted according to the shift pulse SP, and the sampling switch element 12
Are supplied sequentially. During this time, the video input signal from the input signal terminal 10 is propagating through the video input signal line 11, the sampling switch element 12 is turned on by the sample clock from the horizontal scanning shift register 17, and the respective vertical pixel line signal lines Incorporated in 19. The pixel signal taken into the vertical pixel line signal line 19 is the image switch element 1 controlled by the vertical scanning signal supplied from the vertical scanning shift register 18.
The liquid crystal cell 14 is fetched into each liquid crystal cell 14 through 3 and displays the pixel of the liquid crystal display at the corresponding position according to the pixel signal of the video signal.

According to the description in Japanese Patent Application Laid-Open No. Hei 2-309773, a liquid crystal display driving circuit as shown in FIG.
A solution has been proposed assuming that the phase shift of the sampling drive signal with respect to each pixel signal reduces the resolution of an image. That is, the pixels that form a television image have a certain degree of correlation between adjacent pixels, and even if a video signal is captured and displayed in a liquid crystal cell at a shifted pixel position, the video signal and the drive signal cause a phase shift. Although the reduction in resolution is not so problematic, when such a liquid crystal display device is used as a display device for displaying a display image from a computer, the computer image has no interrelation between pixels such as a character image and a sampling drive signal. Is not practical because the phase shift reduces the resolution of the image. Therefore, Japanese Patent Application Laid-Open No. 2-3097
No. 73 discloses a "liquid crystal display device" in which a phase adjustment circuit for adjusting the phase of a drive clock signal of a shift register used for sampling an input signal is provided in the liquid crystal display drive circuit.

FIG. 7 is a circuit diagram showing a liquid crystal display driving circuit provided with a driving clock signal phase adjusting circuit for performing sampling. In FIG. 7, 10 is an input signal terminal, 11 is a video input signal line, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell,
Reference numeral 15 denotes a synchronization separation circuit, 16 denotes a clock generation circuit, 17 denotes a horizontal scanning shift register, 18 denotes a vertical scanning shift register, 19 denotes a vertical pixel line signal line, 71 denotes a switching control terminal, 72 denotes a multiplexer, and 73 denotes a delay circuit. is there.
These 10 to 19 circuit elements are the same circuit elements as those described with reference to FIG. 6, and the operation by each circuit element is also the same.

Here, as shown in FIG. 7, in addition to the circuit elements of the liquid crystal display driving circuit shown in FIG. 6, a phase adjusting circuit for a synchronizing signal comprising a plurality of delay circuits 73 and a multiplexer 72 is provided. The delay time given to the sampling drive clock signal is selected by the phase adjustment circuit, and the signal supplied from the switching control terminal 71 is used to select a signal in which the number of serially connected stages of the delay circuit 73 is switched in the multiplexer 72. To adjust the phase. As a result, the phase of the clock signal is adjusted, the phase shift with the pixel can be adjusted, and an image signal from a computer or the like can be displayed favorably.

[0007]

The liquid crystal display driving circuit shown in FIGS. 6 and 7 has a large number of horizontal pixels on the video input signal line 11, as is apparent from the circuit configuration. The sampling switch elements 12 are connected in parallel. Therefore, the input capacitance (source-gate capacitance, etc.) of each sampling switching element 12 is directly added to the video input signal line 11 as a distributed capacitance. As a result, as shown in FIG. 8, the video input signal line 11 becomes a distributed constant circuit composed of a distributed capacitance (the input capacitance C of the switching element 12) and a distributed resistance (the wiring resistance R between the switching elements 12). This causes a propagation delay of the video input signal. For this reason, like a liquid crystal display device that displays computer images,
If the number of pixels in the horizontal direction is increased in order to increase the resolution of the image, the distribution capacity further increases, and the influence of signal propagation delay on the video input signal line increases.

For this reason, for each pixel signal transmitted on the video input signal line 11, a sequential transmission delay occurs according to the position of the sampling switching element 12, and a phase error with the sampling signal occurs depending on the position. become. Therefore, as described with reference to FIG. 7, it is not sufficient to provide a phase adjustment circuit in the liquid crystal display drive circuit and adjust the phase of the sampling clock signal separated from the synchronization separation circuit at the input point of the image signal. ,
There is a problem that the phase of the sampling clock and the phase of the video input signal are shifted according to the arrangement position of the sampling switching element 12 for taking the video input signal on the video input signal line 11 into the vertical pixel line signal line 19.

The influence of the signal propagation delay on the video input signal line 11 is caused by the horizontal pixel read control line for transmitting the control signal output from the vertical scan shift register 18 for performing the vertical scanning. 70a-7
The same occurs at 0 m (FIG. 7). For this reason,
The video signal from the vertical pixel line signal line 19 is fetched, and the pixel signal is written into the liquid crystal cell 14. The operation timing of the pixel switch element 13 has a phase shift, and the video signal is not written to the liquid crystal cell at a predetermined pixel position. The problem arises.

A specific description will be given with reference to FIG. FIG.
FIG. 3 is a circuit diagram of a liquid crystal display driving circuit for explaining a phase shift due to an influence of a signal propagation delay due to a control signal line in vertical scanning. In FIG. 4, 10 is an input signal terminal, 11 is a video input signal line, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a synchronization separation circuit, 17 is a horizontal scanning shift register, and 18 is a vertical. The scanning shift register 19 is a vertical pixel line signal line. 40a to 40m are horizontal pixel read control lines, 41 is a horizontal scanning clock generation circuit,
Reference numeral 2 denotes a vertical scanning clock generation circuit.

FIG. 5 is a timing chart for explaining the operations of the vertical scanning and the horizontal scanning in the liquid crystal display driving circuit. The operation will be described with reference to the timing chart shown in FIG. When a video input signal including a synchronization signal is supplied from the input signal terminal 10, the synchronization separation circuit 15
Separates the horizontal synchronizing signal and the vertical synchronizing signal from the video input signal, and supplies them to the horizontal scanning clock generation circuit 41 and the vertical scanning clock generation circuit. Horizontal scanning clock generation circuit 41 generates a horizontal scan start pulse IDD and horizontal scanning clock phi _D. Vertical scanning clock generating circuit 42 generates a vertical scanning start pulse IDS and the vertical scanning clock phi _S. Indicates the start of the vertical scanning by the vertical scanning start pulse IDS from the vertical scanning clock generating circuit 42 performs vertical scanning in the vertical scanning shift register 18 by the clock phi _S. While the i-th line is selected by the output QS _i of the vertical scan shift register 18, the start of horizontal scan is instructed by the horizontal scan start pulse IDD, and the horizontal scan clock φ _D
To perform horizontal scanning. The pixel signal of the video input signal is sampled at the j-th pixel by the output QD _j of the horizontal scanning shift register 17.

In this case, the pixel read control lines 40a to 40m, which are the control lines in the horizontal direction of the active matrix section, have the same structure as the video input signal line 11, as described with reference to FIG. Read control line 40a
A distributed constant circuit similar to that of FIG. 8 described above is formed by the input capacitance C of the pixel switch element 13 in the horizontal direction and the wiring resistance R between the pixel switch elements, which are connected to ４０40 m. Therefore, the output QS _i control signals from the vertical scanning shift register 18 produces a propagation delay in the horizontal direction of the pixel read control line 40i. For example, in the timing chart of FIG. 5, the output QS _{1 of the} vertical scanning is QS ₁₁ which is the same as QS ₁ at the first pixel in the horizontal direction, but is the Nth output, as shown in the upper and lower sides in comparison. during incorporation of the pixels, the QS _1N and propagation delay with respect to QS _1. As the number of pixels in the horizontal direction increases and the number of pixel switch elements 13 in the horizontal direction increases, the propagation delay due to this increases further, and the pixel signal of the video input signal is not written to the pixel cell at a predetermined pixel position, resulting in a missing pixel. Occurs.

The present invention has been made to solve such a problem. A first object of the present invention is to provide a phase shift dependent on a signal caused by a distributed resistance and a distributed capacitance of a video input signal line. It adjusts the phase of the sampling clock signal, the pixel signal of the input signal appears exactly original display position at each pixel location Lud Isupurei device and its relative
A drive device is provided.

A second object of the present invention, in the horizontal direction of the pixel number is large, for example, a liquid crystal display device, even if the propagation delay due to the distributed capacitance and distributed resistance in the control signal line of the vertical scanning output QS _i is generated , Eliminate that effect,
To provide a de-Isupurei apparatus that pixel signals of the video signal is written to the liquid crystal cell of the correct display position corresponding to the pixel position.

[0015]

Means for Solving the Problems To achieve the above-described object, a first by the characteristics of Lud Isupurei apparatus of the present invention
In and its drive device, de <br/> Isupurei device of an active matrix driving, a video signal line for transmitting a video signal (11: 1) and a signal for sampling a video signal transmitted by the video signal lines Shift register (1) to be supplied to the signal line of the active matrix section
7) a clock signal line (20) for transmitting a clock signal for driving the shift register to the shift register;
A plurality of clock signal lines are provided, and a phase of a clock signal transmitted by the clock signal line is changed.
Slowly supplied from the shift register
A signal for sampling a video signal is supplied to the video signal line.
And a delay unit (22) for delaying the transmission in accordance with the propagation delay transmitted by the control unit.

Further, in I Lud Isupu <br/> ray device to the second aspect of the present invention, in the de Isupu <br/> Rei device of an active matrix driving, a video signal line for transmitting a video signal (31: FIG. 3) and a shift register (17) for supplying a signal for sampling a video signal transmitted by the video signal line to a signal line of an active matrix section.
A scan start signal line (32) for transmitting a scan start signal for instructing the shift register to start scanning, and a scan start signal provided on the scan start signal line and transmitted from the scan start signal line being fixed. First delay means (33) for delaying time, and second delay provided on the video signal line and delaying a video signal transmitted by the video signal line by the same time as the delay time of the first delay means Means (34).

[0017]

[Action] by the first aspect of the present invention Lud Isupurei apparatus 及
And a driving device for the video signal transmitted through a video signal line (11: FIG. 1) which is a signal line for transmitting a video signal, a shift register (17) converts a signal for sampling the video signal into an active matrix unit. To the signal line. The clock signal line (20)
A signal line for transmitting a clock signal for driving the shift register (17) to the shift register;
A plurality of clock signals 1) are provided on the clock signal line (20), and the phases of the clock signals transmitted through the clock signal line are sequentially delayed and supplied from the shift register.
A signal for sampling a video signal to be
The delay is made corresponding to the propagation delay transmitted by the signal line . The delay time of the delay means (21) is adjusted in accordance with the propagation delay of the video signal on the video signal line (11), and the phase shift between the propagation delay of the video signal and the sampling signal output from the shift register. To eliminate. As a result, the phase of the clock signal is adjusted in accordance with the propagation delay of the video signal on the video signal line (11), the phase with the pixel can be adjusted, and the image signal from the computer or the like can be displayed. Can be performed well.

Further, in Lud Isupu <br/> ray device by the second feature of the present invention, a video signal line of the signal line for transmitting a video signal: the video signal transmitted by the (31 Figure 3) On the other hand, the shift register (17) supplies a signal for sampling the video signal line to the signal line of the active matrix section. The scan start signal line (32) transmits a scan start signal for instructing the start of scanning by the shift register (17). The scanning start signal line (32) is provided with a first delay means (33), and the first delay means (30) is provided.
, The scanning start signal transmitted from the scanning start signal line is delayed for a predetermined time. A second delay means (34) is provided on the video signal line (31).
A delay means (34) delays the video signal transmitted by the video signal line by the same time as the delay time delayed by the first delay means.

In this manner, the video signal line (3) is provided by the first delay means (33) and the second delay means (34).
The video input signal according to 1) and the scanning start signal from the scanning start signal line (32) are delayed by the same time. Thereby, the signal (scanning control signal) supplied to the signal line of the active matrix section is first generated by the delay time delayed here, and then propagates through the signal line to read the pixel signal into the liquid crystal cell. The delay time until the pixel switch element is turned on is secured (guaranteed), and the influence of the propagation delay of the signal of the vertical scanning output propagated in the horizontal direction by the vertical scanning control signal line can be eliminated. Pixel omission does not occur.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an input signal terminal;
Is a video input signal line, 12 is a sampling switch element for a video input signal, 13 is a pixel switch element, 14 is a liquid crystal cell, 15 is a synchronization separation circuit, 16 is a clock generation circuit, 17 is a horizontal scanning shift register, and 18 is vertical scanning The shift register 19 is a vertical pixel line signal line. 20 is a clock signal line, 21 is a first delay circuit, 22 is a second delay circuit, and 23 is a flip-flop constituting a shift register.

In the configuration of the liquid crystal display drive circuit shown in FIG. 1, flip-flops 23 constituting each shift stage of the horizontal scanning shift register 17 are shown for each stage.
A second delay circuit 22 is provided for each flip-flop 23 of each stage. Input signal terminal 10
When a video input signal including a synchronizing signal is supplied from, the synchronizing separation circuit 15 separates the synchronizing signal from the video input signal and supplies the synchronizing signal to the clock generating circuit 16. The clock generation circuit 16 multiplies the supplied synchronization signal to generate a sample clock of the video input signal. The phase of the sample clock generated from the clock generation circuit 16 at the input point of the horizontal scanning shift register 17 is adjusted by the first delay circuit 21. Then, after the sample clock is adjusted by the first delay circuit 21, the clock signal line 2
Propagated through 0.

The clock signal line 20 is provided with a plurality of stages of second delay circuits 22. The plurality of stages of second delay circuits 22 adjust the phase of the sample clock with respect to the propagation delay of the video input signal. You. That is, the influence of the phase shift due to the propagation delay of the video input signal caused by the distributed resistance and the distributed capacitance in the video input signal line 11 is caused by the second delay circuit 22 provided for the flip-flop 23 of each stage of the horizontal scan shift register 17. Is adjusted by As a result, the phase of the clock signal is adjusted for each position of the flip-flop at each stage of the horizontal scanning shift register 17 that transmits the sample clock with respect to the propagation delay of the video input signal on the video input signal line 11, The position of the pixel signal of the video input signal and the phase of the sample clock are accurately adjusted, and the pixel signal is written into the liquid crystal cell 14 at the exact corresponding position.

The subsequent operation is the same as that of the previously described circuit example. That is, the sample clock is supplied from the clock generation circuit 16 to the first delay circuit 21 and the second delay circuit 2.
By 3, the phase is adjusted, added to the horizontal scanning shift register 17, shifted, and sequentially supplied to the sampling switch element 12. During this time, the video input signal from the input signal terminal 10 is propagating through the video input signal line 11, and the sampling switch element 1 is driven by the sample clock from the horizontal scanning shift register 17.
2 sequentially turn on, and are taken into each vertical pixel line signal line 19. The pixel signal captured by the vertical pixel line signal line 19 is captured by each liquid crystal cell 14 via the image switch element 13 controlled by the vertical scanning signal supplied from the vertical scanning shift register 18, and the pixel signal of the corresponding position is The pixels of the liquid crystal display are displayed according to the pixel signal of the video signal.

FIG. 2 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention. 2, 10 is an input signal terminal, 12 is a sampling switch element, 13 is a pixel switch element, 14 is a liquid crystal cell, 15
Is a sync separation circuit, 16 is a clock generation circuit, 17 is a horizontal scanning shift register, 18 is a vertical scanning shift register,
Reference numeral 19 denotes a vertical pixel line signal line, 20 denotes a clock signal line, 21 denotes a first delay circuit, and 23 denotes a flip-flop constituting a shift register. Also, 2
5 is a video input signal line, and 26 is a second delay circuit. In the liquid crystal display drive circuit here, if the propagation delay in the video input signal line 25 is not so large and small, the delay is not necessarily every stage corresponding to the flip-flop 23 of each stage of the horizontal scanning shift register 17. No circuit is required. For this reason, for example, as shown in the circuit diagram of FIG. 2, even in a configuration in which the second delay circuit 26 is provided every other stage, the phase shift can be sufficiently adjusted.

In this way, the video input signal line (1
With respect to the propagation delay of (1, 25), a pixel circuit is fetched by appropriately providing a phase shift depending on the position of the sampling switch element along the clock signal line 20 with a delay circuit for adjusting the phase of the sample clock. Adjust the phase between the sample clock and the video input signal. As a result, the phase of the pixel signal can be matched, and a liquid crystal display device capable of displaying a computer image satisfactorily can be obtained.

FIG. 3 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention. 3, 10 is an input signal terminal, 12 is a sampling switch element, 13 is a pixel switch element, 1
4 is a liquid crystal cell, 15 is a sync separation circuit, 17 is a horizontal scan shift register, 18 is a vertical scan shift register, and 19 is a vertical pixel line signal line. Also, 30a-30
m is a horizontal pixel reading control line, 31 is a video input signal line, 32 is a horizontal scanning start signal line, 33 is a third delay circuit, 34 is a fourth delay circuit, 35 is a horizontal scanning clock generation circuit, and 36 is a vertical line. This is a scan clock generation circuit.

The operation will be described with reference to the timing chart shown in FIG. When a video input signal including a synchronization signal is supplied from the input signal terminal 10, the synchronization separation circuit 15
Separates the horizontal synchronizing signal and the vertical synchronizing signal from the video input signal and supplies them to the horizontal scanning clock generation circuit 35 and the vertical scanning clock generation circuit 36. Horizontal scanning clock generating circuit 35 generates a horizontal scan start pulse IDD and horizontal scanning clock phi _D. The vertical scanning clock generator 36 generates a vertical scanning start pulse IDS and the vertical scanning clock phi _S. It indicated the start of the vertical scanning by the vertical scanning start pulse IDS from the vertical scanning clock generating circuit 36, the vertical scanning by the vertical scanning shift register 18 is performed by the clock phi _S.

[0028] In While wherein the i-th line by the output QS _i of the vertical scanning shift register 18 is selected, the horizontal scanning start pulse IDD is generated from the horizontal scanning clock generating circuit 35, the start of the horizontal scanning Be instructed. The instruction to start the horizontal scan, a horizontal scanning clock phi _D is supplied to the horizontal scanning shift register 17,
The horizontal scanning is performed by the sample clock output from this. In this case, the horizontal scanning start pulse IDD generated from the horizontal scanning clock generating circuit 35 is supplied to the horizontal scanning shift register 17 after being delayed by a third delay circuit 33 through the horizontal scanning start signal line 32 for a certain time. As a result, the instruction to start horizontal scanning by the horizontal scanning start pulse IDD is delayed by a certain time.

On the other hand, a fourth delay circuit 3 for delaying the video input signal line 31 by the same delay time as the third delay circuit 33
The delay circuit 34 delays the video input signal by a predetermined time by the fourth delay circuit 34, propagates the video input signal to the video input signal line, and supplies the signal to the signal input terminal of the sampling switch element 12. The output QD _j ′ from the horizontal scanning shift register 17 delayed for a predetermined time by the third delay circuit 33
Are respectively applied to the control terminals of the corresponding sampling switch elements 12 and sample the pixel signals of the video input signal 31 supplied with the same delay time and supplied to the liquid crystal cell of the corresponding j-th pixel. The pixel signal of the signal is taken.

As described above, in the liquid crystal display drive circuit here, the sync separation circuit 1
5 by taking out a synchronizing signal, the vertical scanning clock circuit 36 and the horizontal scanning clock circuit 35, a vertical scanning start pulse IDS for vertical synchronization, and a vertical scanning clock phi _S, the horizontal scanning start pulse IDD for horizontal scanning, horizontal each generates a scanning clock phi _D.
In this case, the propagation delay of the signal QS _i output from the vertical scanning shift register 18 is large, as explained by the timing chart of FIG. 5, the first and N-th pixel in the horizontal direction, QS ₁ is QS ₁₁ And QS _1N
Therefore, when QS _1N lags behind the QD _N, video signal sampled at QD _N and timing clock,
It is no longer written to the pixel. Therefore, the third delay circuit 33 and the fourth delay circuit 3 for delaying the horizontal scanning start pulse IDD and the video input signal by the delay time (td)
4 is provided. The horizontal scanning start pulse IDD is delayed by td by the third delay circuit 33 to be IDD ', and the signal of the video input signal line 31 is delayed by td by the fourth delay circuit.

As a result, the horizontal scanning shift register 17
Is delayed by td. Therefore,
The outputs QD _{1 to} QD _N from the horizontal scan shift register 17 are also sequentially delayed by td, and become the respective outputs QD ₁ ′ to QD _N ′ of the sampling clock. At this time, the fourth delay circuit 34
, The video input signal is also delayed by td, so that the pixel signal of the corresponding video input signal is sampled at each of the first to Nth sampling timigs in the horizontal scanning. As a result, the propagation delayed Q
A pixel signal is written to the liquid crystal cell at D _ij . Thus, in the third embodiment, a delay circuit (third delay circuit by a delay time corresponding to the propagation delay of the vertical scanning signal QS _i propagating horizontal pixel read control line 30i delays the horizontal scanning 33 and the fourth delay circuit 34), provided in the horizontal scan start signal line 32 for transmitting a video input signal line 31 a horizontal scanning start pulse IDD, adjusts the timing of the QD _j against QS _i.

[0032]

As described above, according to the liquid crystal display device of the present invention, the phase of the clock signal is adjusted in accordance with the propagation delay of the video signal on the video signal line, and the active matrix driving is performed. In this liquid crystal display device, the phase shift between the pixel signal and its sampling clock in the display drive circuit can be accurately eliminated, and the pixel signal of the video input signal can be written into the liquid crystal cell at an appropriate pixel position. In addition, it is possible to eliminate the influence of the propagation delay of the signal of the vertical scanning output propagated in the horizontal direction by the control signal line of the vertical scanning, so that pixel omission does not occur, thereby displaying an image signal from a computer or the like. And the resolution of the displayed image is improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram of a drive circuit showing a configuration of a main part of a liquid crystal display device according to a second embodiment of the present invention;

FIG. 3 is a circuit diagram of a driving circuit showing a configuration of a main part of a liquid crystal display device according to a third embodiment of the present invention;

FIG. 4 is a circuit diagram of a liquid crystal display driving circuit for explaining a phase shift caused by a signal propagation delay due to a write control signal line in vertical scanning;

FIG. 5 is a timing chart for explaining operations of vertical scanning and horizontal scanning in a liquid crystal display driving circuit;

FIG. 6 is a circuit diagram illustrating a configuration of a conventional liquid crystal display driving circuit.

FIG. 7 is a circuit diagram showing a liquid crystal display drive circuit provided with a drive clock signal phase adjustment circuit for performing sampling;

FIG. 8 is a diagram illustrating a propagation delay of a video input signal line in a liquid crystal display driving circuit.

[Explanation of symbols]

Reference Signs List 10: input signal terminal, 11, 25, 31: video input signal line, 12: sampling switch element, 13: pixel switch element, 14: liquid crystal cell, 15: synchronization separation circuit, 1
6 clock generation circuit, 17 horizontal scanning shift register, 18 vertical scanning shift register, 19 vertical pixel line signal line, 20 clock signal line, 21 first delay circuit, 22 second delay circuit, 23 ... Flip-flop, 26 ... Second delay circuit, 30a-30m, 40a-4
0m, 70a to 70m ... horizontal pixel read control lines,
32 ... horizontal scanning start signal line, 33 ... third delay circuit, 34
.. A fourth delay circuit, 35, 41 a horizontal scanning clock generation circuit, 36, 42 a vertical scanning clock generation circuit, 71 a switching control terminal, 72 a multiplexer, 73 a delay circuit.

Claims (3)

(57) [Claims] 1. A de Isupure <br/> Lee device of an active matrix drive, a video signal line for transmitting a video signal, the signal lines of the video signal active matrix unit a signal for sampling a video signal transmitted by the line a shift register for supplying to a clock signal line for transmitting a clock signal for driving the shift register in the shift register is provided a plurality more than the clock signal line, a clock signal transmitted by the clock signal line Phase
Slowly supplied from the shift register
A signal for sampling a video signal is supplied to the video signal line.
It features and to Lud Isupurei apparatus further comprising a delay means for delaying in correspondence to the propagation delay that is transmitted by. 2. A de Isupure <br/> Lee device of an active matrix drive, a video signal line for transmitting a video signal, the signal lines of the video signal active matrix unit a signal for sampling a video signal transmitted by the line A scan start signal line for transmitting a scan start signal for instructing the shift register to start scanning, and a scan start signal provided on the scan start signal line and transmitted from the scan start signal line. First delay means for delaying the video signal by a predetermined time, and second delay means provided on the video signal line and delaying the video signal transmitted by the video signal line by the same time as the delay time of the first delay means. And a display device comprising: 3. A driving device for de Isupure <br/> Lee device of an active matrix driving, a video signal line for transmitting the video signal and the video signal active matrix unit a signal for sampling a video signal transmitted by the line A shift register that supplies a clock signal for driving the shift register to the shift register; and a plurality of clock signal lines that are provided and transmitted by the clock signal line. The phase of the clock signal
Slowly supplied from the shift register
A signal for sampling a video signal is supplied to the video signal line.
And a delay means for delaying in accordance with the propagation delay transmitted by the display device .
Motion device .