JPH0628423B2 - Image display device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an image display device using a liquid crystal display panel or the like.

[Prior art and its problems]

In recent years, a liquid crystal television using a liquid crystal display panel in a display unit has been put into practical use as a small television. The display drive circuit in the liquid crystal television is conventionally constructed as shown in FIG. That is, in the figure, reference numeral 11 is a control and scan electrode driving LSI, which drives the scan electrodes of the liquid crystal display panel 13 in accordance with the sampling data sent from the A / D conversion circuit 12 and a synchronizing signal from a synchronizing circuit (not shown). To do. The liquid crystal display panel 13 has a structure in which the display electrodes are, for example, a double matrix and have 120 × 160 dots. Then, the control and scan electrode driving LSI
Reference numeral 11 supplies sampling data and a display clock to the signal electrode driving LSIs 14a to 14d via the data bus 15 and chip select signals via the control lines 16a to 16d. The signal electrode drive LSI 1
4a to 14d are signal electrodes Y for the liquid crystal display panel 13.
_{1 to} Y ₈₀ are LSIs 14a and 14c, and signal electrodes Y _{81 to} Y ₁₆₀ are
It is driven by the LSIs 14b and 14d. That is, as shown in FIG. 2, for each scanning electrode of the liquid crystal display panel 13,
The picture elements a and c of the signal electrodes Y _{1 to} Y ₈₀ are the LSIs 14a and 14
c, the picture elements b and d of the signal electrodes Y _{81 to} Y ₁₆₀ are the LSI 14b, 1
Driven by 4d.

In the above configuration, the A / D conversion circuit 12 samples the video signal sent from the video amplification circuit (not shown) in synchronization with the clock φ _{2 as} shown in FIG.
The sampling data I _{0 to} I ₄ are output to the control and scan electrode drive LSI 11. This control and scan electrode drive LSI
Reference numeral 11 denotes a buffer 11 which synchronizes the sampling data I _{0 to} I ₄ input as shown in FIG. ₄ with the clock φ _1.
It is read into a and is output as display data O _{0 to} O ₃ of 16 gradations in synchronization with the clock pulse φ ₂ . This buffer 1
The display data O _{0 to} O ₃ output from 1a are sent to the signal electrode drive LSIs 14a to 14d via the data bus 15. Further, the control and scan electrode driving LSI 11 creates various display clocks based on the horizontal synchronizing signal and the vertical synchronizing signal sent from the synchronizing circuit, and the signal electrode driving LSI 14
a to 14d. Signal electrode drive LSIs 14a-14
In d, only the LSI selected by the chip select signal fetches the display data O _{0 to} O ₃ on the data bus 15,
The liquid crystal display panel 13 is driven by creating a gradation waveform.

However, in the above-mentioned conventional liquid crystal driving method, when the number of dots increases in order to increase the size of the liquid crystal display panel 13 or increase the screen density, the frequency of the sampling clock of the video signal must be increased. For example, when the sampling frequency of the video signal is _S for an m × n dot liquid crystal display panel, when driving a 2m × 2n dot liquid crystal display panel, the sampling frequency must be doubled to 2 _S. That is, in FIG. 3, the frequencies of the sampling clocks φ ₁ and φ _{2
Since S} samples 160 times the effective video signal period t _H shown in FIG. 5, _S = (t _H / 160) ⁻¹ Hz. Then, when the liquid crystal display panel is configured with 240 × 320 dots and the number of picture elements is quadrupled, the sampling frequency ′ _S is ′ _H = (t _H / 320) ⁻¹ = 2 _S Hz, which is twice the _S. . Such a high sampling frequency causes many problems such as an increase in current consumption, design of high-speed operation LSI, mounting problems, and high frequency noise. Also, since the sampling frequency of the display data differs depending on the dot configuration of the liquid crystal display panel, it is necessary to use different ones for the m × n dot liquid crystal television LSI and the 2m × 2n dot liquid crystal television LSI. However, the cost of the LSI increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide an image display device capable of driving a display panel having a large number of pixels without increasing the sampling frequency of display data. To aim.

[Points of the Invention] The present invention samples a video signal and uses Km × Ln (K and L are integers of 2 or more) according to the sampling data.
In an image display device for driving a display panel having a dot configuration, a means for alternately sampling the video signal with K-phase clocks φ1 to φK, a data bus for commonly connecting a plurality of signal electrode driving means, and a sampled First to Kth signal electrode driving for reading data with clocks φ1 to φK, outputting to the data bus with clock φK, and driving the signal electrodes of Km dots of the display panel according to the data output to the data bus Means and
Includes n-bit first to Lth shift registers connected to each other, sequentially shifts the signal input to the first shift register at a predetermined timing, and inputs the n-th bit output to the shift register in the subsequent stage. To form an Ln-bit shift register, and the L of the display panel is changed in accordance with a signal sequentially shifted in the first to Lth shift registers.
First to Lth scanning electrode driving means for driving the n-dot scanning electrodes and a single clock for generating the K-phase clocks φ1 to φK and supplying them to the first to Kth signal electrode driving means. The present invention is characterized by including a generating means and a means for operating the first to Kth signal electrode driving means and the first to Lth scanning electrode driving means in synchronization.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. Sixth
In the figure, reference numeral 21 denotes an A / D conversion circuit, which converts a video signal sent from an image amplification circuit (not shown) into clocks φ ₁ and φ.
Sampling by ₂ and control and scan electrode drive LSI
It outputs to 22a and 22b. In addition, this LSI 22a, 2
Although not shown, horizontal and vertical synchronizing signals are input to 2b from a synchronizing circuit. The control and scan electrode drive LSI 22
Although the details of a and 22b will be described later, the operation mode is designated by the mode signals A and B.
Mode, the LSI 22b is given a mode signal to operate in the B mode. Then, the above control and scan electrode drive
LSI22a, 22b drives the scan electrodes _X 1 to X ₁₂₀ of the liquid crystal display panel 23. In this case, when the LSI 22a drives the scan electrodes X _{1 to} X ₆₀ , the LSI 22a to the LSI 22a
b sends a timing signal via a signal line 24 to, thereby LSI22b is adapted to drive the scanning electrodes X ₆₁ to X _120. The liquid crystal display panel 23 has a structure in which the display electrodes are, for example, a double matrix and have 240 × 320 dots. Then, the control and scan electrode driving LSI
22a and 22b are signal electrode drive LSIs 26a, 26b, 27a, 27b and 2 via data buses 25a and 25b.
Display data and a display clock are supplied to 8a, 28b, 29a, and 29b, and a chip select signal is supplied through a signal line (not shown). The signal electrode drive LSI 2
6a to 29b are signal electrodes Y ₁ to Y ₁ of the liquid crystal display panel 23.
While driving the Y _320, as shown in FIG. 7 LSI26a, 2
8a drives the picture elements a, e of the odd-numbered electrodes in the signal electrodes _Y 1 _{~Y 160,} LSI26b, 28b to drive the pixels b, f of the even-numbered electrodes. In addition, LSIs 27a and 29
a drives the picture elements c and g of the odd-numbered electrodes of the signal electrodes Y _{161 to} Y ₃₂₀ , and the LSIs 27b and 29b drive the picture elements d and h of the even-numbered electrodes.

Next, details of the control and scan electrode drive LSIs 22a and 22b will be described. The LSIs 22a and 22b are the eighth
As shown in the figure, an oscillator 31 for generating a reference frequency signal is provided. The oscillator 31 includes the LSI 22a.
Only on the side of the crystal unit 32 through the external connection terminal
Are connected. Oscillator 31 to which crystal oscillator 32 is connected
Are clocks φ ₁ , φ via clocked inverters 33a, 33b controlled by the mode signal A, respectively.
₂ is output. The clocks φ ₁ and φ ₂ are used in the internal circuit and are supplied from the connection terminals 34a and 34b.
It is sent to the LSI 22b side. Further, the LSIs 22a and 22b are
As shown in FIG. 9, a mode specifying terminal 35 is provided,
The V _DD power supply or the V _SS power supply is switched and input by the mode switch 36 or the like. Mode designation terminal 3 above
The input to 5 is used as the mode signal B, and
It is used as the mode signal A via the inverter 37. Therefore, the control and scan electrode drive LSIs 22a, 22
The b temporarily holds the display data I _{0 to} I ₃ sent from the A / D conversion circuit 21 in the buffer 41 as shown in FIG. The A / D conversion circuit 21 performs a sampling operation by the clocks φ ₁ and φ ₂ given from the LSI 22a via the OR circuit 42, and outputs the outputs I _{0 to} I ₃ to the buffer 41 as described above. The buffer 41 reads data according to the clock φ ₁ or φ ₂ supplied via the AND circuits 43 and 44 and the OR circuit 45. In this case, the clock φ ₁ is gated by the mode signal A in the AND circuit 43, and the clock φ ₂ is gated by the mode signal B in the AND circuit 44. Then, the data held in the buffer 41 is sent to the buffer 46 and is output as the display data O _{0 to} O ₃ via the clocked inverter 47 whose gate is controlled by the mode signal B. Further, the buffer 46 reads the input data in synchronization with the clock φ ₂ and outputs it as display data O _{0 to} O ₃ via the clocked inverter 48 that operates according to the mode signal A.
The display data O _{0 to} O ₃ output from the clocked inverters 47 and 48 are output to the data buses 25a and 25b as gradation signals (16 gradations) as shown in FIG.

Further, the control and scan electrode drive LSIs 22a and 22b are provided with a 60-bit shift register 51 as shown in FIG. A timing signal is input to the first bit of the shift register 51 via the clocked inverter 52 controlled by the mode signal A. The shift register 51 sequentially shifts the input timing signal in synchronization with the clock pulse, and supplies the final bit output to the signal line 54 via the clocked inverter 53 controlled by the mode signal A. The signal line 54 is connected to the SR terminal and also connected to the input terminal of the shift register 51 via the clocked inverter 55 controlled by the mode signal B. The SR terminal is connected between the LSIs 22a and 22b.
Then, the contents of the shift register 51 are sent to the display drive circuit 56, and the display drive circuit 56 drives the scan electrodes X _{1 to} X ₆₀ or X _{61 to} X ₁₂₀ of the liquid crystal display panel 23.

Next, the operation of the above embodiment will be described. First, the operation mode is set for the control and scan electrode drive LSIs 22a and 22b. That is, a "0" signal (V _SS power supply) is applied to the mode designation terminal 35 in FIG. 9 for the LSI 22a, and a "1" signal (V _DD power supply) is applied to the mode designation terminal 35 for the LSI 22b. In the LSI 22a, when the "0" signal is applied to the mode designation terminal 35, the mode signal A output through the inverter 37 becomes "1", and the clocked inverter shown in FIGS. 33a, 33b, 48, 52, 53
And the gate of the AND circuit 43 opens. Also, the LSI 22b
The mode signal B is set to "1" by applying the "1" signal to the mode designation terminal 35, and the gates of the clocked inverters 47 and 55 and the AND circuit 44 are opened.
Since the crystal oscillator 32 is externally connected, the LSI 22a generates a reference frequency signal and outputs the two-phase clocks φ ₁ and φ ₂ shown in FIG. 12 via the clocked inverters 33a and 33b. The LSIs 22a and 22b operate in synchronization with the clocks φ ₁ and φ ₂ . And
The clocks φ ₁ and φ ₂ are supplied to the OR circuit 4 in the LSI 22a.
2 to the A / D conversion circuit 21. The A / D conversion circuit 21 performs a sampling operation in synchronization with the clocks φ ₁ and φ ₂ and outputs sampling data I _{0 to} I ₃ thereof.
To the buffer 41 in the LSIs 22a and 22b. Since sampling is performed with the clocks φ ₁ and φ ₂ in this way, if the frequency of the clocks φ ₁ and φ ₂ is _S , then
The sampling data I _{0 to} I ₃ change in 2 _S as shown in FIG. That is, the video signal is sampled at 2 _S. The LSI 22a to which the sampling data I _{0 to} I ₃ is input is the tenth
In the figure, since the gate of the AND circuit 43 is opened by the mode signal A, the clock φ ₁ is supplied to the buffer 41. Therefore, the sampling data I _{0 to} I ₃ are read into the buffer 41 in synchronization with the clock φ ₁ and then read into the buffer 46 in synchronization with the clock φ ₂ . Then, the data read in the buffer 46, that is, the data sampled by the clock φ ₁ is output to the data bus 25a as the display data O _{1 to} O ₃ via the clocked inverter 48, and the signal electrode drive LSI 26.
a, 27a, 28a, 29a. On the other hand, LSI2
2b, the AND circuit 44 is operated by the mode signal B.
Is opened, and clock φ ₂ is applied to the buffer 41. Therefore, the sampling data I _{0 to} I ₃ are read into the buffer 41 in synchronization with the clock φ ₂ . Then, the data read in the buffer 41, that is, the data sampled by the clock φ ₂ is output to the data bus 25b as the display data O _{1 to} O ₃ via the clocked inverter 47 controlled by the mode signal B. , Signal electrode drive LSIs 26b, 27b, 28b, 29
sent to b. That is, the data I _{0 to} I ₃ sampled by the clock φ ₁ or φ ₂ are stored in the LSI 22a,
22b to clock φ ₂ as shown in FIG.
Is output as display data O _{0 to} O ₃ . Then, the signal electrode drive LSIs 26a, 27a, 28a,
29a the odd-numbered signal electrode _Y 1 of the liquid crystal display panel 23 by the data sampled by the clock phi _{1,
Y 3, Y 5, ... Y} 161, Y 163, Y 165, drives ..., signal electrode drive LSI26b, 27b, 28b, 29b, the clock φ even number signal electrodes _Y 2 by sampled data by _2, Y ₄ , Y ₆ , ... Y ₁₆₂ , Y ₁₆₄ , Y
₁₆₆ , ... is driven.

Further, in the control and scan electrode driving LSI 22a, a timing signal synchronized with the vertical synchronizing signal in FIG. 11 is input to the shift register 51 via the clocked inverter 52. The shift register 51 reads the timing signal at the first bit and then sequentially shifts in synchronization with the clock pulse. The data held in the shift register 51 is sent to the display drive circuit 56, and the scan electrodes X _{1 to} X _{60 of the} liquid crystal display panel 23 are sequentially driven according to the position of the “1” signal shifted in the shift register 51. . When the read data of the shift register 50 is shifted to the most significant bit, the clocked inverter 5
The signal is output to the signal line 54 via 3 and further sent from the SR terminal to the SR terminal of the LSI 22b. Since the gate of the clocked inverter 55 is opened by the mode signal B in the LSI 22b, the signal sent from the LSI 22a is input to the first bit of the shift register 51. Then, the signal input to the shift register 51 is sequentially shifted in the shift register 51 in synchronization with the clock pulse. By the shift operation of the shift register 51, the scan electrodes X _{61 to} X _{120 of the} liquid crystal display panel 23 are sequentially driven through the display drive circuit 56. Similarly, the signal electrodes Y _{1 to} Y ₃₂₀ and the scanning electrode X _{1 of the} liquid crystal display panel 23 are similarly processed _.
To X ₁₂₀ are driven, and gradations corresponding to the display data O _{1 to} O ₃ are displayed.

As described above, according to the present invention, the data obtained by alternately sampling the video signal with the K-phase clocks φ1 to φK is read with the clocks φ1 to φK and is output to the data bus with the clock φK. First to Kth signal electrode driving means for driving the Km dot signal electrodes of the display panel according to the data output to the data bus are provided, and
Includes n-bit first to Lth shift registers connected to each other, sequentially shifts the signal input to the first shift register at a predetermined timing, and inputs the n-th bit output to the shift register in the subsequent stage. To form an Ln-bit shift register, and the L of the display panel is changed in accordance with a signal sequentially shifted in the first to Lth shift registers.
Since the first to Lth scan electrode driving means for driving the scan electrodes of n dots are provided and the signal electrode driving means and the scan electrode driving means are operated in synchronization, the same as in the m × n dot display panel. Since the display panel of Km × Ln dots can be driven at a frequency and the sampling data is supplied to the first to Kth signal electrode driving means via the data bus, the signal electrode driving means is formed into an LSI. At any time, the number of LSIs can be set arbitrarily. Further, since the shift register has the L × n configuration also on the scanning side, there is an effect that the number of LSIs can be arbitrarily set when the scan electrode driving means is formed into an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a conventional image display device, FIG. 2 is a diagram showing an electrode driving method of a liquid crystal display panel in FIG. 1, and FIG. 3 is an A / D conversion circuit in FIG. FIG. 4 is a diagram showing a main part of a control and scan electrode driving LSI, FIGS. 4 and 5 are diagrams for explaining the operation of the conventional device, and FIGS. 6 to 12 are diagrams showing an embodiment of the present invention. so,
FIG. 6 is a block diagram showing a circuit configuration, FIG. 7 is a diagram showing a connection relationship between a liquid crystal display panel and an electrode driving LSI, and FIGS. 8 to 11 are detailed views of a main part of a control and scan electrode driving LSI. FIG. 12 and FIG. 12 are timing charts for explaining the operation. 21 ... A / D conversion circuit, 22a, 22b ... Control and scan electrode driving LSI, 23 ... Liquid crystal display panel, 25a, 2
5b ... Data bus, 26a, 26b, 27a, 27
b, 28a, 28b, 29a, 29b ... Signal electrode drive
LSI, 31 ... Oscillator, 32 ... Crystal oscillator, 41, 4
6 ... Buffer, 51 ... Shift register, 56 ... Display drive circuit.

Claims (1)

[Claims] 1. An image display device for sampling a video signal and driving a display panel of Km × Ln (K, L is an integer of 2 or more) dots according to the sampling data, wherein the video signal is K phase clocks φ1 to φ1. means for alternately sampling with φK, a data bus for commonly connecting a plurality of signal electrode driving means, and sampled data are read with clocks φ1 to φK and output to the data bus with clock φK. The first to Kth signal electrode driving means for driving the Km dot signal electrodes of the display panel according to the data output to the bus, and the n-bit first to Lth shift registers connected to each other are provided. The signal input to the first shift register is sequentially shifted at the timing of, and the output of the n-th bit is shifted to the subsequent shift register. To the Ln-bit shift register, and the Ln-bit shift register of the display panel is operated in accordance with signals sequentially shifted in the first to Lth shift registers.
First to Lth scan electrode driving means for driving the n-dot scan electrodes and a single clock for generating the K-phase clocks φ1 to φK and supplying them to the first to Kth signal electrode driving means. An image display device comprising: a generating unit; and a unit for operating the first to Kth signal electrode driving units and the first to Lth scanning electrode driving units in synchronization with each other.