JPS60120678A - Display device of picture - Google Patents

Abstract

PURPOSE:To prevent power consumption from increase by sampling a video signal alternately in double phase clocks, driving a display panel with the sampled data and setting sampling frequency to twice apparently. CONSTITUTION:A video signal transmitted from an image amplifier circuit is added to an A/D convertor circuit 21, where it is sampled double phase clocks phi1 and phi2, and supplied to control and scanning electrode driving LSIs 22a and 22b. Their action modes are designated by a mode signal, the LSIs 22a and 22b drive scanning electrodes X1-X120 of a liquid crystal display panel 23, and apply display data and display clocks for signal electrode driving LSIs 26a-29a and 26b-29b through data buses 25a and 25b. The LSIs 26a and 28a, and the LSIs 26b and 28b drive the odd and even number electrodes respectively, in signal electrodes Y1-Y160, and the LSIs 27a, 29a and 27b, 29b drive the odd and even number electrodes respectively in signal electrodes Y161-Y320.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image display device using a 9-channel liquid crystal display.

[Prior art and its problems]

In recent years, liquid crystal televisions that use liquid crystal display panels in their display sections have been put into practical use as small televisions.

Conventionally, the display drive circuit in the liquid crystal television set is configured as shown in FIG. That is, in the figure, 11 is a control and scanning electrode drive LSI, and A
The scan electrodes of the liquid crystal display panel I3 are driven in accordance with sampling data sent from the /D conversion circuit 12 and a synchronization signal from a synchronization circuit (not shown). The above-mentioned liquid crystal display panel 13 has display electrodes (for example, 2 rows).
It has a 20x160 dot configuration. The above control and scanning electrode drive LSIIZ is the signal electrode drive L
For SI I 4 a-Z 4 d, Te"-Tabas Z
Sampling data and a display clock are provided via the control line 16a=Z6d, and a chip select signal is provided via the control line 16a=Z6d. The above signal electrode drive LSI Z 4
a-14d is the signal electrode Y for the liquid crystal display panel Z3.
1 to yso are driven by LSIs 14 a % 14 e s signal electrodes Y81 to ytgo are driven by LSIs I4b and 14d. That is, as shown in FIG. 2, for each scanning electrode of the liquid crystal display channel Z3, the picture elements B and c of the signal electrodes Y1 to yso are LSI l4bs 14cx signals WL & Y.
s r~ytso picture elements, d is LSI Z 4 b,
14d.

In the above configuration, the A/D '71 conversion circuit 12 converts the video signal sent from the video amplifier circuit (not shown) into the clock φ! as shown in FIG. It is sampled in synchronization with , and outputs it to the control and scanning electrode drive LS11z at the sampling date Io=I4'. As shown in FIG. 4, this control and scanning electrode drive LSI IZ reads the input sampling data I, %I4 into the buffer ZZa in synchronization with the clock φ1, and outputs the clock pulse φ2.
It is output as display data O0-03 of 16 gradations in synchronization with . The display data Oo-03 output from the buffer 711a are sent to the signal electrode drive LSIs 14a-14d via the data bus Z5. Further, the control and scanning magnetic pole drive LSI 11 creates various display clocks based on the horizontal synchronization signals and vertical synchronization signals sent from the synchronization circuit, and outputs various display clocks to the signal electrode drive LSIs I 4 a to 14.
Output to d. Signal electrode drive LSI 24 a to 14 d
- Only the LSI selected by the chip select signal takes in the display data 00 to 03 on the data bus z5,
A gradation waveform is created to drive the liquid crystal display panel 13.

However, in the conventional liquid crystal driving system described above, when the number of dots increases to increase the size of the liquid crystal display panel 13 or increase the screen density, the frequency of the video signal sampling clock must be increased. For example, m x n
Assuming that the sampling frequency of the video signal for a dot liquid crystal display panel is f8, when driving a 2 m x 2 n dot liquid crystal display panel, the sampling frequency must be doubled to 2f3. That is,
In FIG. 3, the frequency f8 of the sampling clocks φ1 and φ8 is set to 1 the effective video signal period tH shown in FIG.
Since sampling is performed 60 times, f s =(t+i/160) Hz. If the liquid crystal display panel is 240 x 320 dots) and the number of picture elements is quadrupled, the sampling wave number f'8
is f, = (tH/320) ”” = 2 f8H
z, which is twice f8. As the sampling frequency increases, current consumption increases and high-speed operation LSI
Many problems arise, such as design and implementation problems, high-frequency noise, etc. In addition, since the sampling frequency of display data differs depending on the dot configuration of the liquid crystal display panel, m
It is necessary to use different LSIs for the Xn-dot liquid crystal television and the 2mx2n-dot liquid crystal television, which increases the cost of the LSI.

[Object of the invention j The present invention has been made in view of the above points, and m
The sampling frequency of display data can be made the same for the dot LCD panel and the 2 m x 2 n dot liquid crystal display i4 channel, and the same LSI can be shared between the two, reducing costs! It is an object of the present invention to provide an image display device which can solve problems such as an increase in current consumption and an increase in high frequency noise.

[Summary of the Invention] The present invention uses two-phase clocks φ1 and φ2 as sampling signals for video signals, and locks each clock φ1 and φ2.
0 [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 6th
In the figure, 21 is an A/D conversion circuit, which converts the video signal sent from the video amplification circuit (not shown) into clock φ1,
Sampling is performed by φ2, and the electrode driving LSI 22a is controlled and scanned.

22b. Also, this LSI? 2a.

Horizontal and vertical synchronization signals are input to 22b from a synchronization circuit (not shown). The above control and scanning electrode drive LSI
22a, 22bf';i.The details will be described later, but the operation mode is specified by mode signals A and B.
A mode signal is given so that the LSI 22a operates in the A mode and the LSI 22b operates in the B mode. The control and scanning type AM dynamic LSIs 22m and 22b are as follows:
Liquid crystal display] 9-channel 23 scanning electrode X I % X1zo
to drive. In this case, the LSI 22 a runs i and is parked
When driving up to l-X60, LSI 22a to L
A timing signal is sent to the SI22b via the signal line 24, and this fl[JILsI22b is connected to the scanning electrode
The liquid crystal shallow water panel 2J has a display electrode of, for example, 2N matrix, and has a configuration of 240 x 320 dots in an IJ box. a, 22
b are signal electrode driving LSIs 26a, 26b, ? through data buses 25a, 25b. 7! L.

27 b, 28 a, 28 b, 29 a, 2
9 Give leather data and display clock to b, and
A chip select signal is given via a signal line (not shown). The signal electrode drive LSIs 26a to 29b are
The signal electrodes Y1 to Y120 of the liquid crystal display panel 23 are driven, and as shown in FIG. 28b drives picture elements f of even-numbered electrodes. Also, LSI 27
a, 29IL drives the picture element c1g of the odd numbered electrode in the signal electrodes ytst to yszo, and LSI27b, 2
9b drives picture elements d and h of even-numbered electrodes.

Next is the control and scanning electrode drive LSI 22a.

22b will be explained in detail. The above LSI 22a.

22b includes an oscillator 3I that generates a reference frequency signal as shown in FIG. A crystal resonator 32 is connected to the oscillator 3I via an external connection terminal only on the LSI 22a side. An oscillator J1 connected to a crystal resonator 32 outputs clocks φ1 and φz via clocked inverters 33a and 33b controlled by a mode signal A, respectively. These clocks φ and φ are used in the internal circuit and are sent to the LSI 22b through the connection terminals 34g and 34b. Further, the LSIs 22a and 22b are provided with a mode designation terminal 35 as shown in FIG. 9, and the source of vDDK6jA or Vss' is switched and inputted by a mode switch 36 or the like. The input to the mode specifying terminal 35 is used as a mode signal B and also as a mode signal A via an inverter 37. Similarly, the control and scanning electrode driving LSI 22a.

22b, as shown in FIG. 10, leather data Io sent from the A/D conversion circuit 2I is temporarily held in the Ink buffer 41.
Clock φ given from 2a via the OR circuit 42
1, the sampling operation is performed by φ2, and the output 1. ~
(2) Send 3 to buffer 4Z as described above. This buffer 41 includes AND circuits 43 and 44 and an OR circuit 45.
Data is read using the clock φIh or φ2 applied via the clock φIh or φ2. In this case, the clock φ1 is passed to the AND circuit 43 and is gate-controlled by the mode signal A, and the clock φ2il-J is passed to the AND circuit 44 and is dart-controlled by the mode signal B. The data held in the buffer 41 is sent to the buffer 46 and output as display data 00 to 03 via a clocked inverter 47 whose gate is controlled by the mode signal B. The buffer 46 also reads input data in synchronization with the clock φ2, and transfers the display data Oo through a clocked inverter 48 operated by the mode signal A.
~03 is output. Display data o output from the clocked inverters 47 and 48.

~03 are output as grayscale signals (16 grayscales) to the data buses 25a and 25b as shown in FIG.

Furthermore, control and scanning electrode drive LSI 22m.

22bVC is provided with a 60-bit shift register 5I as shown in FIG. ii. This shift register 51
A timing signal is input to the first bit of the signal A through a clocked inverter 52 controlled by the mode signal A. The shift register 6Z sequentially shifts the input timing signal in synchronization with the clock pulse, and provides the final bit output to the signal line 54 via the clocked inverter 53 controlled by the motor Ig. This signal line 54 is connected to the SR terminal, and
Clocked impalp control 5 controlled by mode signal B
5 to the input terminal of the shift register 5Z.

The SR terminal is connected between the LSIs 22a and 22b. The contents of the shift register 5I are sent to the display drive circuit 56, and the display drive circuit 56 drives the scanning electrodes X1-X6G or X61-xtzo of the liquid crystal display flat panel 23.

Next, the operation of the above embodiment will be explained. First, first control and scan the dragon'&! , sets the operation mode for the driving LSIs 22a and 22b. That is, LSI 22 a
For mode designation terminal 35 in FIG.
# signal (Vss source) is applied, and for the LSI 22 b, the mode designation terminal 35 is given the ``i'' 4S signal (VDD
source). By applying the II ON signal to the LSI 22ai, t and the mode finger rectangular terminal 35,
Mode signal A output via inverter 37 is 1#
Therefore, the clocked inverters 33 a, 33 b, 4 B, 52 . in FIGS. 8, 10, and 11.
53 and the dart of AND circuit 43 are opened. Also, LSI
22b, when the "Itll signal" is applied to the mode designation terminal 35, the mode signal B becomes "1", and the darts of the clocked inverters 47, 55 and the AND circuit 44 are opened. Since the crystal oscillator 32 is externally connected to the LSI 22a, the LSI 22a generates a reference frequency signal and outputs the two-phase clocks φl and φ2 shown in FIG. 12 via the clocked inverters 338 and 33bf. The LSIs 22a and 22b operate in synchronization with these clocks φ1 and φ2. The above clocks φ1 and φ2 are
It is sent to the conversion circuit 2I via the OR circuit 42 in the LSI 22a. This lv'DK control circuit 2I performs a sampling operation in synchronization with the clocks φ[, φ2, and outputs the sampling data ro to 1. LSI22a
, 22b to the buffer 4I. As described above, sampling is performed using the clocks φ1 and φ2, so if the frequency of the clocks φ1 and φ2 is f8, the sampling data ①o-I3 changes at 2 fs as shown in FIG. In other words, the video signal is sampled at 2fa. And the above sampling data ■0
In the LSI 22a to which .about.3 is input, since the dart of the AND circuit 43 is opened by the mode signal A in FIG. 10, the clock φ[ is applied to the buffer 41.

Therefore, sampling data 1. ~I3 is clock φl
It is read into the buffer 41 in synchronization with φ2, and after 7, it is read into the buffer 46 in synchronization with φ2. 7, the data read into this buffer 46, that is, the data sampled by clock φ1 becomes display data OI.
~03 is outputted to the data bus 25th via the clocked inverter 48, and the signal 'electrode is driven to SI26.
a % 27 a s 2 B a429 a sent to. On the other hand, in the LSI 22 b, the dart of the AND circuit 44 is opened by the motor controller g B, and the clock φ2 is applied to the buffer 41. Therefore, the sampling data IO to I3 are read into the buffer 41 in synchronization with the clock φ2.

The data read into this buffer 41, that is, the data sampled by the clock φ2, is transferred as display data 01 to 03 to the data bus 25b via the clocked inverter 47 controlled by the mode signal B.
signal electrode drive LSI26b, 27h, 28
b, sent to 29b. That is, clock φ1 or φ
The data l0-I, sampled by LS
As shown in FIG. 12, the display data I22a and 22b are output as display data Oo to 03 synchronized with the clock φ2, respectively. The signal electrode driving LSIs 26a, 27
as 28as 29h is based on 7-'-ta sampled by Kuro and Riφ1! llLCD display/yanel 2
3 odd numbered signal turtle 'JjIIA Y t -Y
s II Y 6% °”'YI6L Y163
%Yll18%... is driven, and the signal electrode drive LSI
26b, 27b.

28b and 29b are the even-numbered electrodes Y2 s Y4 based on the data sampled by the clock φ2.
%Y@・"'yts*1Y164% Y166%"゛° is driven.

Further, the collateral and scanning electrode driving LSI 22a is the first
In FIG. 1, a timing signal synchronized with a vertical synchronization signal is input to a shift register 5I via a clocked inverter 52. This shift register 51 reads the timing signal into the first bit, and thereafter sequentially shifts it in synchronization with the clock signal. The data held in the shift register 51 is sent to the display drive circuit 56, and the scan electrodes X1 to xeo of the product display/gunnel 23 are sequentially driven in accordance with the position of l"1g shifted in the shift register 51. When the read data of the shift register 50 is shifted to the most significant bit, it is output to the signal line 54 via the clocked inverter 53, and further sent to the SR terminal of the LSI 22b via the SR terminal.LSI 22 In b, since the dart of clocked inverter 55 is opened by mode signal B, LS
The signal sent from I22a is sent to shift register 5.
It is input to the 1st bit of 1.

Then, the signal input to the shift register 5Z is shifted by one order within the shift register 51 in synchronization with the clock pulse. By this shift operation of the shift register 51, the scan electrodes X61 to X12o of the liquid crystal display channel 23 are sequentially driven via the display drive circuit 56. Similarly, No. 100 electrode Y1=Ysxo of the liquid crystal shallow water panel 23
, the scanning electrodes X1 to X120 are driven, and the display data O
Sea bream corresponding to numbers 1 to 03 are displayed.

[Effect of the Invention J As described above, according to the present invention, two-phase clocks φ1 and φ2 are used as video signal sampling signals, and seven clocks are sampled with each clock φ1 and φ2. Since the display data is obtained, the frequency of the sampling clock can be doubled by the power ≧, and the display frequency of m × n dots and the display of 2 m × 2 n dots) +
The sampling frequency of display data can be made the same for each channel. Therefore, the cost can be reduced by using the same LSI for two types of display channels. Also, 2
Even if an m x 2 n dot display channel is used, since the sampling frequency remains the same, an increase in current consumption and an increase in frequency noise can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of a conventional image display device, and FIG. 2 is a block diagram showing the circuit configuration of a conventional image display device. 3 is a diagram showing the main parts of the A/D conversion circuit and control and scanning electrode driving LSI in FIG. 1, and FIGS. 4 and 5 are diagrams showing the operation of the conventional device described above. Figures 6 to 12, which are for explanation only, show examples of the present invention. Figure 6 is a block diagram showing the circuit configuration, and Figure 7 is a liquid crystal display panel and electrode assembly MLSI. 8 to 1I are diagrams showing the connection relationship with the control and scanning electrode drive LSI.
FIG. 12 is a timing chart for explaining the operation. z r-MD fatigue circuit, 2z a, 22 b-*
+1n and scanning electrode drive LSI, 23...Liquid crystal display panel, 25h, 25b-...Data node, 26a
, 26b. 27a, 27b, 28a, 28b, 29a. 29b...Signal polar drive LSI, 3Z...) 6-oscillator, 32...Crystal resonator, 41.46...Nonotsufa,
5I...Shift control Zostar, 56...Display 1 drive circuit. Applicant's agent Patent attorney Suzue Takehiko No. 31'' Fig. 5 Heap -------+ No. 41) -'1 0o-03-Yu 11-Δn-n+ Fig. 8 Fig. 9 Figure 11 Figure 12

Claims (3)

[Claims] (1) In an image display device that samples a video signal and drives a display panel having a 92m x 2n dot configuration using the sampled data, means for sampling the video signal alternately using two-phase clocks φ1 and φ2; An image display device comprising: means for driving a display panel according to sampled data, and the frequency of the sampling clock is apparently doubled. (2) The means for driving the above display/gunnel is the clock φ
It consists of a first display drive circuit that accepts the data sampled at clock φ2 and drives the display i4 channel, and a second display drive circuit that accepts the data sampled at clock φ2 and drives the display panel. The image display device according to claim 1, characterized in that the operation mode of the second display driving circuit can be specified by external mode No. 115. (3) In an image display device that samples video No. 4g and uses the sampling data to drive a display/main channel having a 2 m x 2 n dot configuration, the video signal is sent to the two-phase clock φ screen, φ. Also, means for mutually sampling, a first scanning electrode driving LSI that reads the data sampled by this means at clock φ1 and outputs it to the data bus at clock φ3, and a first scan electrode driving LSI that reads the sampled data at clock φ2 and outputs it to the data bus at clock φ2. a second scan electrode driving LSI for outputting data to a second scan electrode driving LSI; First and second scan electrode drive LSI
The n-bit 1% second shift register provided in each of means for manually constructing a 2n-bit shift register in the shift register; and means for driving 2n-bit scanning electrodes of the display panel in accordance with signals sequentially shifted in the J-th and second shift registers;
The oscillator is operated only in the first scan electrode driving LSI to generate the two-phase clocks φ1 and φ2, and the two-phase clocks φ1 and φ2 are generated.
An image display device comprising means for synchronously operating the first and second scan electrode drive LSIs using phase clocks φl and φ2.