JPH10271419A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the display device by which video signals with same phase accuracy and different aspect ratios are displayed on a same liquid crystal display panel without the need for changing a frequency of a clock signal generated by a control IC circuit between a video image whose aspect ratio is 9:16 and a video image whose aspect ratio is 3:4. SOLUTION: A PLL 52 generates a reference clock signal forg with a frequency synchronously with a video signal to be displayed and twice number of pixels in a horizontal direction of an image whose aspect ratio is, e.g. 9:16. The reference clock signal is frequency-divided by 1/2 at a timing generating circuit 53 to produce a 1st clock signal f1 corresponding to the aspect ratio of 9:16 and frequency-divided by 2/3 at the timing generating circuit 53 to produce a 2nd clock signal f2. Then the 1st/2nd clock signal f1/f2 is selectively given to a signal line driving circuit in response to an aspect ratio of a given video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention particularly has a liquid crystal display panel having an aspect ratio of 9:16.
The present invention relates to a liquid crystal display device having a plurality of aspect display modes including an aspect ratio of 1.

[0002]

2. Description of the Related Art A horizontally long liquid crystal display panel having a vertical to horizontal ratio of a display screen, that is, an aspect ratio of 9 to 16, is used in, for example, a high-definition television receiver. However, when a television receiving signal having a normal aspect ratio of 3: 4 is supplied to such a liquid crystal display panel having an aspect ratio of 9:16, an image stretched in the horizontal direction is displayed, and a 3: 4 aspect ratio is displayed. Images are not displayed with the correct aspect ratio. For example, an image of a perfect circle included in an image having an aspect ratio of 3: 4 is 9:16.
When displayed at an aspect ratio of, a horizontally elongated circle elongated in the horizontal direction is obtained. Therefore, in such a case, the 9: 1 aspect ratio of the liquid crystal display panel having a 9:16 aspect ratio is used.
The mode is switched so that an image having an aspect ratio of 3 to 4 is displayed using only the portion of 2 (= 3 to 4).

[0003] Even if the aspect ratios are different, if a clock signal having a different frequency corresponding to each aspect ratio is generated within one horizontal scanning period of a given video signal and supplied to the signal line driving circuit, each clock signal is generated. An image can be displayed correctly according to the aspect ratio.

Conventionally, an output voltage of a PLL circuit synchronized in phase with a horizontal synchronizing signal included in a video signal is supplied to, for example, one voltage controlled oscillator (VCO), and the output voltage is changed to change the aspect ratio. Are oscillated at different frequencies.

That is, when the frequency required for displaying an image having an aspect ratio of 9:16 and 3: 4 on the liquid crystal display panel is 9:16, fl is assumed, N is the number of pixels, and N is the number of pixels.
Assuming that T is a data capture period, T is represented by (1 / fl) × N = T (1).

Similarly, if the aspect ratio is 3: 4 and if f2 is a frequency in the case of 3: 4, the number of pixels required here is (3/4) .times.N. Since (1 / f2) × (3/4) × N = T, (3 × N) / (4 × f2) = T (2)

Accordingly, the left sides of the equations 1 and 2 are equal, and if the frequency forg expressed here is used as a reference clock frequency, the following relationship is obtained: 3 × fl = 4 × f2 = forg (3)

From these three equations, a video signal having an aspect ratio of 9:16 is three times the reference clock frequency forg, and
It can be seen that a 3: 4 video signal requires a clock pulse signal having a quadruple frequency.

In order to obtain such two types of clock pulse signals, as described above, in the prior art, it has been responded by changing the oscillation frequency of the VCO oscillator.

[0010]

However, in this method, since the frequency of the clock signal oscillated by the VCO of the PLL circuit becomes two types, a control IC used for controlling the scanning line and the signal line driving circuit is used. The unit must be operated with these two different frequency clock signals, and it is difficult to always maintain the phase accuracy when these clock signals are generated. Required. As a result, the circuit configuration becomes complicated and the manufacturing cost increases.

Therefore, according to the present invention, it is possible to form a clock signal having a plurality of frequencies and a high phase accuracy with a simple circuit configuration corresponding to a plurality of kinds of video signals having different aspect ratios including 9:16. It is an object of the present invention to provide a liquid crystal display device which can be used.

[0012]

According to the present invention, there is provided a liquid crystal display panel including an effective display area having a predetermined aspect ratio and comprising a plurality of horizontal pixel lines each having a plurality of display pixels arranged therein. Means for generating a reference clock signal in which a first frequency related to one horizontal scanning period and the number of display pixels forming the one horizontal pixel line is multiplied by a positive number greater than 1; A first frequency divider for dividing a signal to generate a first clock signal having the first frequency; and a second frequency divider dividing the reference clock signal and forming a second frequency smaller than the first frequency. Second frequency dividing means for generating a clock signal, selecting means for selectively outputting the first clock signal and the second clock signal, and selecting the serial video signal to be inputted for each of the horizontal pixel lines. And a video signal supply circuit for supplying a serial-parallel conversion to display signals to the display pixels corresponding based on the clock signal from the unit.

With the above arrangement, a reference clock signal is generated in synchronization with the video signal to be displayed and having a frequency which is a predetermined positive multiple of the number of pixels in the horizontal direction, and this reference clock signal is frequency-divided. Generating a first clock signal, wherein the reference clock signal is a second clock signal smaller than the first clock signal;
And a second clock signal is formed by dividing the frequency into a second clock signal, and the first and second clock signals can be selectively used in accordance with a given video signal to perform video signal display control, and each has high phase accuracy. The first and second clock signals can be obtained with a simple circuit configuration.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display device 10 according to the first embodiment. In FIG. 1, a liquid crystal display device 10 has, for example, an aspect ratio of 9:
A video signal source 40 which is incorporated in a TV receiver having 16 liquid crystal panels, generates a high definition video signal for displaying an image having an aspect ratio of 9:16 together with a synchronization signal, and displays an image having an aspect ratio of 3: 4. NTS for
It is connected to a video signal source 41 that generates a video signal of the C system together with a synchronization signal.

These video signal sources 40 and 41 are connected to the TV
A receiving circuit for a Hi-Vision and NTSC television signal incorporated in a receiver, or reading a Hi-Vision video signal or an NTSC video signal connected to the outside of a TV receiver from a storage medium such as a magnetic tape or a disk. It is a playback device.

The liquid crystal display device 10 comprises a liquid crystal panel 30 having a screen aspect ratio set to 9:16 and a panel control unit CNT for controlling the liquid crystal panel 30 based on a high definition video signal and an NTSC video signal. .

In the liquid crystal display device 10, a high-vision signal image having an aspect ratio of 9:16 is displayed on the entire screen of the liquid crystal panel 30 as shown in FIG. 2A, and an NTSC signal image having an aspect ratio of 3: 4 is displayed. As shown in FIG. 2B, the image is displayed in a region I on the left side of the screen, which is 3/4. For example, character information and the like are displayed in the remaining area II.

In FIG. 1, a liquid crystal display panel 30 has a plurality of pixel electrodes 31 arranged in a matrix, a plurality of scanning lines 33 formed along the row direction of these pixel electrodes 31 for transmitting a scanning signal, and a plurality of pixel electrodes 31. 31 and a plurality of signal lines 34 formed along the column direction,
3 and an array substrate including a plurality of switching elements 32 formed corresponding to intersections with the signal lines 34. The liquid crystal display panel 30 includes a counter substrate (not shown) including a counter electrode facing the plurality of pixel electrodes 31 of the array substrate, and a liquid crystal layer held between the array substrate and the counter substrate.

Each switching element 32 includes a gate and a signal line 34 connected to a scanning line 33 and a pixel electrode 31.
It is constituted by a thin film transistor (TFT) having a current path connected therebetween, and is turned on by a scanning signal supplied through the scanning line 33, and the potential of the signal line 34 set according to the display signal is changed to the pixel electrode 31. Is applied.

The screen of the liquid crystal display panel 30 is composed of a plurality of pixels consisting of a plurality of pixel electrodes 31, switching elements 32 respectively corresponding to the pixel electrodes 31, a liquid crystal layer portion, and a counter electrode portion. The light transmittance of the layer is controlled by the potential difference between the pixel electrode 31 and the counter electrode.

The panel control unit CNT includes a control IC unit 14, a video selection circuit 15, a first switch circuit 16, a second switch circuit 17, a video signal processing circuit 19, a signal line drive circuit 20, and a scan circuit, which will be described in detail later. The line drive circuit 21 is included.

The image selection circuit 15 has an aspect ratio of 9:16.
This is a circuit for selecting whether display is to be performed or display in 3: 4. For example, the first and second switch circuits 16 and 17 are switched according to a user's manual designation operation to generate a high-definition video signal. Source 40 and NT
One of the output signals of the SC video signal source 41 is supplied to the video signal processing circuit 19.

The switching contact of the first switch circuit 16 is connected to the control IC unit 14, and a horizontal synchronizing signal of the selected Hi-Vision or NTSC video signal is supplied to the control IC unit 14. Note that a display mode switching signal is generated from the video selection circuit 15 in accordance with the user's manual designation operation,
This is supplied to a switching circuit in the control IC unit 14 described later.

The video signal processing circuit 19 is a control IC
It receives a clock signal of an appropriate frequency according to the selected aspect ratio from the unit 14, and further performs video signal processing such as gamma correction to appropriately drive the liquid crystal panel 30.

The scanning line driving circuit 21 also receives a clock signal of a predetermined frequency from the control IC unit 14 and performs a driving operation for sequentially supplying scanning signals to the plurality of scanning lines 33 in response to the clock signal.

The signal line drive circuit 20 includes a clock signal CPH and a horizontal start signal S of appropriate frequencies corresponding to the aspect ratio selected from the control IC unit 14.
Upon receiving TH, the video signals supplied from the video signal processing circuit 19 are sequentially sampled and held, and a driving operation for driving the plurality of signal lines 34 is performed in accordance with the video signals.

The signal line driving circuit 20 includes first to fourth driver ICs 2 for driving signal line blocks formed by dividing all the signal lines 34 into four groups.
0a-2Od.

First to fourth driver ICs 20a-20
d is a plurality of flip-flops connected in series with each other for transmitting the horizontal start signal STH supplied from the control IC unit 14 and connected in series corresponding to the plurality of signal lines 34 for one block. It has at least one shift register configured. Each shift register performs a shift operation of the horizontal start signal STH in response to the clock signal CPH.

FIG. 3 shows the circuit configuration of the control IC unit 14 in detail. This control IC unit 1
Reference numeral 4 denotes a PL for obtaining an output signal that is phase-synchronized with the horizontal synchronization signal H included in the video signal from the HDTV video signal source 40 or the video signal from the NTSC video signal source 41.
It has an L circuit 52. The output signal of the PLL circuit 52 is a high-vision video signal source 4 having an aspect ratio of 9:16.
Video signal from 0 or NTS with aspect ratio 3: 4
A timing generation circuit 5 for generating a clock signal used to display a selected video signal of the video signals from the C video signal source 41 at a predetermined aspect ratio.
3 to be supplied.

The PLL circuit 52 is configured as shown in FIG. 4, and detects a phase error between a horizontal synchronizing signal H supplied from the switch circuit 16 and a reference horizontal clock signal supplied from the counter 55 in a phase comparing circuit 54. Then, an error signal corresponding to the phase error is supplied to the loop filter 56 to generate a signal voltage obtained by removing high-frequency components and noise from the error signal, and this signal voltage is supplied to the VCO 57 to correspond to the signal voltage. A pulse signal having an oscillating frequency is generated as a reference clock signal forg.

The counter 55 divides the frequency of the reference clock signal forg based on the number of pixels in one row and supplies the frequency-divided reference clock signal to the phase comparison circuit 54 as a reference horizontal clock signal.

The reference clock signal forg obtained from the VCO 57 is further supplied to a timing generation circuit 53.

As shown in FIG. 5, the timing generating circuit 53 forms a first clock signal having a first frequency f1 and a second clock signal having a second frequency f2 based on the reference clock signal ford. A first generation circuit 62 and a second generation circuit 63 for performing the operation. These first and second clock signals f1 and f2 are supplied to the CPH switching circuit 64, switched based on the mode switching signal M from the video selection circuit 15, and output as CPH.

As shown in FIG. 6, the first generating circuit 62 is a frequency dividing circuit for reducing the frequency of the reference clock signal forg to を to form the first clock signal f1.
The first clock signal f1 having half the frequency of the reference clock signal forg shown in FIG.
Is shown in Each of these clock signals has a duty ratio set to 1/2, but this duty ratio can be set to an appropriate value.

As will be described later in detail, the first clock signal f1 is a clock synchronized with a given video signal and having a frequency corresponding to the number of pixels in the horizontal direction of an image having an aspect ratio of 9 to 16. Therefore, the reference clock signal forg is a reference clock signal synchronized with a given video signal and having a frequency twice the number of horizontal pixels of an image having an aspect ratio of 9 to 16.

The configuration and operation of the second generation circuit 63 of FIG. 5 for generating the second clock signal f2 will be described below with reference to FIGS. 7 and 8.

First, the frequency of the reference clock signal forg is divided into 1/6 using the 1/6 frequency divider 71 in FIG.
A clock signal S1 as shown in FIG. 7C is formed.

The 1/6 frequency divider 71 sets, for example, a flip-flop (not shown) at the rise of the first reference clock signal "forg", and simultaneously counts the reference clock signal "forg" using a 3 counter (not shown).
The carry of the counter is changed to the fourth reference clock signal for
The configuration can be easily realized by giving the signal to the flip-flop at the rising edge of g to reset the flip-flop and setting the flip-flop again at the rising edge of the seventh reference clock signal forg.

Next, the phase of the clock signal S1 obtained in this manner is supplied from the 1/6 frequency divider 71 to the phase shifter 72, and is delayed by one cycle of the reference clock signal forg. The clock signal S2 as shown in d) is formed.

When the two types of clock signals S1 and S2 thus formed are supplied to the EXOR circuit 73, they rise in synchronization with the rising of the signal S1, as shown in FIG. Clock signal A1 falling in synchronism with the clock signal A1 is obtained. This clock signal A1 is then sent to the phase shifter 74 to delay it by one period of the reference clock signal forg to form a clock signal A2 as shown in FIG.

The clock signal A2 formed as described above is supplied to another flip-flop 75, and in this state, at the falling timing of the reference clock signal forg, the signal shown in FIG.
A clock signal A3 as shown in FIG.
The falling of the clock signal A3 is caused by the clock signal A2
The clock signal A3 as shown in FIG. 7 (g) is formed at the timing of the first fall of the reference clock signal forg after the fall.

The two types of clock signals A1 and A3 thus formed are supplied to an OR circuit 76, and a second clock signal f2 as shown in FIG. 7H is formed. The second clock signal f2 is shown in FIG.
As can be seen from (h), the reference clock signal has a frequency that is 2/3 of the frequency of the reference clock signal.

The first and second clock signals f1 and f2 are supplied to the CPH switching circuit 64 shown in FIG.
Switching is performed based on the mode switching signal M from the video selection circuit 15 and output as CPH.

In order to drive the liquid crystal display panel 30 shown in FIG. 1, control signals such as CPH signal and STH signal for controlling the scanning line driving circuit 21 and the signal line driving circuit 20 according to the aspect ratio are sent from the control IC unit 14. It is necessary to supply.

The CPH signal, which is one of the signal line drive signals, is a sampling clock signal that the signal line drive circuit 20 takes in a video signal as a display signal of the liquid crystal display panel 30. That is, a signal line drive signal is supplied from the control IC unit 14 into the signal line drive circuit 20, and a scan line drive signal is generated and supplied to the scan line drive circuit 21 based on the synchronization signal H.

The timing generation circuit 53 constituting a part of the control IC unit 14 supplies a control signal to the scanning line driving circuit 21 and the signal line driving circuit 20 by a clock signal supplied from the PLL circuit 52. A sampling clock signal CPH, which is one of the control signals, is generated by a timing generation circuit 53.

As described above, the sampling clock signal CPH has two kinds of clock signals f1 and f2 having two frequencies.
The CPH switching circuit 64 switches and outputs the required clock signal f1 or f2.

Here, the relationship between these clock signals f1 and f2 and the reference clock signal forg is shown by an equation.

First, when both sides are divided by 6 in the above-mentioned three equations, forg = (3/6) × fl = (4/6) × f2, so that forg = (1/2) × f1 = (2 / 3) × f2 (4)

That is, the frequency obtained by dividing the reference frequency forg by two is the frequency fl, 2 /
3, that is, 1.5 frequency division, the aspect ratio is 3: 4
Frequency f2.

In FIG. 1, a high-vision video signal source 40 is shown.
In order to display an image having an aspect ratio of 9:16 generated on the liquid crystal display panel 30 on the liquid crystal display panel 30, a mode switching signal M is supplied from the video selection circuit 15 to the CPH switching circuit 64 of the control IC unit 14, and the first The clock signal of the frequency fl from the generation circuit 62 is supplied to the signal line drive circuit 20 as a CPH signal. As a result, an image having an aspect ratio of 9:16 is displayed on the liquid crystal display panel 30 as shown in FIG.

When displaying an image having an aspect ratio of 3: 4 generated from the NTSC image signal source 41 on the liquid crystal display panel 30, the image selection circuit 15 sends a mode to the CPH switching circuit 64 of the control IC unit 14. The switching signal M is supplied, and the clock signal of the frequency f2 from the second generation circuit 63 is supplied to the signal line driving circuit 20 as the CPH signal. As a result, the liquid crystal display panel 3
0 has an aspect ratio of 3: 4 as shown in FIG.
Is displayed.

As described above, the first generation circuit 6 shown in FIG.
By switching the fl and f2 clock signals obtained from the second and second generation circuits 63 by the CPH switching circuit 64, the frequency for controlling the control IC unit 14 is not changed, and the frequency is changed to one reference clock signal frequency forg. , The CPH signals f1 and f2 can be generated.

[0055]

As described in detail above, according to the present invention,
Since there is no need to change the frequency of the clock signal generated by the control IC circuit when displaying images having aspect ratios of 9:16 and 3: 4, the means for generating control signals to be supplied to the inside and outside of the control IC circuit is simple. become,
In addition, it is possible to provide a liquid crystal display device that displays video signals having the same phase accuracy and different aspect ratios of 9:16 and 3: 4 on the same liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a method of displaying images having aspect ratios of 9:16 and 3: 4 on the same liquid crystal display panel.

FIG. 3 is a block diagram showing a part of the internal configuration of the control IC unit shown in FIG. 1;

FIG. 4 is a block diagram showing an example of the internal configuration of the PLL in FIG. 3;

FIG. 5 is a block diagram showing an example of an internal configuration of the tamping generation circuit of FIG. 3;

FIG. 6 is a block diagram showing an example of a first generation circuit of FIG. 5;

FIG. 7 is a time chart showing an operation of the second generation circuit shown in FIG. 8;

FIG. 8 is a block diagram showing an example of a second generation circuit of FIG. 5;

[Explanation of symbols]

 14 Control IC Unit 20 Signal Line Drive Circuit 21 Scan Line Drive Circuit 30 Liquid Crystal Display Panel 57 VCO 62 First Generation Circuit 63 Second Generation Circuit

Claims (4)

[Claims] 1. A liquid crystal display panel including an effective display area having a predetermined aspect ratio and comprising a plurality of horizontal pixel lines in which a plurality of display pixels are arranged; one horizontal scanning period; and one horizontal pixel line. Means for generating a reference clock signal obtained by multiplying a first frequency related to the number of display pixels constituting the first clock signal by a positive number greater than 1; and dividing the reference clock signal to form the first frequency. A first frequency divider for generating a first clock signal; a second frequency divider for dividing the reference clock signal to generate a second clock signal having a second frequency smaller than the first frequency; Selecting means for selecting and outputting the first clock signal and the second clock signal; and for each of the horizontal pixel lines, a serial video signal input corresponding to the horizontal pixel line based on the clock signal from the selecting means. The liquid crystal display device characterized by comprising a video signal supply circuit for supplying a serial-parallel conversion shite display signal to the display pixel. 2. An aspect ratio of the effective display area is 9: 2.
The liquid crystal display device according to claim 1, wherein the number is 16. 3. The liquid crystal display device according to claim 2, wherein the positive number is 2, and the second frequency is 4/3 of the first frequency. 4. The liquid crystal display device according to claim 1, wherein the means for generating the reference clock signal comprises a PLL circuit.